KR970067783A - LOC(lead on chip)유형의 적층 칩 패키지 - Google Patents

LOC(lead on chip)유형의 적층 칩 패키지 Download PDF

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Publication number
KR970067783A
KR970067783A KR1019960006069A KR19960006069A KR970067783A KR 970067783 A KR970067783 A KR 970067783A KR 1019960006069 A KR1019960006069 A KR 1019960006069A KR 19960006069 A KR19960006069 A KR 19960006069A KR 970067783 A KR970067783 A KR 970067783A
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South Korea
Prior art keywords
loc
inner leads
chip
chip package
electrical connection
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KR1019960006069A
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English (en)
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KR100204753B1 (ko
Inventor
안민철
정도수
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960006069A priority Critical patent/KR100204753B1/ko
Priority to JP8347854A priority patent/JPH09246465A/ja
Priority to US08/811,150 priority patent/US5804874A/en
Publication of KR970067783A publication Critical patent/KR970067783A/ko
Application granted granted Critical
Publication of KR100204753B1 publication Critical patent/KR100204753B1/ko

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 적층 칩 패키지에 관한 것으로, LOC 기술을 적용하여 칩들 간의 상호 전기적 연결되도록 적층함으로써, 리드프레임의 내부리드의 과도한 절곡 및 횟수가 감소되고, 각 전기적 연결 구조들의 순차적 적층에 있어서, 그 구조들 간의 전기적 간섭을 최소화할 수 있는 동시에 그 구조들 간의 적층 높이가 최소화되어 패키지의 두께가 박형화될 수 있고, 패키지의 제조 단가를 낮출 수 있는 동시에 신뢰성이 보장된 패키지를 제조할 수 있는 장점을 갖는다.

Description

LOC(Lead on chip)유형의 적층 칩 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 일 실시에에 의한 LOC 유형의 적층 칩 패키지를 나타내는 평면도.

Claims (11)

  1. 복수개의 본딩 패드들을 갖는 상부 칩, 및 그 상부 칩의 본딩 패드들이 형성된 면까지 연장되어 그 상부 칩과 접착되어 있으며, 각기 대응된 상기 본딩 패드들에 각기 전기적 연결된 상부 내부리드들을 포함하는 상부 전기적 연결 구조; 복수개의 본딩 패드들을 갖는 하부 칩, 그 하부 칩의 본딩 패들들이 형성된 면까지 연장되어 그 하부 칩과 접착되어 있으며, 각기 대응된 상기 본딩 패드들에 각기 전기적 연결된 하부 내부리드들, 및 그 하부 내부리드들에 일체로 형성된 외부리드를 포함하는 하부 전기적 연결 구조; 및 상기 하부 내부리드들과 상기 상부 칩간에 개재. 접착된 절연 필름을 포함하며, 상기 상부 내부리드들이 절곡되어 그 상부 내부리드들에 각기 대응된 상기 하부 내부리드들의 상부면에 전기적 연결된 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  2. 제1항에 있어서, 상기 상부 칩이 각기 상기 상부 내부리드들과 각기 접착된 수단이 폴리이미드 테이프인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  3. 제1항에 있어서, 상기 하부 칩이 각기 상기 하부 내부리드들과 각기 접착된 수단이 폴리이미드 테이프인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  4. 제1항에 있어서, 상기 상부 내부리드들이 그들에 각기 대응된 상기 하부 내부리드들과 전기적 연결되기 위해 절곡된 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  5. 제1항 또는 제4항에 있어서, 상기 상부 내부리드들과 그들에 각기 대응된 상기 하부 내부리드들을 각기 전기적 연결하는수단이 전도성 재질인 범프인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  6. 제5항 있어서, 상기 범프의 재질이 솔더인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  7. 제1항에 있어서, 상기 본딩 패드들과 그들에 각기 대응된 내부리드들을 각기 전기적 연결하는 수단이 본딩 와이어인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  8. 제1항 또는 제7항에 있어서, 상기 절연 필름이 상기 하부 전기적 연결 구조의 본딩 와이어들과 상기 상부 칩의 하부면이 기계적으로 접촉되지 않도록 형성된 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  9. 제8항에 있어서, 상기 절연 필름의 재질이 양면 접착성 폴리이미드인 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  10. 제1항에 있어서, 상기 상부 전기적 연결 구조와 상기 하부 전기적 연결 구조가 에폭시 성형 수지에 의해 봉지된 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
  11. 제10항에 있어서, 상기 하부 전기적 연결 구조의 외부리드들이 상기 성형 수지에 대하여 노출된 것을 특징으로 하는 LOC 유형의 적층 칩 패키지.
KR1019960006069A 1996-03-08 1996-03-08 엘오씨 유형의 적층 칩 패키지 KR100204753B1 (ko)

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JP8347854A JPH09246465A (ja) 1996-03-08 1996-12-26 Ｌｏｃ型半導体チップの積層チップパッケージ
US08/811,150 US5804874A (en) 1996-03-08 1997-03-04 Stacked chip package device employing a plurality of lead on chip type semiconductor chips

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