KR970063688A - 패턴닝된 리드프레임을 이용한 멀티 칩 패키지 - Google Patents

패턴닝된 리드프레임을 이용한 멀티 칩 패키지 Download PDF

Info

Publication number
KR970063688A
KR970063688A KR1019960003953A KR19960003953A KR970063688A KR 970063688 A KR970063688 A KR 970063688A KR 1019960003953 A KR1019960003953 A KR 1019960003953A KR 19960003953 A KR19960003953 A KR 19960003953A KR 970063688 A KR970063688 A KR 970063688A
Authority
KR
South Korea
Prior art keywords
lead frame
chip package
lead portions
chips
bonding pads
Prior art date
Application number
KR1019960003953A
Other languages
English (en)
Other versions
KR100203934B1 (ko
Inventor
서정우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960003953A priority Critical patent/KR100203934B1/ko
Priority to JP9025311A priority patent/JPH09232508A/ja
Priority to US08/799,355 priority patent/US5780926A/en
Publication of KR970063688A publication Critical patent/KR970063688A/ko
Application granted granted Critical
Publication of KR100203934B1 publication Critical patent/KR100203934B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 멀티 칩 패키지에 관한 것으로, 리드프레임 상에 실장된 복수개의 칩들 간의 전기적 연결이 되도록 상기 리드프레임 상에 메탈 금속층과 절연층들을 적층ㆍ형성함으로써, 리드프레임 상에 미세 패턴을 제조할 수 있기 때문에 패키지의 두께가 감소되고, 그 리드프레임 상에 실장되는 칩들의 수를 증대할 수 있으며, 별도의 공통 회로 기판이 요구되지 않기 때문에 패키지 제조 공정의 단축 및 패키지의 제조 단가를 낮출 수 있는 장점을 갖는다.

Description

패턴닝된 리드프레임을 이용한 멀티 칩 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제12도는 본 발명의 패턴닝된 리드프레임의 제조 단계를 나타내는 도면이다.

Claims (7)

  1. 복수개의 본딩 패드들을 갖는 복수개의 칩들; 복수개의 리드부들, 그 리드부들의 상하면 상에 적층ㆍ형성 되어 있으며, 일단에 비아 홀들을 갖는 내부 절연층들, 그 내부 절연층들의 상하면 상에 적층ㆍ형성되어 있으며, 각기 대응된 상기 본딩 패드들과 상기 각기 대응된 비아 홀들에 의해 각기 전기적 연결된 패턴들, 및 그 패턴들의 상하면 상에 적층ㆍ형성되어 있으며, 상부면에 각기 이격되어 상기 칩들의 하부면과 접착된 외부 절연층을 포함하는 리드프레임; 및 상기 칩들과 상기 리드프레임이 내재ㆍ봉지된 봉지 수단을 포함하는 것을 특징으로 하는 패턴닝된 리드프레임을 이용한 멀티 칩 패키지.
  2. 제1항에 있어서, 상기 리드프레임이 상기 리드부들이 형성된 동일 평면 상에 지지부가 형성된 것을 특징으로 하는 패턴닝된 리드프레임을 이용한 멀티 칩 패키지.
  3. 제2항에 있어서, 상기 절연층이 PDR인 것을 특징으로 하는 패턴닝된 리드프레임을 이용한 멀티 칩 패키지.
  4. 제1항에 있어서, 상기 외부 절연층들이 상기 각 칩들의 본딩 패드들과 그들에 각기 대응된 패턴들 간의 전기적 연결을 위하여 일부ㆍ노출된 것을 특징으로 하는 패턴닝된 리드프레임을 이용한 멀티 칩 패키지.
  5. 제1항에 있어서, 상기 비아 홀들이 그들에 각기 대응된 상기 패턴들 및 리드부들의 상ㆍ하부면 상에 기계적 접촉되도록 형성되어 각기 전기적 연결된 것을 특징으로 하는 패턴닝된 리드프레임을 이용한 멀티 칩 패키지.
  6. 제1항 또는 제5항에 있어서, 상기 리드부들이 그들에 각기 대응된 상기 비아 홀들과 동시에 전기적 연결된 것을 특징으로 하는 패턴닝된 리드프레임을 이용한 멀티 칩 패키지.
  7. 제1항에 있어서, 상기 봉지 수단이 에폭시 성형 수지인 것을 특징으로 하는 패턴닝된 리드프레임을 이용한 멀치 칩 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960003953A 1996-02-17 1996-02-17 패턴닝된 리드프레임을 이용한 멀티 칩 패키지 KR100203934B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019960003953A KR100203934B1 (ko) 1996-02-17 1996-02-17 패턴닝된 리드프레임을 이용한 멀티 칩 패키지
JP9025311A JPH09232508A (ja) 1996-02-17 1997-02-07 パターン金属層と絶縁層を積層してなるリードフレームを用いたマルチチップパッケージ
US08/799,355 US5780926A (en) 1996-02-17 1997-02-14 Multichip package device having a lead frame with stacked patterned metallization layers and insulation layers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960003953A KR100203934B1 (ko) 1996-02-17 1996-02-17 패턴닝된 리드프레임을 이용한 멀티 칩 패키지

Publications (2)

Publication Number Publication Date
KR970063688A true KR970063688A (ko) 1997-09-12
KR100203934B1 KR100203934B1 (ko) 1999-06-15

Family

ID=19451430

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960003953A KR100203934B1 (ko) 1996-02-17 1996-02-17 패턴닝된 리드프레임을 이용한 멀티 칩 패키지

Country Status (3)

Country Link
US (1) US5780926A (ko)
JP (1) JPH09232508A (ko)
KR (1) KR100203934B1 (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
JPH1168031A (ja) * 1997-08-11 1999-03-09 Mitsubishi Electric Corp Ｉｃモジュールおよび半導体部品
SG88741A1 (en) * 1998-09-16 2002-05-21 Texas Instr Singapore Pte Ltd Multichip assembly semiconductor
TW409330B (en) * 1999-03-20 2000-10-21 United Microelectronics Corp Repairable multi-chip module package
US6473310B1 (en) * 2000-02-18 2002-10-29 Stmicroelectronics S.R.L. Insulated power multichip package
US7181287B2 (en) * 2001-02-13 2007-02-20 Second Sight Medical Products, Inc. Implantable drug delivery device
US6603072B1 (en) * 2001-04-06 2003-08-05 Amkor Technology, Inc. Making leadframe semiconductor packages with stacked dies and interconnecting interposer
EP1603158B1 (en) * 2003-03-11 2021-06-09 The Furukawa Electric Co., Ltd. Optical module, comprising printed wiring board, lead frame and multi-channel optical semiconductor element and method for manufacturing same
JP4270095B2 (ja) * 2004-01-14 2009-05-27 株式会社デンソー 電子装置
US7154186B2 (en) * 2004-03-18 2006-12-26 Fairchild Semiconductor Corporation Multi-flip chip on lead frame on over molded IC package and method of assembly
TWI237882B (en) * 2004-05-11 2005-08-11 Via Tech Inc Stacked multi-chip package
DE102007003182B4 (de) * 2007-01-22 2019-11-28 Snaptrack Inc. Elektrisches Bauelement
US7911053B2 (en) * 2007-04-19 2011-03-22 Marvell World Trade Ltd. Semiconductor packaging with internal wiring bus
KR100891531B1 (ko) * 2007-09-10 2009-04-03 주식회사 하이닉스반도체 패턴 정렬 불량 검출 장치
US20090096073A1 (en) 2007-10-16 2009-04-16 Kabushiki Kaisha Toshiba Semiconductor device and lead frame used for the same
DE102011086722A1 (de) * 2011-11-21 2013-05-23 Robert Bosch Gmbh Mikromechanische Funktionsvorrichtung, insbesondere Lautsprechervorrichtung, und entsprechendes Herstellungsverfahren
US9324584B2 (en) * 2012-12-14 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with transferable trace lead frame
RU2541725C1 (ru) * 2013-07-23 2015-02-20 Федеральное государственное унитарное предприятие "Научно-производственное предприятие "Исток" (ФГУП "НПП "Исток") Выводная рамка для многокристального полупроводникового прибора свч
US20150075849A1 (en) * 2013-09-17 2015-03-19 Jia Lin Yap Semiconductor device and lead frame with interposer
US9368434B2 (en) 2013-11-27 2016-06-14 Infineon Technologies Ag Electronic component
US11145574B2 (en) 2018-10-30 2021-10-12 Microchip Technology Incorporated Semiconductor device packages with electrical routing improvements and related methods
CN117038623B (zh) * 2023-08-18 2024-08-02 上海纳矽微电子有限公司 用于将芯片打线至框架的载具组件和芯片打线方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910001419B1 (ko) * 1987-03-31 1991-03-05 가부시키가이샤 도시바 수지봉합형 집적회로장치
JPS6480032A (en) * 1987-09-21 1989-03-24 Hitachi Maxell Semiconductor device and manufacture thereof
JPH0449650A (ja) * 1990-06-19 1992-02-19 Oki Electric Ind Co Ltd モールドパッケージ型ハイブリッドｉｃ
JP3029736B2 (ja) * 1992-06-11 2000-04-04 株式会社日立製作所 混成集積回路装置の製造方法

Also Published As

Publication number Publication date
US5780926A (en) 1998-07-14
JPH09232508A (ja) 1997-09-05
KR100203934B1 (ko) 1999-06-15

Similar Documents

Publication Publication Date Title
KR970063688A (ko) 패턴닝된 리드프레임을 이용한 멀티 칩 패키지
KR100226737B1 (ko) 반도체소자 적층형 반도체 패키지
KR100204753B1 (ko) 엘오씨 유형의 적층 칩 패키지
KR970077556A (ko) 적층형 반도체 패키지
KR890001186A (ko) 반도체 집적회로 장치 및 그 제조방법
KR970067781A (ko) 반도체 장치와 그의 제조방법 및 집합형 반도체 장치
KR970077555A (ko) 적층형 버텀 리드 패키지
KR930017153A (ko) 반도체 장치
KR920001689A (ko) 반도체장치 및 그 제조방법
KR19980020296A (ko) 반도체 칩 패키지
KR20010068513A (ko) 윈도우가 구비된 회로기판을 포함하는 적층 칩 패키지
KR970077563A (ko) 적층칩 볼 그리드 어레이
KR920007131A (ko) 반도체 장치
KR20020054476A (ko) 반도체 칩 패키지용 인쇄회로기판
KR100400827B1 (ko) 반도체패키지
KR970063590A (ko) 탭 테이프를 적용한 칩 스케일 패키지
KR100548592B1 (ko) 적층형 마이크로 비 지 에이 패키지
KR950002210B1 (ko) 반도체 칩 실장 방법
KR970077544A (ko) 덮개의 기능을 겸비하는 칩이 접착된 기판을 이용한 적층형 볼그리드 어레이 패키지
KR20050022650A (ko) 리드 프레임을 이용한 비지에이 패키지
JPH04124867A (ja) 半導体パッケージ
KR970053783A (ko) Bga 반도체 패키지
KR0164130B1 (ko) 멀티다이 플라스틱 패키지
KR980004169A (ko) 카드 몸체에 칩이 내장된 아이씨 카드
KR960002764A (ko) 캐패시터를 구비한 반도체 패키지 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080303

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee