KR890001186A - 반도체 집적회로 장치 및 그 제조방법 - Google Patents

반도체 집적회로 장치 및 그 제조방법 Download PDF

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KR890001186A
KR890001186A KR1019880007112A KR880007112A KR890001186A KR 890001186 A KR890001186 A KR 890001186A KR 1019880007112 A KR1019880007112 A KR 1019880007112A KR 880007112 A KR880007112 A KR 880007112A KR 890001186 A KR890001186 A KR 890001186A
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semiconductor
chip
lead
chips
integrated circuit
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KR1019880007112A
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KR970003915B1 (ko
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마사유끼 와다나베
도시오 스가노
세이이찌로우 쯔구이
다까시 오노
요시아끼 와까시마
Original Assignee
미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
스즈끼진이찌로
히다찌도부세미콘닥터 가부시기가이샤
사또 고고
아끼다덴시 가부시기가이샤
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Priority claimed from JP62155478A external-priority patent/JP2603636B2/ja
Priority claimed from JP62226307A external-priority patent/JP2642359B2/ja
Application filed by 미다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼, 스즈끼진이찌로, 히다찌도부세미콘닥터 가부시기가이샤, 사또 고고, 아끼다덴시 가부시기가이샤 filed Critical 미다 가쓰시게
Publication of KR890001186A publication Critical patent/KR890001186A/ko
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Publication of KR970003915B1 publication Critical patent/KR970003915B1/ko

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Abstract

내용 없음

Description

반도체 직접회로 장치 및 그 제조방법.
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는, 본 발명의 실시예 1의 1의 반도체 장치의 개략 구성을 도시한 평면도.
재2도는 상기 반도체 장치의 개략 구성을 도시한 측면도.
제3도는 상기 반도체 장치의 개략 구성을 도시한 정면도.

Claims (15)

  1. 반도체칩의 범프 전국을 리이드에 접속하고, 상기 리이드를 갖는 반도체칩을 여러개 모듈기판의 배선에 접속하여 구성한 반도체 장치.
  2. 특허청구의 범위 제1항에 있어서, 상기 반도체칩은 패키지로 봉하여 막지 않는 것을 특징으로 하는 반도체 장치.
  3. 특허청구위 범위 제1항에 있어서, 상기 반도체칩은 상기 모듈기판의 표면과 이면의 양면에 탐재되어 있는 것을 특징으로 하는 반도체 장치.
  4. 특허청구위 범위 제1항에 있어서, 상기 반도체 장치는 제1의 반도체칩상에 제2의 반도체칩을 겹치는 것에 의해 동리 신호 또는 동일 전위를 입력 또는 출력하는 리이드끼리 접속해서 반도체칩의 조를 구성하고, 상기 반도체칩의 조를 상기 모듈기판에 여러개 탑재해서 구성한 것을 특징으로 하는 반도체 장치.
  5. 특허청구의 범위 제1항에 있어서, 상기 모듈기판 표면에 탑재되어 있는 반도체칩은 범프 전국이 마련되어 있는 쪽의 면과 반대측의 면이 탑재 기판과 대면하고, 모듈기판 이면에 탑재되어 있는 반도체칩은 범프 전국이 마련되어 있는 쪽의 면이 모듈기판과 대면하고 있는 것을 특징으로 하는 반도체 장치.
  6. 특허청구위 범위 제1항에 있어서, 상기 반도체칩의 범프 전국의 배치를 제1의 반도체칩과 제2의 반도체 칩사이를 대칭으로 하고, 범프 전국기리 접속하도록 제2의 반도체칩을 뒤집게 하여 제1의 반도체칩에 적층되며, 이들 제1의 반도체칩과 제2의 반도체칩사이에 리이드를 개재시킨 것을 특징으로 하는 반도체장치.
  7. 각 리이드 패턴의 일부를 테이프 캐리어 패키지의 적층 내장이 가능하도록 변경한2이상의 상기 테이프캐리어 패키지를 내장용 기판상에 적층 내장해서 되는 것을 특징으로 하는 반도체 장치.
  8. 특허청구의 범위 제7항에 있어서, 변경한 상기 리이드 패턴의 일부가 상기 테이프 캐리어 패키지내의 칩 선택 신호용 리이드인 반도체 장치.
  9. (a)정사각형 또는 직사각형의 판자 형상이고, 각각 제1 및 제2의 주면을 가지며, 상기 제1의 주면에 각각 SRAM 집접회로의 주요부가 형성되어 있는 제1 및 제2의 SRAM 반도체칩, (b)상기 각각의 칩의 상기 제1주면의 1쌍이 대항하는 변의근방에 마련된 다수의 전국 패드, (c)상기 각각의 칩의 상기 제1주면의 상기1쌍의 변 근방의 어느 것인가에 마련된 각각의 칩 선택 전국 패드, (d)상기 각각의 칩의 상기 다수의 패드와 그 안쪽 끝이 접속된 금속 시트로 되는 다수의 리이드, (e)상기 각각의 칩의 상기 칩 선택 패드와 그 안쪽끝이 접속된 금속 시트로 되는 제1 및 제2라이드, (f)상기 제1칩의 제2주면과 그것에 평행으로 근접하는 상기 제2칩의 제1주면사이에 마련된 절연부재와, (g)상기 각각의 다수의 리이드의 동일 기능을 갖는 패드에 대응하는 바깥쪽 끝부분 밑 그 근방에 서 그 연장 방향이 일치하도록 중첩 접속된 중첩 접속부를 포함하는 반도체 집적회 메모리 장치.
  10. 특허 청구의 범위 제9항에 있어서, 상기 리이드는 SOP(스몰 아우트 라인 패키지)로 형성되어 있는 반도체 집적회로 메모리 장치.
  11. 특허청구의 범위 제9항에 있어서, 상기 리이드는 리이드의 선단이 납땜면과 직가으로 맞닿을 수 있도록 버트 라이드로 형성된 반도체 집적회로 메모리 장치.
  12. 캐리어 테이프 중앙에 따라서 다수 마련된 반도체칩 탑재용 열림구멍부에 각각 메모리 칩을 범프 전국을 거쳐서 접속하는 반도체집적 회로의 제조방법에 있어서, (a)제, 제2의 캐리어 테이프는 각각의 제1주면 및 탑재용 열 림구멍내에 금속 시트로 되는 다수의 리이드를 가지며, 상기 제1 및 제2캐리어 테이프의 리이드 패턴은 각각의 칩 선택 단자 또는 그것과 동기의 단자와 접속되어야할 링이드이외는 동일한 패턴을 갖고, 제1, 제2의 캐리어 테이프에 동일한 패턴을 갖는 메모리칩을 각각 범프 전극을 거쳐서 연동 본딩하는 공정, (b)상기 제1 및 제2의 캐리어 테이프의 각 상기 열림구멍부에 동일한 패턴을 갖는 메모리 칩을 각각 범프 전극을 거쳐서 연동 본딩하는 공정, (c)상기 제1 및 제2의 캐리어 테이프를 일치하는 패턴이 겹치도록 중첩해서 중첩하여 연장하는 상기 각 열림 구멍부의 리이드를 압착하고, 상기 여러개의 메모리칩과 다수의 리이드로 되는 다중 칩 리이드 복합체를 형성하는 공정과, (d)상기 각 캐리어 테이프에서 상기 복합체를 분리하는 공정으로 되는 반도체 집적회로의 제조방법.
  13. 특허 청구의 범위 제12항에 있어서, 상기 공정(b)와 (c)사이에 상기 제1 및 제2의 메모리 칩의 디바이스 형성 주면에 각각의 상기 주면 및 같은 주면상의 각 리이드 및 범프 전극을 덮도록 수지 몰드제를 포팅하는 공정(e)를 갖는 반도체 집적회로의 제조방법.
  14. 특허청구위 범위 제12항에 있어서, 상기 공정(b)와 상기(c)사이에 각 캐리어 테이프 상태에서 각 칩의 전기적 테스트를 행하는 반도체 집적회로의 제조방법.
  15. 특허청구의 범위 제12항에 있어서, 상기 공정(d)후에 상기 복합체를 상기 리이드를 거쳐서 기판에면 내장법에 의해 땜납 리플로우 내장하는 반도체 집적회로의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880007112A 1987-06-24 1988-06-14 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈 KR970003915B1 (ko)

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JP62155478A JP2603636B2 (ja) 1987-06-24 1987-06-24 半導体装置
JP62226307A JP2642359B2 (ja) 1987-09-11 1987-09-11 半導体装置
JP62-226307 1987-09-11

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