TWI392069B - 封裝結構及其封裝製程 - Google Patents

封裝結構及其封裝製程 Download PDF

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TWI392069B
TWI392069B TW098140006A TW98140006A TWI392069B TW I392069 B TWI392069 B TW I392069B TW 098140006 A TW098140006 A TW 098140006A TW 98140006 A TW98140006 A TW 98140006A TW I392069 B TWI392069 B TW I392069B
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Taiwan
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protective layer
semiconductor
semiconductor component
circuit
conductive
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TW098140006A
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TW201118991A (en
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Chi Chih Shen
Jen Chuan Chen
Tommy Pan
Hui Shan Chang
Chia Lin Hung
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Advanced Semiconductor Eng
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Priority to TW098140006A priority Critical patent/TWI392069B/zh
Priority to US12/785,704 priority patent/US8446000B2/en
Publication of TW201118991A publication Critical patent/TW201118991A/zh
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Publication of TWI392069B publication Critical patent/TWI392069B/zh

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Description

封裝結構及其封裝製程
本發明是有關於一種封裝結構及其封裝製程，且特別是有關於一種適於應用在堆疊式半導體元件封裝製程中的封裝結構及其封裝製程。
在現今的資訊社會中，使用者均是追求高速度、高品質、多功能性的電子產品。就產品外觀而言，電子產品的設計是朝向輕、薄、短、小的趨勢邁進。因此，電子封裝技術發展出諸如堆疊式半導體元件封裝等多半導體元件封裝技術。
堆疊式半導體元件封裝是利用垂直堆疊的方式將多個半導體元件封裝於同一封裝結構中，如此可提升封裝密度以使封裝體小型化，且可利用立體堆疊的方式縮短半導體元件之間的訊號傳輸的路徑長度，以提升半導體元件之間訊號傳輸的速度，並可將不同功能的半導體元件組合於同一封裝體中。
習知的堆疊式半導體元件封裝的製作方法如下所述。首先，將多個半導體元件相互堆疊而形成一半導體元件堆疊結構，這些半導體元件至少其中之一具有多個貫穿半導體元件的直通矽晶穿孔(Through Silicon Via，TSV)結構，且半導體元件之間可透過直通矽晶穿孔結構而彼此電性連接。之後，再將半導體元件堆疊結構配置於一線路板上，以藉由直通矽晶穿孔結構電性連接至線路板，並於線路板上形成一封裝膠體，以保護半導體元件堆疊結構。換言之，習知技術是先製作出半導體元件堆疊結構，之後才將半導體元件堆疊結構安裝於線路板上。
然而，習知的堆疊式半導體元件封裝的製作方法必須在製程一開始時就先決定構成半導體元件堆疊結構的多個半導體元件的種類(或佈線)，以致於降低堆疊式半導體元件封裝製程的在半導體元件搭配上的選擇彈性。
本發明提供一種封裝結構，適於應用在堆疊式半導體元件封裝製程中且其可依實際情況而與不同的半導體元件搭配。
本發明提供一種封裝製程，可增加封裝結構在堆疊式半導體元件封裝製程中半導體元件搭配上的選擇彈性。
本發明提出一種封裝製程如下所述。首先，提供一載具。接著，於載具上配置一線路母板，線路母板包括多個線路板。然後，提供多個第一半導體元件，且各第一半導體元件具有相對的一第一頂面與一底面，各第一半導體元件具有多個導電通道，各導電通道具有相對的一第一端面與一第二端面，且各第一半導體元件的底面暴露出對應的導電通道的第二端面。之後，使第一半導體元件分別透過對應的導電通道而連接至線路板，其中第一半導體元件的底面朝向線路母板。接著，於線路母板上形成一第一保護層，第一保護層覆蓋第一半導體元件。然後，薄化第一保護層與第一半導體元件，以暴露出導電通道的第一端面。
在本發明之一實施例中，上述之封裝製程更包括在暴露出導電通道的第一端面之後，移除第一保護層，以及於線路母板上形成一第二保護層，第二保護層覆蓋第一半導體元件。
在本發明之一實施例中，封裝製程更包括下述步驟。在形成第二保護層之後，薄化第二保護層，以暴露出導電通道的第一端面，其中第二保護層覆蓋各第一半導體元件之遠離線路母板的一第二頂面，且各導電通道之遠離該線路母板的一端部突出於第二保護層之遠離線路母板的表面。之後，將多個第二半導體元件分別連接至第一半導體元件，其中各第一半導體元件的導電通道連接對應的第二半導體元件。接著，於線路母板上形成一第三保護層，第三保護層覆蓋第二半導體元件。然後，分離線路母板與載具。之後，沿著線路板的邊界切割第二保護層、第三保護層與線路母板，以形成多個封裝結構。
在本發明之一實施例中，封裝製程更包括在暴露出導電通道之後並在形成第三保護層之前，於各第一半導體元件以及對應的第二半導體元件之間形成一第二絕緣膠。
在本發明之一實施例中，封裝製程更包括在分離線路母板與載具之後，於各線路板之遠離對應的第一半導體元件的表面上形成多個銲球。
在本發明之一實施例中，上述之薄化第一保護層與各第一半導體元件的方法包括對第一保護層之遠離線路母板的一第一側進行一研磨製程，以暴露出導電通道的第一端面，以及自第一保護層的第一側薄化第一保護層與第一半導體元件，以使導電通道之遠離線路母板的一端部突出於對應的第一半導體元件之遠離線路母板的一第二頂面。
在本發明之一實施例中，上述之封裝製程更包括對各導電通道的第一端面進行一表面處理製程，以形成一至少覆蓋第一端面的覆蓋層。
在本發明之一實施例中，上述之封裝製程更包括在將第一半導體元件分別連接至線路板之前，將多個第一絕緣膠分別形成在線路板上，以及在將第一半導體元件分別連接至線路板時，使各第一半導體元件配置於對應的第一絕緣膠上，且各第一絕緣膠包覆對應的第一半導體元件的底面上的多個導電凸塊，其中導電凸塊連接至對應的線路板。
在本發明之一實施例中，上述之封裝製程更包括在將第一半導體元件分別連接至線路板之後，將一第一絕緣膠填入各第一半導體元件與對應的線路板之間。
在本發明之一實施例中，上述之封裝製程更包括在暴露出導電通道的第一端面之後，將多個第二半導體元件分別連接至第一半導體元件，其中各第一半導體元件的導電通道連接對應的第二半導體元件；於線路母板上形成一第三保護層，第三保護層覆蓋第二半導體元件；分離線路母板與載具；以及沿著線路板的邊界切割第一保護層、第三保護層與線路母板，以形成多個封裝結構。
在本發明之一實施例中，上述之封裝製程更包括在暴露出導電通道之後並在形成第三保護層之前，於各第一半導體元件以及對應的第二半導體元件之間形成一第二絕緣膠。
在本發明之一實施例中，上述之封裝製程更包括在分離線路母板與載具之後，於各線路板之遠離對應的第一半導體元件的表面上形成多個銲球。
本發明提出一種封裝結構包括一線路板、一第一半導體元件以及一第一保護層。第一半導體元件配置於線路板上，並具有相對的一頂面與一底面，其中底面朝向線路板，且第一半導體元件具有多個導電通道，各導電通道具有相對的一第一端面與一第二端面，頂面暴露出導電通道的第一端面，底面暴露出導電通道的第二端面。第一保護層配置於線路板上，並至少包覆第一半導體元件的側壁且暴露出導電通道的第一端面，其中第一保護層的側壁切齊於線路板的側壁。
在本發明之一實施例中，上述之封裝結構更包括一覆蓋層，其配置於各導電通道的第一端面上。
在本發明之一實施例中，上述之封裝結構更包括一第一絕緣膠，其配置於第一半導體元件與線路板之間，且包覆第一半導體元件的底面上的多個導電凸塊，導電凸塊連接至線路板。
在本發明之一實施例中，上述之封裝結構更包括多個銲球，其配置於線路板之遠離第一半導體元件的表面上。
在本發明之一實施例中，上述之封裝結構更包括一第二半導體元件以及一第三保護層，第二半導體元件配置於第一半導體元件的頂面上，並連接第一半導體元件的導電通道，第三保護層配置於線路板上且覆蓋第二半導體元件。
在本發明之一實施例中，上述之封裝結構更包括一第二絕緣膠，其配置於第一半導體元件與第二半導體元件之間。
在本發明之一實施例中，上述之第三保護層的側壁切齊於第一保護層的側壁以及線路板的側壁。
在本發明之一實施例中，各導電通道之遠離線路板的一端部突出於第一半導體元件的頂面。
在本發明之一實施例中，第一保護層之遠離線路板的頂面切齊於第一半導體元件的頂面。
在本發明之一實施例中，部分第一保護層覆蓋第一半導體元件的頂面，且導電通道之遠離線路板的一端部突出於第一保護層之遠離線路板的表面。
在本發明之一實施例中，第一保護層之遠離線路板的頂面低於或高於第一半導體元件的頂面。
基於上述，本發明是先在線路母板上配置第一半導體元件以形成一暴露出第一半導體元件之導電通道的封裝結構，之後，再視實際需求而將符合需要的第二半導體元件連接至第一半導體元件。因此，本發明之封裝製程在第一半導體元件與第二半導體元件的搭配上具有較大的選擇彈性。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A～圖1G繪示本發明一實施例之封裝結構的製程剖面圖。
首先，請參照圖1A，提供一載具110。接著，在本實施例中，可在載具110上形成一黏著層A。接著，請參照圖1B，於黏著層A上配置一線路母板120，線路母板120包括多個線路板122。
然後，請參照圖1C，提供多個第一半導體元件130(例如晶片)，且各第一半導體元件130具有相對的一頂面132與一底面134。此外，各第一半導體元件130還具有多個導電通道136，且各導電通道136具有相對的一第一端面136a與一第二端面136b，其中各第一半導體元件130的底面134暴露出對應的導電通道136的第二端面136b。值得注意的是，前述『對應』一詞是代表同一第一半導體元件130的底面134與導電通道136。在本實施例中，導電通道136為直通矽晶穿孔(Through Silicon Via，TSV)結構。之後，使第一半導體元件130透過導電通道136以及配置於底面134上的多個導電凸塊138而連接至線路板122，其中第一半導體元件130的底面134朝向線路母板120，而頂面132遠離線路母板120。
在本實施例中，為保護導電凸塊138，可在各第一半導體元件130與對應的線路板122之間形成一第一絕緣膠140，而且第一絕緣膠140可以是在第一半導體元件130連接至線路板122之前或之後形成。第一絕緣膠140例如是非導電膠(Non-Conductive Polymer，NCP)或其他適合作為底膠的材料。
若是在第一半導體元件130連接至線路板122之前形成第一絕緣膠140，則在將第一半導體元件130連接至線路板122時，需使各第一半導體元件130配置於對應的第一絕緣膠140上，其中各第一絕緣膠140包覆對應的第一半導體元件130的底面134上的多個導電凸塊138，其中導電凸塊138連接至對應的線路板122。若是在第一半導體元件130連接至線路板122之後形成第一絕緣膠140，則形成第一絕緣膠140的方式可以是將第一絕緣膠140填入各第一半導體元件130與對應的線路板122之間，以包覆導電凸塊138。
接著，請參照圖1D，於線路母板120上形成一第一保護層150，第一保護層150覆蓋第一半導體元件130。在本實施例中，形成第一保護層150的方式可為塗佈(coating)或是鑄模成型(molding)。
然後，請參照圖1F，薄化第一保護層150與第一半導體元件130，以暴露出導電通道136的第一端面136a。詳細而言，在本實施例中，薄化第一保護層150與各第一半導體元件130的方法如下所述。首先，請參照圖1D與圖1E，對第一保護層150之遠離線路母板120的一第一側152進行一研磨製程，以暴露出導電通道136的第一端面136a。研磨製程例如為一般研磨或化學機械研磨(chemical mechanical polishing，CMP)製程。
之後，請參照圖1F，自第一保護層150的第一側152薄化第一保護層150與第一半導體元件130，以使各導電通道136之遠離線路母板120的一端部136c突出於對應的第一半導體元件130之遠離線路母板120的頂面132a，其中薄化第一保護層150與第一半導體元件130的方法可為化學機械研磨(chemical mechanical polishing，CMP)、化學蝕刻、灰化(ashing)、研磨或是其他適合同時或分別薄化第一保護層150與第一半導體元件130的加工製程。在本實施例中，化學機械研磨所使用的化學藥液可選擇對矽的蝕刻速度大於對導電通道136的蝕刻速度的化學藥液，以避免在薄化的過程中過度損傷導電通道136。
值得注意的是，在本實施例中，可以是同時薄化也可以是分別薄化第一保護層150與第一半導體元件130，因此，第一保護層150之遠離線路母板120的頂面154與第一半導體元件130的頂面132a可以是共平面也可以是不共平面。
然後，請參照圖1G，在本實施例中，可對各導電通道136的第一端面136a進行一表面處理製程，以形成一至少覆蓋第一端面136a的覆蓋層160，覆蓋層160的材質例如為鎳/金、化鎳鈀金、銀、錫及其合金、錫膏或有機保銲劑(Organic Solderability Preservative，OSP)。在其他實施例中，覆蓋層160可覆蓋導電通道136之突出於頂面132a的端部136c。
圖2A～圖2B繪示接續圖1G的步驟的封裝結構的製程剖面圖。在一實施例中，第一保護層150的材質例如為易移除的材料，因此，可在暴露出導電通道136的第一端面136a之後，移除第一保護層150(如圖2A所示)，然後，於線路母板120上形成一第二保護層170(如圖2B所示)，第二保護層170覆蓋第一半導體元件130，以作為一封裝膠體，形成第二保護層170的方式可為塗佈或是鑄模成型。
圖3A～圖3F繪示接續圖1G的步驟的封裝結構的製程剖面圖。接續圖1G，請參照圖3A，在本實施例中，可選擇性地在各第一半導體元件130上形成一第二絕緣膠210，第二絕緣膠210例如是非導電膠或其他適合作為底膠的材料。之後，請參照圖3B，在本實施例中，於各第二絕緣膠210上配置一第二半導體元件220(例如晶片)，並使第二半導體元件220連接至第一半導體元件130，其中各第一半導體元件130的導電通道136連接對應的第二半導體元件220的接墊222。
在其他實施例中，第二絕緣膠210也可以是在第二半導體元件220連接至第一半導體元件130之後形成，且形成第二絕緣膠210的方式可以是將第二絕緣膠210填入各第一半導體元件130與對應的第二半導體元件220之間。
接著，請參照圖3C，在本實施例中，於線路母板120上形成一第三保護層230，且第三保護層230覆蓋第二半導體元件220，而形成第三保護層230的方式可為塗佈或是鑄模成型。然後，請參照圖3D，在本實施例中，分離線路母板120與載具110(以及黏著層A)。之後，請參照圖3E，在本實施例中，於各線路板122之遠離對應的第一半導體元件130的表面122a上形成多個銲球240。
之後，請參照圖3E與圖3F，沿著線路板122的邊界124切割第一保護層150、第三保護層230與線路母板120，以形成多個封裝結構P(圖3F僅繪示一個封裝結構P為代表)。
值得注意的是，在本實施例中是以相互堆疊的第一半導體元件130與第二半導體元件220為例，但並非用以限定封裝結構P中堆疊的半導體元件數量。舉例來說，封裝結構P可具有三個或三個以上相互堆疊的半導體元件，而這些半導體元件可透過半導體元件的導電通道136而彼此電性連接。
圖4繪示圖3F中的封裝結構的一種變化。請參照圖4，若是於圖3A與圖3B的步驟中未形成第二絕緣膠210，則於圖3C的步驟中第三保護層230可填入第一半導體元件130與第二半導體元件220之間，且在經過圖3D～圖3F的步驟(亦即分離線路母板120與載具110、形成銲球240以及切割第一保護層150、第三保護層230與線路母板120)之後，可形成圖4的封裝結構P1。
值得注意的是，相較於習知技術是先製作出半導體元件堆疊結構，之後才將半導體元件堆疊結構安裝於線路板上，本實施例是先在線路母板120上配置第一半導體元件130以形成一暴露出第一半導體元件130之導電通道136的封裝結構P2(如圖1G所示)，之後，再視實際需求而將適合的第二半導體元件220連接至第一半導體元件130。因此，本實施例之封裝製程在第一半導體元件130與第二半導體元件220的搭配上具有較大的選擇彈性。
如此一來，封裝結構的製造商可製作封裝結構P2並將封裝結構P2賣給客戶，而客戶可依照實際的需求而選擇將需要的第二半導體元件220連接至第一半導體元件130，以製作出符合實際需求的封裝結構P(如圖3F所示)。因此，封裝結構的製造商的製程與客戶的製程可彼此獨立，從而增加客戶在半導體元件搭配上的選擇性。
以下將詳細介紹圖3F的封裝結構P。
請參照圖3F，本實施例之封裝結構P包括一線路板122、一第一半導體元件130以及一第一保護層150。第一半導體元件130配置於線路板122上，並具有相對的一頂面132a與一底面134，其中底面134朝向線路板122。此外，第一半導體元件130具有多個導電通道136，且各導電通道136具有相對的一第一端面136a與一第二端面136b，其中頂面132a暴露出導電通道136的第一端面136a，底面134暴露出導電通道136的第二端面136b。在本實施例中，導電通道136貫穿第一半導體元件130，且導電通道136之遠離線路板122的一端部136c突出於第一半導體元件130之頂面132a。
詳細而言，在本實施例中，第一半導體元件130是透過配置於底面134上的多個導電凸塊138而連接至線路板122，並且，為保護導電凸塊138，可在第一半導體元件130與線路板122之間填入一第一絕緣膠140。
在本實施例中，可在各導電通道136的第一端面136a上配置一覆蓋層160，以避免導電通道136氧化或受到外界環境的污染，或者是以利於導電通道136與其他的電子元件(例如另一半導體元件)電性連接。
第一保護層150配置於線路板122上，並覆蓋第一半導體元件130的側壁S1，且暴露出導電通道136的第一端面136a。第一保護層150的側壁S2切齊於線路板122的側壁S3，且第一保護層150之遠離線路板122的頂面154切齊於第一半導體元件130的頂面132a。在其他實施例中，可藉由使部分的第一保護層150填入第一半導體元件130與線路板122之間來取代第一絕緣膠140。
在本實施例中，可在各第一半導體元件130的頂面132a上配置一第二半導體元件220，且第二半導體元件220的底面224上的多個接墊222連接第一半導體元件130的導電通道136。另外，在本實施例中，可在第一半導體元件130與第二半導體元件220之間配置一第二絕緣膠210，以保護第一半導體元件130與第二半導體元件220的相接之處(即接墊222、覆蓋層160與導電通道136的第一端面136a)。
此外，為保護第二半導體元件220免於受到外界環境的污染或者是後續製程的破壞，可在線路板122上配置一第三保護層230，且第三保護層230覆蓋第二半導體元件220，其中第三保護層230的側壁S4切齊於第一保護層150的側壁S2以及線路板122的側壁S3。在其他實施例中，可藉由使部分的第三保護層230填入第一半導體元件130與第二半導體元件220之間來取代第二絕緣膠210。
另外，為使第一半導體元件130與第二半導體元件220可透過線路板122的線路(未繪示)而與其他的電子元件電性連接，可在線路板122之遠離第一半導體元件130的表面122a上配置多個銲球240。
圖5A～圖5F繪示接續圖2B的步驟的封裝結構的製程剖面圖。接續圖2B，請參照圖5A，薄化第二保護層170，以暴露出導電通道136的第一端面136a。在本實施例中，第二保護層170覆蓋各第一半導體元件130之頂面132a，且各導電通道136之遠離線路母板120的一端部136c突出於第二保護層170之遠離線路母板120的表面172。
之後，請參照圖5B，將多個第二半導體元件220分別連接至第一半導體元件130，其中各第一半導體元件130的導電通道136連接對應的第二半導體元件220。在本實施例中，可選擇性地於各第一半導體元件130以及對應的第二半導體元件220之間形成一第二絕緣膠210，而且第二絕緣膠210可以是在第二半導體元件220連接至第一半導體元件130之前或之後形成。
接著，請參照圖5C，於線路母板120上形成一第三保護層230，第三保護層230覆蓋第二半導體元件220。
然後，請參照圖5D，分離線路母板120與載具110(以及黏著層A)。
之後，請參照圖5E，於各線路板122之遠離對應的第一半導體元件130的表面122a上形成多個銲球240。
之後，請參照圖5F，沿著線路板122的邊界124切割第二保護層170、第三保護層230與線路母板120，以形成多個封裝結構P3。
在本實施例中，封裝結構P3相似於圖3F的封裝結構P，兩者的差異之處在於封裝結構P3的第二保護層170係覆蓋第一半導體元件130的頂面132a，且導電通道136突出於第二保護層170之遠離線路板122的表面172。在本實施例中，第二保護層170的表面172高於第一半導體元件130的頂面132a。
綜上所述，本發明是先在線路母板上配置第一半導體元件以形成一暴露出第一半導體元件之導電通道的封裝結構，之後，再視實際需求而將符合需要的第二半導體元件連接至第一半導體元件。因此，本發明之封裝製程在第一半導體元件與第二半導體元件的搭配上具有較大的選擇彈性。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110．．．載具
120．．．線路母板
122．．．線路板
122a、172．．．表面
124．．．線路板的邊界
130．．．第一半導體元件
132、132a、154．．．頂面
134、224．．．底面
136．．．導電通道
136a．．．第一端面
136b．．．第二端面
136c．．．端部
138．．．導電凸塊
140．．．第一絕緣膠
150．．．第一保護層
152．．．第一側
160．．．覆蓋層
170．．．第二保護層
210．．．第二絕緣膠
220．．．第二半導體元件
222．．．接墊
230．．．第三保護層
240．．．銲球
A．．．黏著層
P、P1、P2、P3．．．封裝結構
S1、S2、S3、S4．．．側壁
圖1A～圖1G繪示本發明一實施例之封裝結構的製程剖面圖。
圖2A～圖2B繪示接續圖1G的步驟的封裝結構的製程剖面圖。
圖3A～圖3F繪示接續圖1G的步驟的封裝結構的製程剖面圖。
圖4繪示圖3F中的封裝結構的一種變化。
圖5A～圖5F繪示接續圖2B的步驟的封裝結構的製程剖面圖。
122．．．線路板
122a．．．表面
130‧‧‧第一半導體元件
132a、154‧‧‧頂面
134、224‧‧‧底面
136‧‧‧導電通道
136a‧‧‧第一端面
136b‧‧‧第二端面
136c‧‧‧端部
138‧‧‧導電凸塊
140‧‧‧第一絕緣膠
150‧‧‧第一保護層
160‧‧‧覆蓋層
210‧‧‧第二絕緣膠
220‧‧‧第二半導體元件
222‧‧‧接墊
230‧‧‧第三保護層
240‧‧‧銲球
P‧‧‧封裝結構
S1、S2、S3、S4‧‧‧側壁

Claims (23)

  1. 一種封裝製程，包括：提供一載具；於該載具上配置一線路母板，該線路母板包括多個線路板；提供多個第一半導體元件，且各該第一半導體元件具有相對的一第一頂面與一底面，各該第一半導體元件具有多個導電通道，各該導電通道具有相對的一第一端面與一第二端面，且各該第一半導體元件的該底面暴露出對應的該些導電通道的該些第二端面；使該些第一半導體元件分別透過對應的該些導電通道而連接至該些線路板，其中該些第一半導體元件的該些底面朝向該線路母板；於該線路母板上形成一第一保護層，該第一保護層覆蓋該些第一半導體元件；以及薄化該第一保護層與該些第一半導體元件，以暴露出該些導電通道的該些第一端面。
  2. 如申請專利範圍第1項所述之封裝製程，更包括：在暴露出該些導電通道的該些第一端面之後，移除該第一保護層；以及於該線路母板上形成一第二保護層，該第二保護層覆蓋該些第一半導體元件。
  3. 如申請專利範圍第2項所述之封裝製程，更包括：在形成該第二保護層之後，薄化該第二保護層，以暴 露出該些導電通道的該些第一端面，其中該第二保護層覆蓋各該第一半導體元件之遠離該線路母板的一第二頂面，且各該導電通道之遠離該線路母板的一端部突出於該第二保護層之遠離該線路母板的表面；將多個第二半導體元件分別連接至該些第一半導體元件，其中各該第一半導體元件的該些導電通道連接對應的該第二半導體元件；於該線路母板上形成一第三保護層，該第三保護層覆蓋該些第二半導體元件；分離該線路母板與該載具；以及沿著該些線路板的邊界切割該第二保護層、該第三保護層與該線路母板，以形成多個封裝結構。
  4. 如申請專利範圍第3項所述之封裝製程，更包括：在暴露出該些導電通道之後並在形成該第三保護層之前，於各該第一半導體元件以及對應的該第二半導體元件之間形成一第二絕緣膠。
  5. 如申請專利範圍第3項所述之封裝製程，更包括：在分離該線路母板與該載具之後，於各該線路板之遠離對應的該第一半導體元件的表面上形成多個銲球。
  6. 如申請專利範圍第1項所述之封裝製程，其中薄化該第一保護層與各該第一半導體元件的方法包括：對該第一保護層之遠離該線路母板的一第一側進行一研磨製程，以暴露出該些導電通道的該些第一端面；以及自該第一保護層的該第一側薄化該第一保護層與該些 第一半導體元件，以使各該導電通道之遠離該線路母板的一端部突出於對應的該第一半導體元件之遠離該線路母板的一第二頂面。
  7. 如申請專利範圍第1項所述之封裝製程，更包括：對各該導電通道的該第一端面進行一表面處理製程，以形成一至少覆蓋該第一端面的覆蓋層。
  8. 如申請專利範圍第1項所述之封裝製程，更包括：在將該些第一半導體元件分別連接至該些線路板之前，將多個第一絕緣膠分別形成在該些線路板上；以及在將該些第一半導體元件分別連接至該些線路板時，使各該第一半導體元件配置於對應的該第一絕緣膠上，且各該第一絕緣膠包覆對應的該第一半導體元件的該底面上的多個導電凸塊，其中該些導電凸塊連接至對應的該線路板。
  9. 如申請專利範圍第1項所述之封裝製程，更包括：在將該些第一半導體元件分別連接至該些線路板之後，將一第一絕緣膠填入各該第一半導體元件與對應的該線路板之間。
  10. 如申請專利範圍第1項所述之封裝製程，更包括：在暴露出該些導電通道的該些第一端面之後，將多個第二半導體元件分別連接至該些第一半導體元件，其中各該第一半導體元件的該些導電通道連接對應的該第二半導體元件；於該線路母板上形成一第三保護層，該第三保護層覆 蓋該些第二半導體元件；分離該線路母板與該載具；以及沿著該些線路板的邊界切割該第一保護層、該第三保護層與該線路母板，以形成多個封裝結構。
  11. 如申請專利範圍第10項所述之封裝製程，更包括：在暴露出該些導電通道之後並在形成該第三保護層之前，於各該第一半導體元件以及對應的該第二半導體元件之間形成一第二絕緣膠。
  12. 如申請專利範圍第10項所述之封裝製程，更包括：在分離該線路母板與該載具之後，於各該線路板之遠離對應的該第一半導體元件的表面上形成多個銲球。
  13. 一種封裝結構，包括：一線路板；一第一半導體元件，配置於該線路板上，並具有相對的一頂面與一底面，其中該底面朝向該線路板，且該第一半導體元件具有多個導電通道，各該導電通道具有相對的一第一端面與一第二端面，該頂面暴露出該些導電通道的該些第一端面，該底面暴露出該些導電通道的該些第二端面；以及一第一保護層，配置於該線路板上，並至少包覆該第一半導體元件的側壁且暴露出該些導電通道的該些第一端面，其中該第一保護層的側壁切齊於該線路板的側壁，其 中該第一保護層之遠離該線路板的頂面低於或高於該第一半導體元件的該頂面。
  14. 如申請專利範圍第13項所述之封裝結構，更包括：一覆蓋層，配置於各該導電通道的該第一端面上。
  15. 如申請專利範圍第13項所述之封裝結構，更包括：一第一絕緣膠，配置於該第一半導體元件與該線路板之間，且包覆該第一半導體元件的該底面上的多個導電凸塊，其中該些導電凸塊連接至該線路板。
  16. 如申請專利範圍第13項所述之封裝結構，更包括：多個銲球，配置於該線路板之遠離該第一半導體元件的表面上。
  17. 如申請專利範圍第13項所述之封裝結構，更包括：一第二半導體元件，配置於該第一半導體元件的該頂面上，並連接該第一半導體元件的該些導電通道；以及一第三保護層，配置於該線路板上且覆蓋該第二半導體元件。
  18. 如申請專利範圍第17項所述之封裝結構，更包括：一第二絕緣膠，配置於該第一半導體元件與該第二半導體元件之間。
  19. 如申請專利範圍第17項所述之封裝結構，其中該第三保護層的側壁切齊於該第一保護層的側壁以及該線路板的側壁。
  20. 如申請專利範圍第13項所述之封裝結構，其中各該導電通道之遠離該線路板的一端部突出於該第一半導體元件的該頂面。
  21. 如申請專利範圍第13項所述之封裝結構，其中該第一保護層之遠離該線路板的頂面切齊於該第一半導體元件的該頂面。
  22. 如申請專利範圍第13項所述之封裝結構，其中部分該第一保護層覆蓋該第一半導體元件的該頂面，且各該導電通道之遠離該線路板的一端部突出於該第一保護層之遠離該線路板的表面。
  23. 一種封裝結構，包括：一線路板；一第一半導體元件，配置於該線路板上，並具有相對的一頂面與一底面，其中該底面朝向該線路板，且該第一半導體元件具有多個導電通道，各該導電通道具有相對的一第一端面與一第二端面，該頂面暴露出該些導電通道的該些第一端面，該底面暴露出該些導電通道的該些第二端面；一第一保護層，配置於該線路板上，並至少包覆該第一半導體元件的側壁且暴露出該些導電通道的該些第一端面，其中該第一保護層的側壁切齊於該線路板的側壁； 一第二半導體元件，配置於該第一半導體元件的該頂面上，並連接該第一半導體元件的該些導電通道；以及一第三保護層，配置於該線路板上以及該第一半導體元件與該第二半導體元件之間，且該第三保護層覆蓋該第二半導體元件。
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