TWI394253B - 具有凸塊之晶片及具有凸塊之晶片之封裝結構 - Google Patents

具有凸塊之晶片及具有凸塊之晶片之封裝結構 Download PDF

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Publication number
TWI394253B
TWI394253B TW098109809A TW98109809A TWI394253B TW I394253 B TWI394253 B TW I394253B TW 098109809 A TW098109809 A TW 098109809A TW 98109809 A TW98109809 A TW 98109809A TW I394253 B TWI394253 B TW I394253B
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Taiwan
Prior art keywords
metal layer
wafer
layer
package structure
bump
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TW098109809A
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English (en)
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TW201036128A (en
Inventor
Kuo Pin Yang
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Advanced Semiconductor Eng
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Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW098109809A priority Critical patent/TWI394253B/zh
Priority to US12/726,777 priority patent/US8314490B2/en
Publication of TW201036128A publication Critical patent/TW201036128A/zh
Application granted granted Critical
Publication of TWI394253B publication Critical patent/TWI394253B/zh

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    • H—ELECTRICITY
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

具有凸塊之晶片及具有凸塊之晶片之封裝結構
本發明係關於一種晶片及具有晶片之封裝結構，詳言之，係關於一種具有凸塊之晶片及具有凸塊之晶片之封裝結構。
參考圖1，顯示習知具有凸塊之晶片之剖面示意圖。該習知具有凸塊之晶片1包括一晶片本體11、一保護層12、一球下金屬層14及至少一凸塊13。該晶片本體11具有一表面111。該保護層12位於該晶片本體11之表面111上，該保護層12具有至少一開口121。該球下金屬層14位於該保護層12之開口121。該凸塊13位於該球下金屬層14上。
該習知具有凸塊之晶片1之缺點如下。該凸塊13係由單一金屬構成，意即，該凸塊13之熔點為於一固定範圍內，在進行一回銲步驟時，該凸塊13會因高溫而呈熔融狀態，以利於與一銲墊互相連接，然而，其熔融狀態不易控制，難以確實與該銲墊連接，而降低產品良率。此外，該凸塊13若未以活性低之金屬包覆，則該凸塊13容易氧化，產生質變。
因此，有必要提供一種具有凸塊之晶片及具有凸塊之晶片之封裝結構，以解決上述問題。
本發明提供一種具有凸塊之晶片，其包括一晶片本體、一保護層、一球下金屬層及至少一凸塊。該晶片本體具有一表面。該保護層位於該晶片本體之表面上，該保護層具有至少一開口。該球下金屬層位於該保護層之開口。該凸塊位於該球下金屬層上，該凸塊包括一第一金屬層、一第二金屬層、一第三金屬層及一第四金屬層。該第一金屬層位於該球下金屬層上。該第二金屬層位於該第一金屬層上。該第三金屬層位於該第二金屬層上。該第四金屬層位於該第三金屬層上。
藉此，該凸塊係可連結二個晶片，使該晶片可堆疊，以提高產品密度，進而縮小產品尺寸。
本發明更提供一種具有凸塊之晶片，其包括一晶片本體、至少一穿導孔、一保護層、一球下金屬層及至少一凸塊。該晶片本體具有一表面。該穿導孔貫穿該晶片本體，且顯露於該晶片本體之表面。該保護層位於該晶片本體之表面上，該保護層具有至少一開口，該開口顯露該穿導孔。該球下金屬層位於該保護層之開口，且連接該穿導孔。該凸塊位於該球下金屬層上。該凸塊包括一第一金屬層、一第二金屬層及一第三金屬層。該第一金屬層位於該球下金屬層上。該第二金屬層位於該第一金屬層上。該第三金屬層位於該第二金屬層上。
藉此，該穿導孔使該晶片本體之該表面及一相對表面都可形成該凸塊，並進行一堆疊步驟，以縮小產品尺寸。
本發明另提供一種具有凸塊之晶片之封裝結構，其包括一基板、至少一電性連接體、一第一晶片及一第二晶片。該基板具有一上表面及一下表面。該電性連接體位於該基板之上表面。該第一晶片位於該電性連接體上，其包括一晶片本體、至少一穿導孔、一保護層、一球下金屬層及至少一凸塊。該晶片本體具有一上表面及一下表面。該穿導孔貫穿該晶片本體，且顯露於該晶片本體之上表面。該保護層位於該晶片本體之上表面上，其具有至少一開口，且該開口顯露該穿導孔。該球下金屬層位於該保護層之開口，且連接該穿導孔。該凸塊位於該球下金屬層上，其包括一第一金屬層、一第二金屬層及一第三金屬層。該第一金屬層位於該球下金屬層上。該第二金屬層位於該第一金屬層上。該第三金屬層位於該第二金屬層上。該第二晶片位於該第一晶片上。
參考圖2，顯示本發明具有凸塊之晶片之第一實施例之剖面示意圖。該具有凸塊之晶片2包括一晶片本體21、一保護層22、一球下金屬層25及至少一凸塊23。該晶片本體21具有一表面211。在本實施例中，該晶片本體21係為一空白晶片(Dummy Chip)，其包括一穿孔212及一線路層(圖中未示)，且該.線路層係位於該晶片本體21之表面211。然而在其他應用中，該晶片本體21係可為一有功能的晶片(Device Chip)，其更包括一主動面、至少一銲墊及一影像感測元件(CMOS Image Sensor)(圖中未示)。該銲墊係位於該晶片本體21內，且顯露於該主動面。該影像感測元件係位於該晶片本體21內，顯露於該主動面，且位於該銲墊外之相對位置。
該保護層22位於該晶片本體21之表面211上，該保護層22具有至少一開口221。該球下金屬層25位於該保護層22之開口221。在本實施例中，該球下金屬層25之材質係為鈦銅(TiCu)合金，且該球下金屬層25係連接該線路層。該凸塊23位於該球下金屬層25上，該凸塊23包括一第一金屬層232、一第二金屬層233、一第三金屬層234及一第四金屬層235。該第一金屬層232位於該球下金屬層25上。該第二金屬層233位於該第一金屬層232上。該第三金屬層234位於該第二金屬層233上。該第四金屬層235位於該第三金屬層234上。
在本實施例中，該第三金屬層234之材質係與該第一金屬層232相同，皆為銅(Cu)，該第二金屬層233之材質係為鎳(Ni)，該第四金屬層235之材質係為錫銀合金，然而在其他應用中，該第四金屬層235之材質係可為錫(Sn)。較佳地，該第一金屬層232之厚度係為7μm，該第二金屬層233之厚度係為3μm，該第三金屬層234之厚度係大於7μm，該第四金屬層235之厚度係為3-5μm。
在本實施例中，該晶片2更包括至少一穿導孔24，該穿導孔24係貫穿該晶片本體21，且顯露於該晶片本體21之表面211，該球下金屬層25係連接該穿導孔24。該穿導孔24包括一阻絕層241及一導電體242，該阻絕層241位於該晶片本體21之穿孔212之孔壁上，該導電體242位於該阻絕層241內。在本實施例中，二個相鄰之穿導孔24之中心軸之距離定義為一間距D，且較佳地，該凸塊23之直徑d係小於或等於該間距D之三分之二，以避免該等凸塊23互相連接而造成短路。
藉此，該凸塊23係可連結二個晶片2，使該晶片2可堆疊，以提高產品密度，進而縮小產品尺寸。此外，當該凸塊23進行一回銲步驟後，若該第二金屬層233擴散至該第一金屬層232，而消耗部分該第一金屬層232，並形成一介金屬化合物(Inter-material Compound,IMC)，該第三金屬層234可彌補該第一金屬層232被消耗的量，以加強該凸塊23之結合力。此外，該穿導孔24使該晶片本體21之該表面211及一相對表面213都可形成該凸塊23，並進行一堆疊步驟，以縮小產品尺寸。
參考圖3，顯示本發明具有凸塊之晶片之第二實施例之剖面示意圖。本實施例之具有凸塊之晶片3與第一實施例之具有凸塊之晶片2(圖2)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該晶片3之凸塊23之材質不同。在本實施例中，該第三金屬層234之材質係與該第一金屬層232不同，該第一金屬層232之材質係為銅(Cu)，該第二金屬層233之材質係為鎳(Ni)，該第三金屬層234之材質係為錫(Sn)或錫銀合金，該第四金屬層235之材質係為金(Au)。較佳地，該第一金屬層232之厚度係為7μm，該第二金屬層233之厚度係為3μm，該第三金屬層234之厚度係為3-4μm，該第四金屬層235之厚度係為0.5μm。藉此，該第四金屬層235可避免該第一金屬層232、該第二金屬層233及該第三金屬層234氧化。此外，當一選取工具(Die Bonder)選取該晶片3後，進行加熱時，該第四金屬層235(金層)可避免該晶片3沾黏於該選取工具上。
參考圖4，顯示本發明具有凸塊之晶片之第三實施例之剖面示意圖。該晶片4包括一晶片本體41、至少一穿導孔42、一保護層43、一球下金屬層45及至少一凸塊44。該晶片本體41具有一表面411。在本實施例中，該晶片本體41係為一空白晶片(Dummy Chip)，其更包括一穿孔412。然而在其他應用中，該晶片本體41係可為一有功能的晶片(Device Chip)，其更包括一主動面、至少一銲墊及一影像感測元件(CMOS Image Sensor)(圖中未示)。該銲墊係位於該晶片本體41內，且顯露於該主動面。該影像感測元件係位於該晶片本體41內，顯露於該主動面，且位於該銲墊外之相對位置。
該穿導孔42貫穿該晶片本體41，且顯露於該晶片本體41之表面411。在本實施例中，該穿導孔42包括一阻絕層421及一導電體422，該阻絕層421位於該晶片本體41之穿孔412之孔壁上，該導電體422位於該阻絕層421內。在本實施例中，二個相鄰之穿導孔42之中心軸之距離定義為一間距D，且較佳地，該凸塊44之直徑d係小於或等於該間距D之三分之二，以避免該等凸塊44互相連接而造成短路。該保護層43位於該晶片本體41之表面411上，該保護層43具有至少一開口431，該開口431顯露該穿導孔42。該球下金屬層45位於該保護層43之開口431，且連接該穿導孔42。在本實施例中，該球下金屬層45之材質係為鈦銅(TiCu)合金。
該凸塊44位於該球下金屬層45上。該凸塊44包括一第一金屬層442、一第二金屬層443及一第三金屬層444。該第一金屬層442位於該球下金屬層45上。該第二金屬層443位於該第一金屬層442上。該第三金屬層444位於該第二金屬層443上。在本實施例中，該第一金屬層442之材質係為銅(Cu)，該第二金屬層443之材質係為鎳(Ni)，該第三金屬層444之材質係為錫(Sn)或錫銀合金。較佳地，該第一金屬層442之厚度係為7μm，該第二金屬層443之厚度係為3μm，該第三金屬層444之厚度係為2μm。在其他應用中，該晶片4更包括一線路層，該線路層係位於該晶片本體21之表面211，該球下金屬層45係連接該線路層。
藉此，該穿導孔42使該晶片本體41之該表面411及一相對表面413都可形成該凸塊44，並進行一堆疊步驟，以縮小產品尺寸。
參考圖5，顯示本發明具有凸塊之晶片之第四實施例之剖面示意圖。本實施例之具有凸塊之晶片5與第三實施例之具有凸塊之晶片4(圖4)大致相同，其中相同之元件賦予相同之編號。本實施例與第三實施例之不同處在於該晶片5之凸塊44之材質不同。在本實施例中，該第一金屬層442之材質係為銅(Cu)，該第二金屬層443之材質係為鎳(Ni)，該第三金屬層444之材質係為金(Au)。較佳地，該第一金屬層442之厚度係為7μm，該第二金屬層443之厚度係為3μm，該第三金屬層444之厚度係為0.5μm。此外，當一選取工具選取該晶片5後，進行加熱時，該第三金屬層444(金層)可避免該晶片5沾黏於該選取工具上。
參考圖6，顯示本發明具有凸塊之晶片之封裝結構之剖面示意圖。該封裝結構6包括一基板61、至少一電性連接體62、一第一晶片7、一第二晶片64及複數個銲球65。該基板61具有一上表面611及一下表面612。在本實施例中，該基板61更包括至少一導電通孔613貫穿該基板61，且顯露於該基板61之上表面611及下表面612。該電性連接體62位於該基板61之上表面611。在本實施例中，該電性連接體62係為一凸塊。然而在其他應用中，該電性連接體62係可為一銲球。
該第一晶片7位於該電性連接體62上，其包括一晶片本體71、至少一穿導孔72、一保護層73、一球下金屬層75及至少一凸塊74。該晶片本體71具有一上表面711及一下表面713。該下表面713係為一主動面，其相對於該晶片本體71之上表面711。在本實施例中，該晶片本體71係為一有功能的晶片(Device Chip)，其更包括至少一銲墊76及一穿孔712。該銲墊76係位於該晶片本體71內，且顯露於該下表面713。然而在其他應用中，該晶片本體71係可為一空白晶片(Dummy Chip)。
該穿導孔72貫穿該晶片本體71，其一端係顯露於該晶片本體71之上表面711，另一端係連接該銲墊76。在本實施例中，該穿導孔72包括一阻絕層721及一導電體722，該阻絕層721位於該晶片本體71之穿孔712之孔壁上，該導電體722位於該阻絕層721內。在本實施例中，二個相鄰之穿導孔72之中心軸之距離定義為一間距D，且較佳地，該凸塊74之直徑d係小於或等於該間距D之三分之二，以避免該等凸塊74互相連接而造成短路。
該保護層73位於該晶片本體71之上表面711上，該保護層73具有至少一開口731，該開口731顯露該穿導孔72。該球下金屬層75位於該保護層73之開口731，且連接該穿導孔72。在本實施例中，該球下金屬層75之材質係為鈦銅(TiCu)合金。
該凸塊74位於該球下金屬層75上。該凸塊74包括一第一金屬層742、一第二金屬層743及一第三金屬層744。該第一金屬層742位於該球下金屬層75上。該第二金屬層743位於該第一金屬層742上。該第三金屬層744位於該第二金屬層743上。在本實施例中，該第一金屬層742之材質係為銅(Cu)，該第二金屬層743之材質係為鎳(Ni)，該第三金屬層744之材質係為錫(Sn)或錫銀合金。較佳地，該第一金屬層742之厚度係為7μm，該第二金屬層743之厚度係為3μm，該第三金屬層744之厚度係為2μm。
在本實施例中，該第一晶片7更包括一球下金屬層77，位於該下表面713，且連接該銲墊76。該電性連接體62係位於該球下金屬層77上，其係為一凸塊，且包括一第四金屬層621、一第五金屬層622及一第六金屬層623，該第四金屬層621係與該第一金屬層742相同，該第五金屬層622係與該第一金屬層743相同，該第六金屬層623係與該第三金屬層744相同。
在其他應用中，該第一晶片7更包括一影像感測元件(CMOS Image Sensor)(圖中未示)及一線路層(圖中未示)。該影像感測元件係位於該晶片本體71內，顯露於該下表面713，且位於該銲墊76外之相對位置。該線路層係位於該晶片本體71之上表面711，該球下金屬層75係連接該線路層。
該第二晶片64位於該第一晶片7上，且連接該第三金屬層744。在本實施例中，該第二晶片64係為覆晶晶片。然而在其他應用中，該第二晶片64係可具有至少一穿導孔。該等銲球65位於該基板61之下表面612。
惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
1．．．習知具有凸塊之晶片
2．．．本發明具有凸塊之晶片之第一實施例
3．．．本發明具有凸塊之晶片之第二實施例
4．．．本發明具有凸塊之晶片之第三實施例
5．．．本發明具有凸塊之晶片之第四實施例
6．．．本發明具有凸塊之晶片之封裝結構
7．．．第一晶片
11．．．晶片本體
12．．．保護層
13．．．凸塊
14．．．球下金屬層
21．．．晶片本體
22．．．保護層
23．．．凸塊
24．．．穿導孔
25．．．球下金屬層
41．．．晶片本體
42．．．穿導孔
43．．．保護層
44．．．凸塊
45．．．球下金屬層
61．．．基板
62．．．電性連接體
64．．．第二晶片
65．．．銲球
71．．．晶片本體
72．．．穿導孔
73．．．保護層
74．．．凸塊
75．．．球下金屬層
76．．．銲墊
77．．．球下金屬層
111．．．表面
121．．．開口
211．．．表面
212．．．穿孔
213．．．相對表面
221．．．開口
232．．．第一金屬層
233．．．第二金屬層
234．．．第三金屬層
235．．．第四金屬層
241．．．阻絕層
242．．．導電體
411．．．表面
412．．．穿孔
413．．．相對表面
421．．．阻絕層
422．．．導電體
431．．．開口
442．．．第一金屬層
443．．．第二金屬層
444．．．第三金屬層
611．．．上表面
612．．．下表面
613．．．導電通孔
621．．．第四金屬層
622．．．第五金屬層
623．．．第六金屬層
711．．．上表面
712．．．穿孔
713．．．下表面
721．．．阻絕層
722．．．導電體
731．．．開口
742．．．第一金屬層
743．．．第二金屬層
744．．．第三金屬層
圖1顯示習知具有凸塊之晶片之剖面示意圖；
圖2顯示本發明具有凸塊之晶片之第一實施例之剖面示意圖；
圖3顯示本發明具有凸塊之晶片之第二實施例之剖面示意圖；
圖4顯示本發明具有凸塊之晶片之第三實施例之剖面示意圖；
圖5顯示本發明具有凸塊之晶片之第四實施例之剖面示意圖；及
圖6顯示本發明具有凸塊之晶片之封裝結構之剖面示意圖。
4．．．本發明具有凸塊之晶片之第三實施例
41．．．晶片本體
42．．．穿導孔
43．．．保護層
44．．．凸塊
45．．．球下金屬層
411．．．表面
412．．．穿孔
413．．．相對表面
421．．．阻絕層
422．．．導電體
431．．．開口
442．．．第一金屬層
443．．．第二金屬層
444．．．第三金屬層

Claims (54)

  1. 一種具有凸塊之晶片，包括：一晶片本體，具有一表面；一保護層，位於該晶片本體之表面上，該保護層具有至少一開口；一球下金屬層(Under Ball Metal,UBM)，位於該保護層之開口；及至少一凸塊，位於該球下金屬層上，該凸塊包括：一第一金屬層，位於該球下金屬層上；一第二金屬層，位於該第一金屬層上；一第三金屬層，位於該第二金屬層上；及一第四金屬層，位於該第三金屬層上。
  2. 如請求項1之晶片，其中該晶片本體係為一空白晶片(Dummy Chip)。
  3. 如請求項1之晶片，其中該晶片本體係為一有功能的晶片(Device Chip)，該晶片本體更包括一主動面及至少一銲墊，該銲墊係位於該晶片本體內，且顯露於該主動面。
  4. 如請求項3之晶片，其中該晶片更包括一影像感測元件(CMOS Image Sensor)，其係位於該晶片本體內，顯露於該主動面，且位於該銲墊外之相對位置。
  5. 如請求項1之晶片，其中該球下金屬層之材質係為鈦銅(TiCu)合金。
  6. 如請求項1之晶片，其中該第三金屬層之材質係與該第一金屬層相同。
  7. 如請求項6之晶片，其中該第一金屬層及該第三金屬層之材質係為銅(Cu)，該第二金屬層之材質係為鎳(Ni)，該第四金屬層之材質係為錫(Sn)或錫銀合金。
  8. 如請求項1之晶片，其中該第一金屬層之材質係為銅(Cu)，該第二金屬層之材質係為鎳(Ni)，該第三金屬層之材質係為錫(Sn)或錫銀合金，該第四金屬層之材質係為金(Au)。
  9. 如請求項1之晶片，其中該第四金屬層之材質係為金(Au)。
  10. 如請求項1之晶片，其中該第一金屬層之厚度係為7μm。
  11. 如請求項1之晶片，其中該第二金屬層之厚度係為3μm。
  12. 如請求項1之晶片，其中該第三金屬層之厚度係大於7μm。
  13. 如請求項1之晶片，其中該第三金屬層之厚度係為3-4μm。
  14. 如請求項1之晶片，其中該第四金屬層之厚度係為3-5μm。
  15. 如請求項1之晶片，其中該第四金屬層之厚度係為0.5μm。
  16. 如請求項1之晶片，更包括一線路層，該線路層係位於該晶片本體之表面，該球下金屬層係連接該線路層。
  17. 如請求項1之晶片，更包括至少一穿導孔，該穿導孔係貫穿該晶片本體，且顯露於該晶片本體之表面，該球下金屬層係連接該穿導孔。
  18. 如請求項17之晶片，其中該穿導孔包括一阻絕層及一導電體，該阻絕層位於該晶片本體之一穿孔之孔壁上，該導電體位於該阻絕層內。
  19. 如請求項17之晶片，其中二個相鄰之穿導孔之中心軸之距離定義為一間距，且該凸塊之直徑係小於或等於該間距之三分之二。
  20. 一種具有凸塊之晶片，包括：一晶片本體，具有一表面；至少一穿導孔，貫穿該晶片本體，且顯露於該晶片本體之表面；一保護層，位於該晶片本體之表面上，該保護層具有至少一開口，該開口顯露該穿導孔；一球下金屬層(Under Ball Metal,UBM)，位於該保護層之開口，且連接該穿導孔；及至少一凸塊，位於該球下金屬層上，該凸塊包括：一第一金屬層，位於該球下金屬層上；一第二金屬層，位於該第一金屬層上；及一第三金屬層，位於該第二金屬層上。
  21. 如請求項20之晶片，其中該晶片本體係為一空白晶片(Dummy Chip)。
  22. 如請求項20之晶片，其中該晶片本體係為一有功能的晶片(Device Chip)，該晶片本體更包括一主動面及至少一銲墊，該銲墊係位於該晶片本體內，且顯露於該主動面。
  23. 如請求項22之晶片，其中該晶片更包括一影像感測元件(CMOS Image Sensor)，其係位於該晶片本體內，顯露於該主動面，且位於該銲墊外之相對位置。
  24. 如請求項20之晶片，其中該穿導孔包括一阻絕層及一導電體，該阻絕層位於該晶片本體之一穿孔之孔壁上，該導電體位於該阻絕層內。
  25. 如請求項20之晶片，其中二個相鄰之穿導孔之中心軸之距離定義為一間距，且該凸塊之直徑係小於或等於該間距之三分之二。
  26. 如請求項20之晶片，其中該球下金屬層之材質係為鈦銅(TiCu)合金。
  27. 如請求項20之晶片，其中該第一金屬層之材質係為銅(Cu)，該第二金屬層之材質係為鎳(Ni)，該第三金屬層之材質係為錫(Sn)或錫銀合金。
  28. 如請求項20之晶片，其中該第一金屬層之材質係為銅(Cu)，該第二金屬層之材質係為鎳(Ni)，該第三金屬層之材質係為金(Au)。
  29. 如請求項20之晶片，其中該第三金屬層之材質係為金(Au)。
  30. 如請求項20之晶片，其中該第一金屬層之厚度係為7μm。
  31. 如請求項20之晶片，其中該第二金屬層之厚度係為3μm。
  32. 如請求項20之晶片，其中該第三金屬層之厚度係為2μm。
  33. 如請求項20之晶片，其中該第三金屬層之厚度係為0.5μm。
  34. 如請求項20之晶片，更包括一線路層，該線路層係位於該晶片本體之表面，該球下金屬層係連接該線路層。
  35. 一種具有凸塊之晶片之封裝結構，包括：一基板，具有一上表面及一下表面；至少一電性連接體，位於該基板之上表面；一第一晶片，位於該電性連接體上，包括：一晶片本體，具有一上表面及一下表面；至少一穿導孔，貫穿該晶片本體，且顯露於該晶片本體之上表面；一保護層，位於該晶片本體之上表面上，該保護層具有至少一開口，該開口顯露該穿導孔；一球下金屬層(Under Ball Metal,UBM)，位於該保護層之開口，且連接該穿導孔；及至少一凸塊，位於該球下金屬層上，該凸塊包括：一第一金屬層，位於該球下金屬層上；一第二金屬層，位於該第一金屬層上；及一第三金屬層，位於該第二金屬層上；及一第二晶片，位於該第一晶片上，且連接該第三金屬層。
  36. 如請求項35之封裝結構，其中該基板更包括至少一導電通孔，貫穿該基板，且顯露於該基板之上表面及下表面。
  37. 如請求項35之封裝結構，其中該電性連接體係為一銲球。
  38. 如請求項35之封裝結構，更包括一球下金屬層，其位於該晶片本體之下表面，且該電性連接體係為一凸塊，其包括一第四金屬層、一第五金屬層及一第六金屬層，該第四金屬層位於該球下金屬層上，該第五金屬層位於該第四金屬層上，該第六金屬層位於該第五金屬層上。
  39. 如請求項35之封裝結構，其中該第一晶片之晶片本體係為一空白晶片(Dummy Chip)。
  40. 如請求項35之封裝結構，其中該第一晶片之晶片本體係為一有功能的晶片(Device Chip)，該晶片本體更包括至少一銲墊，該銲墊係位於該晶片本體內，且顯露於該下表面。
  41. 如請求項40之封裝結構，其中該第一晶片更包括一影像感測元件(CMOS Image Sensor)，其係位於該晶片本體內，顯露於該下表面，且位於該銲墊外之相對位置。
  42. 如請求項35之封裝結構，其中該第一晶片之穿導孔包括一阻絕層及一導電體，該阻絕層位於該晶片本體之一穿孔之孔壁上，該導電體位於該阻絕層內。
  43. 如請求項35之封裝結構，其中二個相鄰之穿導孔之中心軸之距離定義為一間距，且該凸塊之直徑係小於或等於該間距之三分之二。
  44. 如請求項35之封裝結構，其中該第一晶片之球下金屬層之材質係為鈦銅(TiCu)合金。
  45. 如請求項35之封裝結構，其中該第一晶片之第一金屬層之材質係為銅(Cu)，該第二金屬層之材質係為鎳(Ni)，該第三金屬層之材質係為錫(Sn)或錫銀合金。
  46. 如請求項35之封裝結構，其中該第一晶片之第一金屬層之材質係為銅(Cu)，該第二金屬層之材質係為鎳(Ni)，該第三金屬層之材質係為金(Au)。
  47. 如請求項35之封裝結構，其中該第一晶片之第三金屬層之材質係為金(Au)。
  48. 如請求項35之封裝結構，其中該第一晶片之第一金屬層之厚度係為7μm。
  49. 如請求項35之封裝結構，其中該第一晶片之第二金屬層之厚度係為3μm。
  50. 如請求項35之封裝結構，其中該第一晶片之第三金屬層之厚度係為2μm。
  51. 如請求項35之封裝結構，其中該第一晶片之第三金屬層之厚度係為0.5μm。
  52. 如請求項35之封裝結構，其中該第一晶片更包括一線路層，該線路層係位於該晶片本體之上表面，該球下金屬層係連接該線路層。
  53. 如請求項35之封裝結構，其中該第二晶片具有至少一穿導孔或係為覆晶晶片。
  54. 如請求項35之封裝結構，更包括複數個銲球，位於該基板之下表面。
TW098109809A 2009-03-25 2009-03-25 具有凸塊之晶片及具有凸塊之晶片之封裝結構 TWI394253B (zh)

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