TWI446420B - 用於半導體製程之載體分離方法 - Google Patents

用於半導體製程之載體分離方法 Download PDF

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TWI446420B
TWI446420B TW099128960A TW99128960A TWI446420B TW I446420 B TWI446420 B TW I446420B TW 099128960 A TW099128960 A TW 099128960A TW 99128960 A TW99128960 A TW 99128960A TW I446420 B TWI446420 B TW I446420B
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semiconductor wafer
adhesive
separation method
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TW201209896A (en
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Kuo Pin Yang
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Description

用於半導體製程之載體分離方法
本發明係關於一種載體分離方法，詳言之，係關於一種用於半導體製程之載體分離方法。
參考圖1，其顯示習知半導體製程之載體分離方法之結構示意圖。提供一半導體晶圓10及一載體11。利用一黏膠12，將該半導體晶圓10之該第一表面設置於該載體11上。該半導體晶圓10具有一第一表面101、一第二表面102、一主動層103、複數個導電孔104及複數個導電元件105。該主動層103設置於該第一表面101，且該等導電元件105設置於該主動層103，該等導電孔104設置於該半導體晶圓10內具有一端點1041。一保護層13形成於該第二表面102，該等導電孔104之端點1041突出於該保護層13。
設置一第一夾盤15及一第二夾盤16分別夾制該載體11及該半導體晶圓10之該第二表面102，並加熱使黏膠12分解，再將第一夾盤15及一第二夾盤16以相反方向移動(如箭頭方向)，以移除該載體11，如圖2所示。
上述習知半導體製程之載體分離方法有以下缺點。由於第二夾盤16夾制該半導體晶圓10之該第二表面102，可能造成該半導體晶圓10之損壞，且第二夾盤16橫向移動之力可能造成該半導體晶圓10之破片。
因此，有必要提供一種創新且具進步性的用於半導體製程之載體分離方法，以解決上述問題。
本發明提供一種用於半導體製程之載體分離方法，包括以下步驟：(a)設置一半導體晶圓之一第一表面於一第一載體上；(b)於該半導體晶圓之一第二表面進行表面處理，該第二表面係相對於該第一表面；(c)設置一第二載體於該半導體晶圓之該第二表面；(d)移除該第一載體；(e)設置該半導體晶圓之該第一表面於一框架；及(f)移除該第二載體。
本發明之載體分離方法利用該第二載體支撐保護該半導體晶圓，再移除該第一載體，故不會損壞該半導體晶圓，亦不會造成該半導體晶圓之破片，可提高製程之良率。另外，由於有該第二載體之支撐，可利於殘膠之清除。再者，移除該第一載體及該第二載體之方法簡化，可提高製程效率。
參考圖3至15，其顯示本發明第一實施例用於半導體製程之載體分離方法之結構示意圖。首先參考圖3，提供一半導體晶圓20及一第一載體21。該半導體晶圓20具有一第一表面201、一第二表面202、一主動層203、複數個導電孔204及複數個導電元件205。該第二表面202係相對於該第一表面201。該主動層203設置於該第一表面201，且該等導電元件205設置於該主動層203，該等導電孔204設置於該半導體晶圓20內。
於該第一載體21之一第一表面211形成複數個凹槽213，該等凹槽213不貫穿該第一載體21，且塗佈黏膠22於該第一載體21之該第一表面211，部分黏膠22流入該等凹槽213內，其中該第一載體21的材料可為一半導體晶圓或是玻璃，黏膠22例如是使用住友化學(SUMITOMO CHEMICAL)的X5000。
參考圖4，設置該半導體晶圓20之該第一表面201於該第一載體21上，利用該黏膠22使該半導體晶圓20黏著於該第一載體21上。
於該半導體晶圓20之該第二表面202進行表面處理。以下說明本發明第一實施例之表面處理步驟。參考圖5，研磨並蝕刻該半導體晶圓20之該第二表面202，以顯露該等導電孔204之端點2041。參考圖6，形成一保護層23於該第二表面202，以覆蓋該等導電孔204之端點2041。參考圖7，移除部分保護層23，使得該等導電孔204之端點2041突出於該保護層23。參考圖8，於該等導電孔204之端點2041電鍍形成一表面處理層(surface finish layer)24。
參考圖9及10，設置一第二載體26於該半導體晶圓20之該第二表面202。在本實施例中，係利用一雙面膠帶25將第二載體26設置於該半導體晶圓20之該第二表面202，其中該雙面膠帶25可具有於紫外光照射下黏著性降低的特性，例如是積水化學(SEKISUI CHEMICAL)的SELFA膜；該雙面膠帶25亦可是具有於高溫環境下黏度降低的特性，例如是日東電工株式会社(NITTO DENKO)的熱剝離膜(31950E)，該第二載體26為一支撐體，該第二載體26可為一帽蓋狀，蓋住該半導體晶圓20，該第二載體26可為一透明載體，例如是：玻璃。
參考圖11，移除該第一載體21。在本實施例中，移除該第一載體21包括以下步驟。研磨該第一載體21之一第二表面212，該第二表面212係相對於該第一表面211，以顯露該第一載體21之該等凹槽213。再將該第一載體21及黏膠22浸入一溶劑中，例如是：γ-丁酸內酯(GBL，gamma-Butyrolactone)亦或是單甲基醚丙二醇乙酸酯(PGMEA，Propylene Glycol Monomethyl Ether Acetate)，使黏膠22由該等顯露之凹槽213流出，以移除該第一載體21。
參考圖12，分離該第一載體21後，因可能有部分殘膠會殘留在該半導體晶圓20之該第一表面201，故可於移除該第一載體21後再進行清除殘膠步驟，用以清除該半導體晶圓20之該第一表面201之殘膠。且由於有該第二載體26之支撐，可倒置該半導體晶圓20，以利於殘膠之清除。
參考圖13，設置該半導體晶圓20之該第一表面201於一框架(film frame)27。參考圖14，移除該第二載體26。在本實施例中，移除該第二載體26的方法，係利用照射紫外光亦或是一熱製程來使得雙面膠帶25的黏著性降低，故可同時移除該雙面膠帶25及該第二載體26。參考圖15，利用雷射切割該半導體晶圓20以形成複數個半導體裝置28。
本發明之載體分離方法利用該第二載體26支撐保護該半導體晶圓20，再移除該第一載體21，故不會損壞該半導體晶圓20，亦不會造成該半導體晶圓20之破片，可提高製程之良率。另外，由於有該第二載體26之支撐，可利於殘膠之清除。再者，利用該第一載體21之該等顯露之凹槽213，使黏膠22能由該等顯露之凹槽213流出，可簡化分離第一載體21之製程，以提高製程效率。
參考圖16至18，其顯示本發明第二實施例用於半導體製程之載體分離方法之結構示意圖。本發明第二實施例用於半導體製程之載體分離方法，其設置該半導體晶圓20之第一表面201於第一載體31上及於該半導體晶圓20之第二表面202進行表面處理之步驟大致與本發明第一實施例用於半導體製程之載體分離方法相同，請參考圖9至14。上述步驟不同之處在於，本發明第二實施例用於半導體製程之載體分離方法並沒有於該第一載體31形成複數個凹槽。但同樣地塗佈黏膠32於該第一載體31之該第一表面311，使該半導體晶圓20黏著於該第一載體31上。
參考圖16及17，設置一第二載體36於該半導體晶圓20之該第二表面202。在本實施例中，係利用雙面膠帶35將第二載體36設置於該半導體晶圓20之該第二表面202，其中該第二載體36為一支撐體，該雙面膠帶35可具有於高溫環境下黏度降低的特性，例如是日東電工株式会社(NITTO DENKO)的熱剝離膜(31950E)，該第二載體36可為一半導體晶圓。
參考圖18，移除該第一載體31。在本實施例中，移除該第一載體31包括以下步驟。研磨該第一載體31之一第二表面312，該第二表面312係相對於該第一表面311，使該第一載體31之厚度變薄。再蝕刻該第一載體31，以移除該第一載體31。
分離該第一載體31後，可利用一高溫製程來移除該雙面膠帶35及該第二載體36，然而，清除殘膠、設置於框架及切割步驟與本發明第一實施例用於半導體製程之載體分離方法相同，不再敘述。
參考圖19至21，其顯示本發明第三實施例用於半導體製程之載體分離方法之結構示意圖。本發明第三實施例用於半導體製程之載體分離方法與本發明第二實施例用於半導體製程之載體分離方法大致相同。本發明第三實施例用於半導體製程之載體分離方法塗佈第一黏膠42於該第一載體41之該第一表面411，使該半導體晶圓20黏著於該第一載體41上，其中該第一黏膠42例如是使用住友化學(SUMITOMO CHEMICAL)的X5000。
在本實施例中，係利用一第二黏膠44將第二載體43設置於該半導體晶圓20之該第二表面202，在本實施例中，該第二黏膠44可為一雙面膠帶並具有於紫外光照射下黏著性降低的特性，例如是積水化學(SEKISUI CHEMICAL)的SELFA膜，該第二載體43為透明載體，例如是玻璃。
參考圖20，移除該第一載體41。在本實施例中，移除該第一載體41包括以下步驟。研磨該第一載體41之一第二表面412，該第二表面412係相對於該第一表面411，使該第一載體41之厚度變薄。再蝕刻該第一載體41，以移除該第一載體41。
分離該第一載體41後，清除殘膠之步驟與本發明第二實施例用於半導體製程之載體分離方法相同。參考圖21，設置該半導體晶圓20之該第一表面201於一框架(film frame)47。再移除該第二載體43。在本實施例中，利用紫外光照射該第二載體43，由於該第二載體43為透明載體，且該第二黏膠44具有於紫外光照射下黏著性降低的特性，故可移除該第二黏膠44及該第二載體43。
在其他實施例應用中，若該第二黏膠44具有於高溫環境下黏度降低的特性，，可加熱使其黏度將低，以移除該第二黏膠44與該第二載體43。
參考圖22，其顯示本發明第四實施例用於半導體製程之載體分離方法之結構示意圖。本發明第四實施例用於半導體製程之載體分離方法與本發明第三實施例用於半導體製程之載體分離方法大致相同，不同之處在於，移除該第一載體41。在本實施例中，移除該第一載體41包括以下步驟。設置一第一夾盤(chuck)45及一第二夾盤46分別夾制該第一載體41及該第二載體43。其中，該第一黏膠42為熱融膠，例如是住友化學(SUMITOMO CHEMICAL)的X5000，可加熱以降低其黏度。
於一高溫環境中，將第一夾盤45及一第二夾盤46以相反方向移動，可移除該第一黏膠42與該第一載體41。
分離該第一載體41後，清除殘膠、設置於框架、移除該第二載體43步驟與本發明第三實施例用於半導體製程之載體分離方法相同，不再敘述。
在本發明第四實施例用於半導體製程之載體分離方法中，雖然仍利用第一夾盤45及第二夾盤46分離該第一載體41，但因有該第二載體43支撐保護該半導體晶圓10之該第二表面102，故不會造成該半導體晶圓20之損壞及破片。
參考圖23，其顯示本發明第五實施例用於半導體製程之載體分離方法之結構示意圖。本發明第五實施例用於半導體製程之載體分離方法與本發明第二實施例用於半導體製程之載體分離方法大致相同，不同之處在於，移除該第一載體51。在本實施例中，切割該第一載體51之一部份，該切割部分511貫穿該第一載體51。再將該第一載體51及該第一黏膠52，例如是：住友化學(SUMITOMO CHEMICAL)的X5000，浸入一溶劑中，例如是：γ-丁酸內酯(GBL,gamma-Butyrolactone)亦或是單甲基醚丙二醇乙酸酯(PGMEA,Propylene Glycol Monomethyl Ether Acetate)，使第一黏膠52由該切割部分511流出，以移除該第一載體51。較佳地，在本實施例中，第一黏膠52之厚度可加厚，以具有一誤差容忍度，使得切割時可切割至部分第一黏膠52，而不至於切割且破壞該導電元件205。
分離該第一載體51後，清除殘膠、設置於框架、移除該第二載體54及切割步驟與本發明第二實施例用於半導體製程之載體分離方法相同，不再敘述。
本發明之載體分離方法利用該第二載體支撐保護該半導體晶圓，再移除該第一載體，故不會損壞該半導體晶圓，亦不會造成該半導體晶圓之破片，可提高製程之良率。另外，由於有該第二載體之支撐，可利於殘膠之清除。再者，移除該第一載體及該第二載體之方法簡化，可提高製程效率。
上述實施例僅為說明本發明之原理及其功效，並非限制本發明。因此習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。
10．．．半導體晶圓
11．．．載體
12．．．黏膠
13．．．保護層
14．．．表面處理層
15．．．第一夾盤
16．．．第二夾盤
20．．．半導體晶圓
21．．．第一載體
22．．．黏膠
24．．．表面處理層
25．．．研磨膠帶
26．．．第二載體
27．．．框架
28．．．半導體裝置
31．．．第一載體
32．．．黏膠
35．．．研磨膠帶
36．．．第二載體
41．．．第一載體
42．．．第一黏膠
43．．．第二載體
44．．．第二黏膠
45．．．第一夾盤
46．．．第二夾盤
47．．．框架
51．．．第一載體
52．．．第一黏膠
53．．．第二黏膠
54．．．第二載體
101．．．第一表面
102．．．第二表面
103．．．主動層
104．．．導電孔
105．．．導電元件
201．．．半導體晶圓之第一表面
202．．．半導體晶圓之第二表面
203．．．主動層
204．．．導電孔
205．．．導電元件
211．．．第一載體之第一表面
212．．．第一載體之第二表面
213．．．凹槽
311．．．第一載體之第一表面
312．．．第一載體之第二表面
411．．．第一載體之第一表面
412．．．第一載體之第二表面
511．．．切割部分
1041．．．端點
2041．．．端點
圖1至2顯示習知半導體製程之載體分離方法之結構示意圖；
圖3至15顯示本發明第一實施例用於半導體製程之載體分離方法之結構示意圖；
圖16至18顯示本發明第二實施例用於半導體製程之載體分離方法之結構示意圖；
圖19至21顯示本發明第三實施例用於半導體製程之載體分離方法之結構示意圖；
圖22顯示本發明第四實施例用於半導體製程之載體分離方法之結構示意圖；及
圖23顯示本發明第五實施例用於半導體製程之載體分離方法之結構示意圖。
20‧‧‧半導體晶圓
22‧‧‧黏膠
25‧‧‧研磨膠帶
26‧‧‧第二載體
201‧‧‧半導體晶圓之第一表面
202‧‧‧半導體晶圓之第二表面
203‧‧‧主動層
204‧‧‧導電孔
205‧‧‧導電元件
211‧‧‧第一載體之第一表面
212‧‧‧第一載體之第二表面
213‧‧‧凹槽

Claims (11)

  1. 一種用於半導體製程之載體分離方法，包括以下步驟：(a)設置一半導體晶圓之一第一表面於一第一載體上，於該第一載體之一第一表面形成複數個凹槽，該等凹槽不貫穿該第一載體，且塗佈黏膠於該第一載體之該第一表面，使該半導體晶圓黏著於該第一載體上；(b)於該半導體晶圓之一第二表面進行表面處理，該第二表面係相對於該第一表面；(c)設置一第二載體於該半導體晶圓之該第二表面；(d)移除該第一載體；(e)設置該半導體晶圓之該第一表面於一框架；及(f)移除該第二載體。
  2. 如請求項1之載體分離方法，其中在步驟(c)中，係利用一研磨膠帶將第二載體設置於該半導體晶圓之該第二表面，其中該第二載體為一支撐體。
  3. 如請求項2之載體分離方法，其中在步驟(d)中，另包括以下步驟：(d1)研磨該第一載體之一第二表面，該第二表面係相對於該第一表面，以顯露該第一載體之該等凹槽；及(d2)將該第一載體及黏膠浸入一溶液中，使黏膠由該等顯露之凹槽流出，以移除該第一載體。
  4. 如請求項3之載體分離方法，其中在步驟(d)之後，另包括一清除殘膠步驟，用以清除該半導體晶圓之該第一表 面之殘膠。
  5. 如請求項1之載體分離方法，其中，在步驟(c)中，係利用一第二黏膠將第二載體設置於該半導體晶圓之該第二表面，在步驟(f)中，利用紫外光照射該第二載體，，以移除該第二黏膠及該第二載體。
  6. 如請求項1之載體分離方法，其中在步驟(c)中，係利用一第二黏膠將第二載體設置於該半導體晶圓之該第二表面，在步驟(f)中，加熱以移除該第二黏膠與該第二載體。
  7. 一種用於半導體製程之載體分離方法，包括以下步驟：(a)設置一半導體晶圓之一第一表面於一第一載體上，塗佈第一黏膠於該第一載體之一第一表面，使該半導體晶圓黏著於該第一載體上；(b)於該半導體晶圓之一第二表面進行表面處理，該第二表面係相對於該第一表面；(c)設置一第二載體於該半導體晶圓之該第二表面；(d)移除該第一載體，在步驟(d)中，另包括以下步驟：(d1)設置一第一夾盤及一第二夾盤分別夾制該第一載體及該第二載體；(d2)加熱該第一黏膠；及(d3)將第一夾盤及一第二夾盤以相反方向移動，以移除該第一載體與該第一黏膠；(e)設置該半導體晶圓之該第一表面於一框架；及(f)移除該第二載體。
  8. 如請求項7之載體分離方法，其中在步驟(c)中，係利用一第二黏膠將第二載體設置於該半導體晶圓之該第二表面，在步驟(f)中，利用紫外光照射該第二載體，以移除該第二黏膠及該第二載體。
  9. 一種用於半導體製程之載體分離方法，包括以下步驟：(a)設置一半導體晶圓之一第一表面於一第一載體上，塗佈第一黏膠於該第一載體之一第一表面，使該半導體晶圓黏著於該第一載體上；(b)於該半導體晶圓之一第二表面進行表面處理，該第二表面係相對於該第一表面；(c)設置一第二載體於該半導體晶圓之該第二表面；(d)移除該第一載體，在步驟(d)中，另包括以下步驟：(d1)切割該第一載體之一部份，該切割部分貫穿該第一載體；及(d2)將該第一載體及該第一黏膠浸入一溶液中，使黏膠由該切割部分流出，以移除該第一載體；(e)設置該半導體晶圓之該第一表面於一框架；及(f)移除該第二載體。
  10. 如請求項9之載體分離方法，其中在步驟(d1)中，切割至部分第一黏膠。
  11. 一種用於半導體製程之載體分離方法，包括以下步驟：(a)設置一半導體晶圓之一第一表面於一第一載體上；(b)於該半導體晶圓之一第二表面進行表面處理，該第二表面係相對於該第一表面； (c)設置一第二載體於該半導體晶圓之該第二表面；(d)移除該第一載體，在步驟(d)中，另包括以下步驟：；(d1)研磨該第一載體之一第二表面，該第二表面係相對於該第一表面，使該第一載體之厚度變薄；(d2)蝕刻該第一載體，以移除該第一載體；(e)設置該半導體晶圓之該第一表面於一框架；及(f)移除該第二載體。
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