TWI805983B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI805983B
TWI805983B TW110100707A TW110100707A TWI805983B TW I805983 B TWI805983 B TW I805983B TW 110100707 A TW110100707 A TW 110100707A TW 110100707 A TW110100707 A TW 110100707A TW I805983 B TWI805983 B TW I805983B
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Taiwan
Prior art keywords
layer
pattern
conductive
semiconductor device
opening
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TW110100707A
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TW202137448A (zh
Inventor
愼重垣
李瑌眞
李仁榮
崔智旻
韓正勳
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南韓商三星電子股份有限公司
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Priority claimed from KR1020200080050A external-priority patent/KR20210121999A/ko
Application filed by 南韓商三星電子股份有限公司 filed Critical 南韓商三星電子股份有限公司
Publication of TW202137448A publication Critical patent/TW202137448A/zh
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Abstract

揭露一種半導體裝置，所述半導體裝置包括：半導體基板；導電接墊，位於半導體基板的第一表面上；鈍化層，位於半導體基板的第一表面上，鈍化層具有暴露出導電接墊的第一開口；有機介電層，位於鈍化層上，有機介電層具有第二開口；以及凸塊結構，位於導電接墊上且位於第一開口及第二開口中。有機介電層包含與鈍化層的材料不同的材料。第二開口在空間上連接至第一開口且暴露出鈍化層的一部分。凸塊結構包括與鈍化層及有機介電層接觸的柱圖案。

Description

半導體裝置 [相關申請案的交叉參考]
本申請案主張優先於在2020年3月27日在韓國智慧財產局提出申請的韓國專利申請案第10-2020-0037698號以及在2020年6月30日在韓國智慧財產局提出申請的韓國專利申請案第10-2020-0080050號，所述韓國專利申請案的揭露內容全文特此併入供參考。
本發明概念是有關於一種半導體裝置，且更具體而言，是有關於一種包括凸塊結構的半導體裝置。
半導體裝置已迅速發展，以增加電極端子的數目並減小電極端子之間的節距。與此同時，對減小半導體裝置的大小的研究日益增多。半導體裝置一般而言具有電性連接端子(例如焊料球或凸塊)，用於與其他電子裝置或印刷電路板(printed circuit board，PCB)電性連接。半導體裝置受益於具有高度可靠的連接端子。
本發明概念的一些示例性實施例提供一種具有增強的 耐久性及可靠性的半導體裝置。
根據本發明概念的一些示例性實施例，一種半導體裝置可包括：半導體基板；導電接墊，位於所述半導體基板的第一表面上；鈍化層，位於所述半導體基板的所述第一表面上，所述鈍化層具有暴露出所述導電接墊的一部分的第一開口；有機介電層，位於所述鈍化層上，所述有機介電層具有第二開口；以及凸塊結構，位於所述導電接墊上且位於所述第一開口及所述第二開口中。所述有機介電層可包含與所述鈍化層的材料不同的材料。所述第二開口可在空間上連接至所述第一開口且可暴露出所述鈍化層的一部分。所述凸塊結構可包括與所述鈍化層及所述有機介電層接觸的柱圖案。
根據本發明概念的一些示例性實施例，一種半導體裝置可包括：半導體基板；導電接墊，位於所述半導體基板的第一表面上；含矽層，位於所述半導體基板的所述第一表面上且暴露出所述導電接墊的一部分；聚合物層，位於所述含矽層上且暴露出所述含矽層的一部分及所述導電接墊的所述一部分；柱圖案，位於所述導電接墊上且與所述含矽層及所述聚合物層接觸；以及焊料圖案，位於所述柱圖案上。
根據本發明概念的一些示例性實施例，一種半導體裝置可包括：半導體基板；電路層，位於所述半導體基板上；導電接墊，位於所述電路層上；含矽層，位於所述導電接墊上，所述含矽層具有第一開口；聚合物層，位於所述含矽層上，所述聚合物 層具有第二開口；以及凸塊結構，設置於所述導電接墊上。所述電路層可包括：積體電路，位於所述半導體基板的第一表面上；介電層，位於所述半導體基板的所述第一表面上，所述介電層覆蓋所述積體電路；以及內連結構，位於所述介電層中，所述內連結構耦合至所述積體電路，所述內連結構包括配線圖案及通孔圖案。所述第一開口可暴露出所述導電接墊的一部分及所述含矽層的內壁。所述第二開口可在空間上連接至所述第一開口且可暴露出所述含矽層的頂表面。所述凸塊結構可包括：柱圖案，位於所述第一開口及所述第二開口中且與所述導電接墊、所述含矽層的所述內壁及被暴露出的所述頂表面、以及所述聚合物層的內壁及頂表面接觸；以及焊料圖案，位於所述柱圖案上。所述柱圖案可包括：晶種圖案，與所述導電接墊接觸；以及導電圖案，位於所述晶種圖案上。
1:半導體封裝
1A:半導體裝置
100:半導體裝置/最上部半導體裝置/下部半導體裝置/上部半導體裝置/最下部半導體裝置
110:基板
110a:第一表面/頂表面
110b:第二表面
120:電路層
121:介電層
125:積體電路
127:內連結構
130:導電接墊
140:鈍化層
141:第一鈍化層
141c、142c、150c:內壁
142:第二鈍化層
149:第一開口
150:有機介電層
150a、161a:頂表面
159:第二開口
160:凸塊結構
161:柱圖案
161b:底表面
161x:第一底表面
161y:第二底表面
161z:第三底表面
162:晶種圖案
163:導電圖案
163c:上側壁
165:焊料圖案
170:上部接墊
180:貫通電極
200:模製層
300:第一半導體晶片
310:基礎基板
330:電路圖案
350:第一結合凸塊
370:上部導電接墊
380:導電貫通電極
400:第二半導體晶片
430:晶片接墊
450:第二結合凸塊
710:第一底部填充圖案
720:第二底部填充圖案
730:第三底部填充圖案
800:中介層基板
820:金屬接墊
830:金屬線
850:中介層凸塊
900:封裝基板
910:介電基礎層
920:基板接墊
930:內部線
950:外部端子
1000:晶片堆疊
1631:第一導電部/層
1631a:頂表面
1632:第二導電部/層
1633:第三導電部/層
I、IV:區段
II-III:線
P1、P2、P3:節距
W1、W2、W3:寬度
圖1A示出顯示根據一些示例性實施例的半導體裝置的剖視圖。
圖1B示出顯示根據一些示例性實施例的半導體裝置中所包括的柱圖案的平面圖。
圖1C示出放大剖視圖，所述放大剖視圖是沿著圖1B所示線II-III截取的、對應於圖1A所示區段I。
圖2A示出顯示根據一些示例性實施例的半導體裝置的凸塊結構的剖視圖。
圖2B示出顯示根據一些示例性實施例的半導體裝置的凸塊結構的剖視圖。
圖2C示出顯示根據一些示例性實施例的半導體裝置的鈍化層的剖視圖。
圖2D示出顯示根據一些示例性實施例的半導體裝置的鈍化層的剖視圖。
圖3示出顯示根據一些示例性實施例的半導體封裝的剖視圖。
圖4A示出顯示根據一些示例性實施例的半導體封裝的剖視圖。
圖4B示出顯示圖4A所示區段IV的放大視圖。
在本說明中，相同的參考編號可指示相同的組件。
以下現將闡述根據本發明概念的一種半導體裝置及一種製作所述半導體裝置的方法。
圖1A示出顯示根據一些示例性實施例的半導體裝置的剖視圖。圖1B示出顯示根據一些示例性實施例的半導體裝置中所包括的柱圖案的平面圖。圖1C示出放大剖視圖，所述放大剖視圖是沿著圖1B所示線II-III截取的、對應於圖1A所示區段I。
參照圖1A、圖1B及圖1C，半導體裝置100可包括基板110、電路層120、導電接墊130、鈍化層140、有機介電層150及凸塊結構160。半導體裝置100可為半導體晶片。舉例而言，半 導體裝置100可為記憶體晶片、邏輯晶片或緩衝晶片。基板110可為半導體基板。舉例而言，基板110可包含半導體材料(例如矽、鍺或矽鍺)或者可由所述半導體材料形成。基板110可具有彼此相對的第一表面110a與第二表面110b。
電路層120可設置於基板110的第一表面110a上。如圖1C中所示，電路層120可包括介電層121、積體電路125及內連結構127。積體電路125可設置於基板110的第一表面110a上。積體電路125可包括例如電晶體及/或電性連接電晶體的配線。介電層121可設置於基板110的第一表面110a上且可覆蓋積體電路125。儘管為了簡化而未示出，但介電層121可包括多個堆疊層。介電層121可包含含矽材料或可由含矽材料形成。舉例而言，介電層121可為絕緣體層或者可包括在垂直方向上堆疊的多個絕緣體層。舉例而言，介電層121可包含氧化矽、氮化矽、氮氧化矽、及/或正矽酸四乙酯，或者可由氧化矽、氮化矽、氮氧化矽、及/或正矽酸四乙酯形成。內連結構127可設置於介電層121中。內連結構127可電性連接至積體電路125。在本說明中，當元件被闡述為電性連接至半導體裝置時，所述元件可電性連接至半導體裝置的積體電路，使得訊號可在元件與積體電路中的一或多者之間傳遞。當兩個組件被闡述為電性連接/耦合至彼此時，所述兩個組件可直接連接/耦合至彼此(例如，使得它們實體觸摸且亦被連接以在彼此之間傳遞電子訊號)，或者所述兩個組件可藉由其他導電組件間接連接/耦合至彼此(例如，使得它們不會彼此實體接觸， 但它們仍然被連接以在彼此之間傳遞電子訊號)。內連結構127可包括配線圖案及連接至配線圖案的通孔圖案。配線圖案及通孔圖案可為多個配線圖案及通孔圖案的部分。每一配線圖案可在與基板110的第一表面110a平行的方向上延伸。舉例而言，配線圖案可具有沿著配線圖案縱向延伸且在與第一表面110a平行的方向上延伸的主軸。配線圖案可包括插置於介電層121中所包括的層(例如，絕緣體層)之間的多個配線圖案。通孔圖案可各自具有軸向對稱性，且軸向對稱性的對稱軸可與基板110的第一表面110a交叉。舉例而言，通孔圖案的對稱軸可與基板110的第一表面110a垂直。通孔圖案可設置於介電層121中所包括的層(例如，絕緣體層)中的至少一者中。舉例而言，介電層121可包括堆疊於一起的多個子層(例如，絕緣體層)，且通孔圖案可穿透所述子層中的一者。在不同的各個子層中可包括有多個通孔圖案。每一通孔圖案可設置於多個配線圖案之間且耦合至所述多個配線圖案。配線圖案中的每一者可具有較對應的通孔圖案的寬度小的寬度。在此種情形中，對應的通孔圖案可直接連接至一或多個對應的配線圖案。內連結構127可包含金屬，例如鋁或銅。
導電接墊130可設置於基板110的第一表面110a上/之上。在本說明中，當某個組件被闡述為位於另一組件上時，所述某個組件可直接形成於所述另一組件上或者在所述某個組件與所述另一組件之間可插置有第三個組件。舉例而言，導電接墊130可設置於電路層120上。導電接墊130可藉由內連結構127電性 連接至積體電路125。導電接墊130可為晶片接墊。舉例而言，晶片接墊可為上面施加有焊料球或其他焊料材料的導電接墊且在晶片接墊與其中整合有電路及/或半導體裝置的半導體基板之間未施加有其他焊料球或材料。導電接墊130可包含金屬(例如鋁)或者可由所述金屬形成。儘管未示出，但在導電接墊130與電路層120之間可進一步插置有接墊晶種層。接墊晶種層可用於形成導電接墊130。導電接墊130可包括邊緣部及中心部。當在平面圖中觀察時，導電接墊130的邊緣部可環繞導電接墊130的中心部。導電接墊130的邊緣部可包括導電接墊130的側壁及鄰近側壁的部。
鈍化層140可設置於基板110的第一表面110a上。鈍化層140可覆蓋電路層120。鈍化層140可包括第一鈍化層141及第二鈍化層142。第一鈍化層141可設置於電路層120上，並且可覆蓋介電層121的頂表面且亦覆蓋導電接墊130的側壁及邊緣部。第一鈍化層141可包含含矽介電材料。第一鈍化層141可包含例如氧化矽及/或正矽酸四乙酯。第一鈍化層141可不包含氮。第二鈍化層142可設置於第一鈍化層141上。第二鈍化層142可具有介電特性。第二鈍化層142可為含矽層。第二鈍化層142可包含與第一鈍化層141的材料不同的材料。舉例而言，第二鈍化層142可包含與第一鈍化層141的含矽介電材料不同的含矽介電材料或者可由與第一鈍化層141的含矽介電材料不同的含矽介電材料形成。舉例而言，第一鈍化層141與第二鈍化層142二者可包含彼此不同的含矽介電材料。第二鈍化層142可包含矽及氮。 第二鈍化層142可包含例如氮化矽、氮氧化矽、碳氮化矽、及/或氮氧化矽碳。鈍化層140可具有第一開口149，且第一開口149可暴露出導電接墊130的頂表面。第一開口149可穿透第一鈍化層141及第二鈍化層142。第一開口149可暴露出第一鈍化層141的內壁141c及第二鈍化層142的內壁142c。舉例而言，第一鈍化層141的內壁141c可為第一開口149的側壁的形成於第一鈍化層141中的一部分，且第二鈍化層142的內壁142c可為第一開口149的側壁的形成於第二鈍化層142中的另一部分。第二鈍化層142的內壁142c可與第一鈍化層141的內壁141c共面。舉例而言，共同形成第一開口149的側壁的內壁141c與內壁142c可線性地連接(例如，在剖視圖中)，且可具有實質上線性的斜率。舉例而言，第一鈍化層141的內壁141c的頂端與第二鈍化層142的內壁142c的底端可彼此接觸，且內壁141c與內壁142c可相對於基板110的第一表面110a具有實質上相同的傾斜角。第一開口149可具有較導電接墊130的寬度小的寬度W1。舉例而言，第一開口149的寬度W1可約5微米以上且小於約10微米。寬度W1可為第一開口149的下部部分的寬度/直徑或者第一開口149的底表面/端的寬度/直徑。第一開口149的底表面可與導電接墊130的被暴露出的頂表面對應。舉例而言，鈍化層140可暴露出導電接墊130的中心部處的頂表面。如圖1B中所示，第一開口149可具有圓形形狀，例如當在平面圖中觀察時。舉例而言，第一開口149可具有截頭圓錐形狀，且可具有圓形頂端及圓形底端。舉例而言，第 一開口149的圓形頂端可具有較第一開口149的圓形底端大的直徑。
當在本文中提及定向、佈局、位置、形狀、大小、數量或其它度量時，使用例如「相同」、「相等」、「平坦」或「共面」等用語不一定意指完全相同的定向、佈局、位置、形狀、大小、數量或其它度量，而是旨在囊括在例如由於製造製程而可能發生的可接受變化內的幾乎相同的定向、佈局、位置、形狀、大小、數量或其它度量。除非上下文或其它陳述另有指示，否則用語「實質上」在本文中可用於強調此含義。舉例而言，被闡述為「實質上相同」、「實質上相等」或「實質上平坦」的項可為完全相同、相等或平坦，或者可為在例如由於製造製程而可能發生的可接受的變化內相同、相等或平坦。
例如「約」或「近似」等用語可反映僅以相對小的方式及/或以不顯著改變某些元件的操作、功能或結構的方式變化的數量、大小、定向或佈局。舉例而言，自「約0.1至約1」的範圍可囊括例如在0.1左右偏差0%至5%及在1左右偏差0%至5%的範圍，尤其是在此種偏差保持與所列範圍相同的效果的情況下。
有機介電層150可設置於鈍化層140的頂表面上。舉例而言，有機介電層150可覆蓋第二鈍化層142的頂表面。除非本說明中另有陳述，否則在鈍化層140由第一鈍化層141及第二鈍化層142構成的情形中，鈍化層140的頂表面可表示第二鈍化層142的頂表面。有機介電層150可具有第二開口159。有機介電層 150可具有彼此相對的頂表面150a與底表面，且第二開口159可穿透有機介電層150的頂表面150a及底表面。舉例而言，第二開口159可穿透包括頂表面150a及底表面的有機介電層150。當在平面圖中觀察時，第二開口159可與第一開口149交疊。第二開口159可在空間上連接至第一開口149。如圖1B中所示，當在平面圖中觀察時，第二開口159可具有圓形形狀。舉例而言，第二開口159可具有截頭圓錐形狀，且可具有圓形頂端及圓形底端。舉例而言，第二開口159的圓形頂端可具有較第二開口159的圓形底端大的直徑。第二開口159可具有較第一開口149的直徑大的直徑。舉例而言，第二開口159的圓形底端的直徑可大於第一開口149的圓形頂端的直徑。第二開口159可具有較第一開口149的寬度W1大的寬度W2。舉例而言，第二開口159的寬度W2可約10微米以上且小於約20微米。寬度W2可為在有機介電層150的底表面處量測的寬度/直徑或者在第二開口159的底表面/端處量測的寬度/直徑。有機介電層150的底表面可接觸鈍化層140。第二開口159可暴露出鈍化層140的頂表面的一部分及有機介電層150的內壁150c。舉例而言，有機介電層150的內壁150c可為第二開口159的側壁。有機介電層150的內壁150c可不與第二鈍化層142的內壁142c對齊。舉例而言，由內壁150c在剖視圖中形成的線可不處於由內壁142c在剖視圖中形成的同一條線上，如圖1C中所示。舉例而言，內壁150c與內壁142c可不垂直交疊，如圖1C中所示。鈍化層140可具有由鈍化層140的內壁及被暴露 出的頂表面形成的台階狀結構，且有機介電層150亦可具有由有機介電層150的內壁150c及頂表面150a形成的台階狀結構。舉例而言，由第一開口149與第二開口159共同形成的開口可具有台階狀側壁，所述台階狀側壁具有由內壁141c、142c及150c形成的傾斜部分以及由鈍化層140的被暴露出的頂表面形成的平整部分。有機介電層150可為聚合物層。有機介電層150可包含例如聚醯亞胺。聚醯亞胺可包括感光性聚醯亞胺。
應理解，當一個元件被指「連接」或「耦合」至另一元件或位於另一個元件「上」時，所述元件可直接連接或耦合至所述另一元件或位於所述另一元件上，或者可存在中間元件。相反，當一個元件被指「直接連接」或「直接耦合」至另一元件，或者被指「接觸(contacting或in contact with)」另一元件時，不存在中間元件。用於闡述元件之間關係的其他詞語應以類似的方式來解釋(例如，「位於...之間」與「直接位於...之間」、「鄰近」與「直接鄰近」等)。舉例而言，除非上下文另有指示，否則本文中使用的用語「接觸」指的是直接連接(即，觸摸)。
凸塊結構160可設置於導電接墊130的頂表面上且耦合至導電接墊130。舉例而言，凸塊結構160可接觸導電接墊130。凸塊結構160可包括柱圖案161及焊料圖案165。舉例而言，焊料圖案165可為焊料球。柱圖案161可設置於導電接墊130的頂表面上且設置於第一開口149及第二開口159中。柱圖案161可填充第一開口149及第二開口159。如圖1B中所示，柱圖案161可 具有圓形形狀，例如，當在平面圖中觀察時。舉例而言，柱圖案161的頂表面161a可具有圓形形狀。柱圖案161可具有較第二開口159的直徑大的直徑。舉例而言，柱圖案161的頂表面161a可具有較第二開口159的頂部部分的直徑大的直徑。柱圖案161可具有較第二開口159的寬度W2大的寬度W3。舉例而言，柱圖案161的寬度W3可20微米以上且可約70微米以下。寬度W3可為柱圖案161的上部部分的寬度/直徑。舉例而言，寬度W3可為柱圖案161的頂表面161a處的寬度/直徑。柱圖案161可具有設置於有機介電層150的頂表面150a上的側壁，且柱圖案161的設置於有機介電層150的頂表面150a上的側壁可與有機介電層150的頂表面150a實質上垂直。因此，柱圖案161可在較有機介電層150的頂表面150a的水平高的水平的範圍內具有實質上均勻的寬度/直徑。舉例而言，柱圖案161的設置於較有機介電層150的頂表面150a高的水平處的一部分可具有圓柱形狀。由於柱圖案161的寬度W3大於第二開口159的寬度W2，因此柱圖案161可覆蓋有機介電層150的頂表面150a的一部分。舉例而言，本揭露中的寬度W1、W2及W3可為柱圖案161的在與基板110的頂表面110a平行的水平方向上量測的寬度/直徑。
柱圖案161的頂表面161a可為實質上平整的。當在本說明中某個表面被闡述為平整的時，所述表面可能包括在製作製程中可能出現的誤差，且可排除台階差、突起或凹陷的有意形成。柱圖案161的頂表面161a可與基板110的第一表面110a平行。柱 圖案161可具有與頂表面161a相對的底表面161b。舉例而言，柱圖案161的底表面161b可面對及/或接觸形成於柱圖案161下方的頂表面，例如導電接墊130的頂表面、鈍化層140的頂表面及/或有機介電層150的頂表面。柱圖案161的底表面161b可具有由鈍化層140及有機介電層150引起的台階差。舉例而言，柱圖案161的底表面161b可包括第一底表面161x、第二底表面161y及第三底表面161z。柱圖案161的第一底表面161x可與有機介電層150的頂表面150a接觸。柱圖案161的第二底表面161y可位於較第一底表面161x的水平低的水平處。柱圖案161的第二底表面161y可與鈍化層140的頂表面接觸。柱圖案161的第三底表面161z可位於較第二底表面161y的水平低的水平處。柱圖案161的第三底表面161z可與導電接墊130接觸。在本說明中，語言「水平」可指示垂直水平，且用語「垂直」可對應於與基板110的第一表面110a垂直的方向。可在與基板110的第一表面110a垂直的方向上量測兩個表面之間的水平差。
第二鈍化層142可用作黏合層，例如用於將柱圖案161貼合至下部結構(鈍化層/介電層/基板)。由於柱圖案161與第二鈍化層142接觸，因此柱圖案161可穩定地貼合至介電層121及第一鈍化層141。舉例而言，柱圖案161與第二鈍化層142之間的黏合力可大於柱圖案161與介電層121之間的黏合力。柱圖案161與第二鈍化層142之間的黏合力可大於柱圖案161與第一鈍化層141之間的黏合力。
有機介電層150可具有較第二鈍化層142的柔軟度大的柔軟度。有機介電層150可具有相對低的硬度。舉例而言，有機介電層150可具有較第二鈍化層142的硬度低的硬度。因此，有機介電層150可減輕施加至凸塊結構160的應力。應力可能是物理應力。舉例而言，應力可為例如在重佈線基板、封裝基板或電路板上進行的安裝製程中施加至凸塊結構160的壓力。柱圖案161與有機介電層150之間的接觸面積可大於柱圖案161與第二鈍化層142之間的接觸面積，此可有益於減小施加至凸塊結構160的應力。因此，可在將半導體裝置100安裝於例如重佈線基板、封裝基板或電路板上的期間防止柱圖案161受到損壞/保護柱圖案161免受損壞。柱圖案161與有機介電層150之間的接觸面積可包括柱圖案161與有機介電層150的內壁150c之間的接觸面積以及柱圖案161與有機介電層150的頂表面150a之間的接觸面積。柱圖案161與第二鈍化層142之間的接觸面積可包括柱圖案161與第二鈍化層142的內壁142c之間的接觸面積以及柱圖案161與第二鈍化層142的頂表面之間的接觸面積。
柱圖案161可包括晶種圖案162及導電圖案163。晶種圖案162可設置於導電接墊130的頂表面上，且可延伸至鈍化層140及有機介電層150上。晶種圖案162可共形地覆蓋導電接墊130的被暴露出的頂表面、鈍化層140的內壁及頂表面、以及有機介電層150的內壁150c及頂表面150a的一部分。晶種圖案162可與導電接墊130的被暴露出的所述頂表面、鈍化層140的內壁 及頂表面、以及有機介電層150的內壁150c及頂表面150a實體接觸。除非本說明中另有陳述，否則鈍化層140的內壁可包括第一鈍化層141的內壁141c及第二鈍化層142的內壁142c。除非上下文另有指示，否則本文中使用的用語「實體接觸」指的是類似於如上所述的「接觸」的直接連接(即，觸摸)。晶種圖案162可包含例如選自鈦及銅中的至少一者。柱圖案161的底表面161b可指示晶種圖案162的底表面。導電圖案163可形成於晶種圖案162上。導電圖案163可包含金屬，例如銅、鎳、或其合金。導電圖案163可藉由其中晶種圖案162被用作電極的鍍覆製程形成。晶種圖案162可暴露出導電圖案163的上側壁163c。導電圖案163的上側壁163c可位於較有機介電層150的頂表面150a的水平高的水平處。柱圖案161的頂表面161a可指示導電圖案163的頂表面。
焊料圖案165可設置於柱圖案161的頂表面161a上且電性連接至柱圖案161。焊料圖案165可包含與柱圖案161的材料不同的材料。舉例而言，焊料圖案165可包含錫(Sn)、銀(Ag)、鋅(Zn)、鉛(Pd)、或其合金。
為了在除了圖1C、圖2A至圖2D、及圖4B之外的圖中簡化柱圖案161的例示，將不對晶種圖案162與導電圖案163進行區分。然而，此並非旨在自實施例排除晶種圖案162及/或導電圖案163。此外，除了圖1C、圖2A至圖2D、及圖4B之外的圖會省略介電層121、積體電路125及內連結構127的例示，但此並 非旨在自本發明概念排除介電層121、積體電路125及內連結構127中的任意者。在圖中省略該些特徵僅僅是為了簡化例示，且在本申請案中揭露的且與所述圖兼容的任意特徵可應用於所述圖。類似地，在本揭露的實施例中，可應用及/或互換其他兼容及/或可互換的特徵。
圖2A示出顯示根據一些示例性實施例的半導體裝置的凸塊結構的放大剖視圖，所述放大剖視圖是沿著圖1B所示線II-III截取的且對應於圖1A所示區段I。以下將參照圖1A及圖1B以及圖2A，並且為了避免重複說明將進行省略。
參照圖2A，半導體裝置可包括基板110、電路層120、導電接墊130、鈍化層140、有機介電層150、晶種圖案162、導電圖案163及焊料圖案165。晶種圖案162、導電圖案163及焊料圖案165可與以上參照圖1A至圖1C論述的晶種圖案162、導電圖案163及焊料圖案165實質上相同。然而，導電圖案163可由多個層形成(如圖2A中所示)，此與圖1C中所示的實施例的導電圖案163不同(乃因圖1C所示導電圖案163是單個層)。舉例而言，導電圖案163可包括垂直堆疊的導電層，所述垂直堆疊的導電層包括第一導電部/層1631、第二導電部/層1632及第三導電部/層1633。第一導電部1631可對應於導電圖案163的下部部分。第一導電部1631可覆蓋晶種圖案162。第一導電部1631可設置於第一開口149及第二開口159中，且可設置於有機介電層150的頂表面150a的一部分上。第一導電部1631可具有處於較有機介 電層150的頂表面150a的水平高的水平處的頂表面1631a。第一導電部1631的頂表面1631a可為實質上平整的。第一導電部1631可包含第一金屬或者可由第一金屬形成。第一金屬可為例如銅、鎳、鎢、鋁等。
第二導電部1632可設置於第一導電部1631上。第二導電部1632可與晶種圖案162間隔開。舉例而言，第一導電部/層1631可插置於晶種圖案162與第二導電部/層1632之間的所有區域中且可填充晶種圖案162與第二導電部/層1632之間的間隙，如圖2A中所示。第二導電部1632可包含與第一金屬不同的第二金屬或者可由所述第二金屬形成。第二金屬可為例如鎳、銅、鎢、鋁等。第二導電部1632可具有實質上平整的頂表面。
第三導電部1633可設置於第二導電部1632上。第二導電部1632可插置於第一導電部1631與第三導電部1633之間。舉例而言，第二導電部/層1632可插置於第一導電部/層1631與第三導電部/層1633之間的所有區域中且可填充第一導電部/層1631與第三導電部/層1633之間的間隙，如圖2A中所示。第三導電部1633可包含第一金屬或者可由第一金屬形成。舉例而言，第三導電部1633可包含與第一導電部1631的金屬相同的金屬。根據一些示例性實施例，由於導電圖案163包括第一導電部1631、第二導電部1632及第三導電部1633，因此調整導電圖案163的特性可能是有益的。
圖2B示出顯示根據一些示例性實施例的半導體裝置的 凸塊結構的放大剖視圖，所述放大剖視圖是沿著圖1B所示線II-III截取的且對應於圖1A所示區段I。以下將參照圖1A及圖1B以及圖2B，並且為了避免重複說明將進行省略。
參照圖2B，半導體裝置可包括基板110、電路層120、導電接墊130、鈍化層140、有機介電層150、包括晶種圖案162及導電圖案163的柱圖案161、以及焊料圖案165。柱圖案161及焊料圖案165可與以上在圖1A至圖1C中論述的柱圖案161及焊料圖案165實質上相同。然而，在圖2B中所示的實施例中，晶種圖案162可延伸至導電圖案163的上側壁163c上且覆蓋導電圖案163的上側壁163c。晶種圖案162可具有處於與導電圖案163的頂表面的水平實質上相同的水平處的最上表面。作為另一種選擇，導電圖案163可包括第一導電部1631、第二導電部1632及第三導電部1633，如圖2A中所論述。
在圖2A及圖2B的實施例中，基板110、電路層120、有機介電層150可與以上在圖1A至圖1C中論述的基板110、電路層120、有機介電層150實質上相同。
圖2C示出顯示根據一些示例性實施例的半導體裝置的鈍化層的放大剖視圖，所述放大剖視圖是沿著圖1B所示線II-III截取的且對應於圖1A所示區段I。以下將參照圖1A及圖1B以及圖2C，並且為了避免重複說明將進行省略。
參照圖2C，半導體裝置可包括基板110、電路層120、導電接墊130、鈍化層140、有機介電層150及凸塊結構160。鈍 化層140可由單個層形成。舉例而言，鈍化層140可包括第二鈍化層142，但可不包括圖1C中論述的第一鈍化層141。第二鈍化層142可與電路層120的頂表面及有機介電層150的底表面實體接觸。第二鈍化層142可與導電接墊130接觸。舉例而言，第二鈍化層142可與導電接墊130的側壁以及導電接墊130的邊緣部的頂表面實體接觸。導電接墊130可設置於第二鈍化層142中。如上所述，第二鈍化層142可為含矽層。第二鈍化層142可包含矽及氮。第二鈍化層142可包含例如氮化矽、氮氧化矽、碳氮化矽、及/或氮氧化矽碳。根據一些示例性實施例，柱圖案161與第二鈍化層142之間可具有增大的接觸面積，使得柱圖案161可穩定地貼合至導電接墊130/介電層121/半導體裝置100。舉例而言，第一開口149的傾斜側壁及第二開口159的傾斜側壁、鈍化層140的被暴露出的頂表面、位於有機介電層150的頂表面的一部分上的柱圖案161、及/或層及圖案的相應材料對於將凸塊結構160可靠地貼合於導電接墊130上(且貼合至半導體裝置100)可能是有益的。
圖2D示出顯示根據一些示例性實施例的半導體裝置的鈍化層的放大剖視圖，所述放大剖視圖是沿著圖1B所示線II-III截取的且對應於圖1A所示區段I。以下將參照圖1A及圖1B以及圖2D，並且為了避免重複說明將進行省略。
參照圖2D，半導體裝置可包括基板110、電路層120、導電接墊130、第一鈍化層141、第二鈍化層142、有機介電層150 及凸塊結構160。第一鈍化層141及第二鈍化層142可類似於以上參照圖1A至圖1C論述的第一鈍化層141及第二鈍化層142。然而，在圖2D中所示的實施例中，第二鈍化層142可設置於第一鈍化層141的頂表面上且可覆蓋第一鈍化層141的內壁141c。第二鈍化層142可與導電接墊130的頂表面的一部分接觸。第一開口149可暴露出第二鈍化層142的內壁142c，但可不暴露出第一鈍化層141。
柱圖案161可設置於第一開口149及第二開口159中，且可與第二鈍化層142的內壁142c以及有機介電層150的內壁150c及頂表面150a接觸。隨著第二鈍化層142延伸至第一鈍化層141的內壁141c上，柱圖案161與第二鈍化層142之間可具有增大的接觸面積。因此，第二鈍化層142可有助於將柱圖案161穩定地固定至第一鈍化層141。舉例而言，第一鈍化層141及第二鈍化層142以及柱圖案161可分別由以下材料製成：所述材料使得第二鈍化層142與柱圖案161之間的黏合力可較第一鈍化層141與柱圖案161之間的黏合力強，且第一鈍化層141與第二鈍化層142之間的黏合力可較第一鈍化層141與柱圖案161之間的黏合力強。柱圖案161可與第一鈍化層141的內壁141c間隔開(例如，由於柱圖案161與第一鈍化層141的內壁141c之間插置有第二鈍化層142)。
在圖2C及圖2D的實施例中，基板110、電路層120、有機介電層150及凸塊結構160可與以上參照圖1A至圖1C論述 的基板110、電路層120、有機介電層150及凸塊結構160實質上相同。作為另一種選擇，凸塊結構160可與參照圖2A或圖2B論述的凸塊結構160實質上相同。
以下將闡述包括根據本發明概念的半導體裝置的半導體封裝。為了簡化，以下將省略重複說明。
圖3示出顯示根據一些示例性實施例的半導體封裝的剖視圖。
參照圖3，半導體封裝1可包括封裝基板900、半導體裝置100及模製層200。封裝基板900可具有彼此相對的頂表面與底表面。封裝基板900可包括介電基礎層910、基板接墊920及內部線930。介電基礎層910可包括單個層或多個層。基板接墊920可暴露於封裝基板900的頂表面上。內部線930可設置於介電基礎層910中且耦合至基板接墊920。示意性地示出介電基礎層910中的實線，以指示內部線930。在本說明中，當元件被闡述為電性連接至封裝基板900時，所述元件可電性連接至內部線930。此可類似地應用於其他元件。基板接墊920及內部線930可包含金屬，例如銅、鋁、鎢、及/或鈦。舉例而言，封裝基板900可為具有電路圖案的印刷電路板(PCB)。在某些實施例中，重佈線基板可用作封裝基板900。當重佈線基板被用作封裝基板900時，介電基礎層910可包含感光性聚合物。當重佈線基板被用作封裝基板900時，內部線930可包括晶種層及位於晶種層上的金屬層。舉例而言，晶種層可為有助於金屬成核以形成金屬層的層。
在封裝基板900的底表面上可設置有外部端子950，且外部端子950耦合至內部線930。外部電性訊號可藉由外部端子950傳輸至內部線930。外部端子950可包括焊料球。外部端子950可包含金屬(例如焊料材料(例如，錫、銅、銀、鉍、銦、鋅、銻、鉛等))或者可由所述金屬形成。
可將半導體裝置100安裝於封裝基板900上。可將半導體裝置100設置於封裝基板900上，以容許半導體裝置100的凸塊結構160面對封裝基板900。凸塊結構160可與基板接墊920對齊。凸塊結構160可與基板接墊920接觸。將半導體裝置100安裝於封裝基板900上可包括對凸塊結構160實行結合製程。結合製程可為焊接製程。舉例而言，焊接製程可包括對凸塊結構160實行退火製程。退火製程可在較焊料圖案165的熔點高的溫度下執行。在此步驟中，可進一步向凸塊結構160供應外力，例如壓力。由於柱圖案161與有機介電層150接觸，因此有機介電層150可減輕在結合製程中施加至柱圖案161的應力。因此，在焊接製程期間，可防止柱圖案161受到損壞/保護柱圖案161免受損壞。可在結合製程期間將焊料圖案165結合至基板接墊920，且因此可藉由凸塊結構160將半導體裝置100的積體電路電性連接至封裝基板900。
模製層200可設置於封裝基板900的頂表面上。模製層200可覆蓋半導體裝置100的頂表面及側壁(例如，側壁中的每一者)。在某些實施例中，模製層200可覆蓋半導體裝置100的側壁， 但可暴露出半導體裝置100的頂表面。模製層200可延伸至封裝基板900與半導體裝置100之間的間隙中，藉此包封凸塊結構160。作為另一種選擇，可在封裝基板900與半導體裝置100之間設置底部填充層(未示出)。模製層200可包含介電聚合物，例如環氧系模製化合物。
圖4A示出顯示根據一些示例性實施例的半導體封裝的剖視圖。圖4B示出顯示圖4A所示區段IV的放大視圖。為了簡化，以下將省略重複說明。
參照圖4A及圖4B，半導體封裝1A可包括封裝基板900、中介層基板800、及晶片堆疊1000。封裝基板900可與參照圖3A論述的封裝基板900實質上相同。在封裝基板900的底表面上可設置有多個外部端子950。
中介層基板800可設置於封裝基板900上。中介層基板800可包括金屬接墊820及金屬線830。金屬接墊820可暴露於中介層基板800的頂表面上。金屬線830可設置於中介層基板800中且耦合至金屬接墊820。在本說明中，當元件被闡述為電性連接至中介層基板800時，所述元件可電性連接至金屬線830。金屬接墊820及金屬線830可包含金屬，例如銅、鋁、鎢、及/或鈦。中介層凸塊850可插置於封裝基板900與中介層基板800之間且耦合至封裝基板900及中介層基板800。舉例而言，中介層凸塊850可耦合至基板接墊920及金屬線830。中介層凸塊850可為焊料球或另一種焊料結構(例如，焊料柱)。中介層凸塊850可包含金屬 (例如焊料材料(例如，錫、銅、銀、鉍、銦、鋅、銻、鉛等))或者可由所述金屬形成。
晶片堆疊1000可安裝於中介層基板800的頂表面上。晶片堆疊1000可包括第一半導體晶片300及多個半導體裝置100。第一半導體晶片300可安裝於中介層基板800的頂表面上。第一半導體晶片300可為邏輯晶片、緩衝晶片及系統晶片中的一者。舉例而言，第一半導體晶片300的積體電路(未示出)可包括邏輯電路，且第一半導體晶片300可用作邏輯晶片。舉例而言，邏輯晶片可為中央處理器(central processing unit，CPU)、圖形處理單元(graphic processing unit，GPU)、或另一處理器。第一半導體晶片300可包括基礎基板310、電路圖案330、導電貫通電極380及上部導電接墊370。基礎基板310可為半導體基板。電路圖案330中可具有積體電路。上部導電接墊370可設置於第一半導體晶片300的頂表面上。導電貫通電極380可設置於基礎基板310中且耦合至上部導電接墊370。第一結合凸塊350可插置於中介層基板800與第一半導體晶片300之間且電性連接至中介層基板800及第一半導體晶片300。在本說明中，片語「電性連接至半導體晶片」可意指「電性連接至半導體晶片的積體電路」。舉例而言，第一結合凸塊350可電性連接至第一半導體晶片300的積體電路。第一結合凸塊350可包括選自焊料球及柱中的至少一者。第一結合凸塊350可包含金屬(例如焊料材料(例如，錫、銅、銀、鉍、銦、鋅、銻、鉛等))或者可由所述金屬形成。多個第一結合凸塊 350可設置於中介層基板800與第一半導體晶片300之間，且第一結合凸塊350中的至少一者可電性連接至導電貫通電極380。
半導體裝置100可堆疊於第一半導體晶片300上。半導體裝置100可各自具有與第一半導體晶片300的類型不同的類型。舉例而言，半導體裝置100可為記憶體晶片。記憶體晶片可包括高頻寬記憶體(high bandwidth memory，HBM)晶片。半導體裝置100中的每一者可包括基板110、電路層120、導電接墊130、鈍化層140、有機介電層150及凸塊結構160。基板110、電路層120、導電接墊130、鈍化層140、有機介電層150及凸塊結構160可與參照圖1A至圖1C論述的基板110、電路層120、導電接墊130、鈍化層140、有機介電層150及凸塊結構160實質上相同。作為另一種選擇，凸塊結構160可與參照圖2A或圖2B論述的凸塊結構160實質上相同，及/或鈍化層140可與參照圖2C或圖2D論述的鈍化層140實質上相同。
半導體裝置100中的每一者可更包括貫通電極180及上部接墊170。上部接墊170可設置於半導體裝置100的頂表面上。貫通電極180可設置於基板110中。貫通電極180的頂端可耦合至上部接墊170。如圖4B中所示，貫通電極180的底端可藉由內連結構127耦合至選自導電接墊130及積體電路125中的至少一者。因此，上部接墊170可藉由貫通電極180耦合至選自導電接墊130及積體電路125中的至少一者。最上部半導體裝置100可既不包括貫通電極180亦不包括上部接墊170。
半導體裝置100可包括彼此相鄰的下部半導體裝置100與上部半導體裝置100。上部半導體裝置100可設置於下部半導體裝置100的頂表面上。上部半導體裝置100的凸塊結構160可耦合至下部半導體裝置100的上部接墊170。因此，多個半導體裝置100可電性連接至彼此。最下部半導體裝置100的凸塊結構160可耦合至第一半導體晶片300的上部導電接墊370。因此，半導體裝置100可電性連接至封裝基板900。
如圖4A中所示，半導體裝置100中的每一者可包括多個凸塊結構160，且可在所述多個凸塊結構160之間提供精細節距P1。舉例而言，插置於中介層基板800與封裝基板900之間的中介層凸塊850可具有如圖4A中所示的節距P2，且凸塊結構160的節距P1可小於中介層凸塊850的節距P2，且小於外部端子950的節距P3。特定組件的節距可為特定組件被重複設置的週期。
半導體封裝1A可更包括第二半導體晶片400。第二半導體晶片400可安裝於中介層基板800的頂表面上。第二半導體晶片400可與第一半導體晶片300在側向上間隔開。第二半導體晶片400可具有與第一半導體晶片300的類型及半導體裝置100的類型不同的類型。第二半導體晶片400可包括中央處理器(CPU)或圖形處理單元(GPU)。在第二半導體晶片400的晶片接墊430與形成於中介層基板800的頂表面上的多個金屬接墊820中的對應的金屬接墊820之間可設置有第二結合凸塊450，如圖4A中所示。第二結合凸塊450可包括選自焊料球及柱中的至少一者。第 二結合凸塊450可包含金屬(例如焊料材料(例如，錫、銅、銀、鉍、銦、鋅、銻、鉛等))或者可由所述金屬形成。多個第二結合凸塊450可設置於第二半導體晶片400與中介層基板800之間，且各個第二結合凸塊450可接觸形成於第二半導體晶片400的底表面上的對應的晶片接墊430且可接觸形成於中介層基板800的頂表面上的對應的金屬接墊820。所述多個第二結合凸塊450可具有較外部端子950的節距P3小的節距。第二半導體晶片400可藉由第二結合凸塊450及中介層基板800的金屬線830電性連接至第一半導體晶片300或半導體裝置100中的任一者。舉例而言，第二半導體晶片400可藉由第二結合凸塊450及金屬線830電性連接至第一半導體晶片300及/或半導體裝置100中的一或多者。
半導體封裝1A可更包括選自第一底部填充圖案710、第二底部填充圖案720及第三底部填充圖案730中的至少一者。第一底部填充圖案710可設置於中介層基板800與第一半導體晶片300之間的間隙中，且可包封第一結合凸塊350。第一底部填充圖案710可包含介電聚合物，例如環氧系聚合物。多個第二底部填充圖案720可設置於半導體裝置100之間的間隙中，且可包封對應的凸塊結構160。第二底部填充圖案720可包含介電聚合物，例如環氧系聚合物。第三底部填充圖案730可設置於中介層基板800與第二半導體晶片400之間的間隙中，且可包封第二結合凸塊450。第三底部填充圖案730可包含介電聚合物，例如環氧系聚合物。
半導體封裝1A可更包括模製層(未示出)。模製層可設置於中介層基板800的頂表面上，且可覆蓋晶片堆疊1000及第二半導體晶片400。
根據本發明概念，凸塊結構可與鈍化層及有機介電層實體接觸。由於凸塊結構與有機介電層接觸，因此有機介電層可減輕施加至凸塊結構的應力。由於凸塊結構與鈍化層接觸，因此凸塊結構可穩定地固定至電路層。因此，凸塊結構及包括所述凸塊結構的半導體裝置可具有增加的可靠性及耐久性。
儘管已參照示例性實施例闡述了本發明概念，然而對熟習此項技術者而言顯而易見的是，在不背離本發明概念的精神及範圍的條件下，可作出各種改變及修改。因此，應理解，以上實施例並非限制性的，而是為例示性的。因此，本發明的範圍將由以下申請專利範圍及其等效範圍所許可的最廣範圍的解釋來確定，而不應受上述說明約束或限制。
100:半導體裝置/最上部半導體裝置/下部半導體裝置/上部半導體裝置/最下部半導體裝置
110:基板
110a:第一表面/頂表面
110b:第二表面
120:電路層
130:導電接墊
140:鈍化層
149:第一開口
150:有機介電層
159:第二開口
160:凸塊結構
161:柱圖案
165:焊料圖案
I:區段

Claims (19)

  1. 一種半導體裝置，包括：半導體基板；導電接墊，位於所述半導體基板的第一表面上；鈍化層，位於所述半導體基板的所述第一表面上，所述鈍化層具有暴露出所述導電接墊的一部分的第一開口；有機介電層，位於所述鈍化層上，所述有機介電層具有第二開口；以及凸塊結構，位於所述導電接墊上且位於所述第一開口及所述第二開口中，其中所述有機介電層包含與所述鈍化層的材料不同的材料，其中所述第二開口在空間上連接至所述第一開口且暴露出所述鈍化層的一部分，其中所述凸塊結構包括與所述鈍化層及所述有機介電層接觸的柱圖案，且其中所述柱圖案包括晶種圖案及導電圖案，所述晶種圖案與所述鈍化層的頂表面及所述有機介電層的頂表面接觸，所述導電圖案與所述鈍化層及所述有機介電層間隔開。
  2. 如請求項1所述的半導體裝置，其中所述凸塊結構更包括位於所述柱圖案上的焊料圖案。
  3. 如請求項1所述的半導體裝置，其中所述柱圖案接觸所述導電接墊且延伸至所述有機介電層的所述頂表面上。
  4. 如請求項1所述的半導體裝置，其中所述柱圖案的寬度大於所述第二開口的寬度，且所述第二開口的所述寬度大於所述第一開口的寬度。
  5. 如請求項4所述的半導體裝置，其中所述柱圖案的所述寬度約20微米以上且約70微米以下，所述第二開口的所述寬度約10微米以上且小於約20微米，並且所述第一開口的所述寬度約5微米以上且小於約10微米。
  6. 如請求項1所述的半導體裝置，其中所述柱圖案的頂表面是平整的。
  7. 如請求項1所述的半導體裝置，其中所述導電圖案包括導電層，所述導電層包括：第一導電層，位於所述晶種圖案上；第二導電層，位於所述第一導電層上；以及第三導電層，位於所述第二導電層上。
  8. 如請求項7所述的半導體裝置，其中所述第一導電層的頂表面處於較所述有機介電層的所述頂表面的水平高的水平處。
  9. 如請求項7所述的半導體裝置，其中所述第三導電層包含與所述第一導電層的材料相同的材料，且所述第二導電層包含與所述第一導電層的所述材料及所述第 三導電層的所述材料不同的材料。
  10. 如請求項1所述的半導體裝置，其中所述鈍化層包括含矽層。
  11. 如請求項1所述的半導體裝置，其中所述鈍化層包括：第一鈍化層；以及第二鈍化層，位於所述第一鈍化層上且包含與所述第一鈍化層的材料不同的材料，其中所述第二鈍化層的內壁與所述第一鈍化層的內壁共面且與所述柱圖案接觸。
  12. 一種半導體裝置，包括：半導體基板；導電接墊，位於所述半導體基板的第一表面上；含矽層，位於所述半導體基板的所述第一表面上且暴露出所述導電接墊的一部分；聚合物層，位於所述含矽層上且暴露出所述含矽層的一部分及所述導電接墊的所述一部分；柱圖案，位於所述導電接墊上且與所述含矽層及所述聚合物層接觸；以及焊料圖案，位於所述柱圖案上，其中所述柱圖案包括晶種圖案及導電圖案，所述晶種圖案與所述導電接墊的頂表面、所述含矽層的頂表面及所述聚合物層的 頂表面接觸。
  13. 如請求項12所述的半導體裝置，其中所述聚合物層暴露出所述含矽層的頂表面。
  14. 如請求項12所述的半導體裝置，其中所述柱圖案與所述含矽層的內壁及所述聚合物層的內壁接觸，其中所述聚合物層的所述內壁不與所述含矽層的所述內壁對齊。
  15. 如請求項12所述的半導體裝置，其中所述晶種圖案覆蓋所述導電接墊的被暴露出的所述頂表面、所述含矽層的內壁及所述頂表面、以及所述聚合物層的內壁及所述頂表面。
  16. 如請求項12所述的半導體裝置，其中所述柱圖案與所述聚合物層之間的接觸面積大於所述柱圖案與所述含矽層之間的接觸面積。
  17. 如請求項12所述的半導體裝置，其中所述含矽層包含矽及氮，且所述聚合物層包含感光性聚醯亞胺。
  18. 一種半導體裝置，包括：半導體基板；電路層，位於所述半導體基板上；導電接墊，位於所述電路層上；含矽層，位於所述導電接墊上，所述含矽層具有第一開口； 聚合物層，位於所述含矽層上，所述聚合物層具有第二開口；以及凸塊結構，設置於所述導電接墊上，其中所述電路層包括：積體電路，位於所述半導體基板的第一表面上；介電層，位於所述半導體基板的所述第一表面上，所述介電層覆蓋所述積體電路；以及內連結構，位於所述介電層中，所述內連結構耦合至所述積體電路，所述內連結構包括配線圖案及通孔圖案，其中所述第一開口暴露出所述導電接墊的一部分及所述含矽層的內壁，其中所述第二開口在空間上連接至所述第一開口且暴露出所述含矽層的頂表面，並且其中所述凸塊結構包括：柱圖案，位於所述第一開口及所述第二開口中；以及焊料圖案，位於所述柱圖案上，其中所述柱圖案包括：晶種圖案，與所述導電接墊、所述含矽層的被暴露出的所述頂表面及所述聚合物層的內壁及頂表面接觸接觸；以及導電圖案，位於所述晶種圖案上。
  19. 如請求項18所述的半導體裝置，其中所述導電圖案包括： 第一導電部，位於所述晶種圖案上，所述第一導電部包含第一金屬；第二導電部，位於所述第一導電部上，所述第二導電部包含第二金屬；以及第三導電部，位於所述第二導電部上，所述第三導電部包含所述第一金屬，其中所述第二金屬不同於所述第一金屬。
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