CN110718528A - 半导体封装件 - Google Patents
半导体封装件 Download PDFInfo
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- CN110718528A CN110718528A CN201910585222.7A CN201910585222A CN110718528A CN 110718528 A CN110718528 A CN 110718528A CN 201910585222 A CN201910585222 A CN 201910585222A CN 110718528 A CN110718528 A CN 110718528A
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- pads
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Abstract
一种半导体封装件包括:基板;安装在基板上的半导体芯片;位于半导体芯片上且包括再分布图案的中介层芯片;位于中介层芯片上的第一焊盘;位于中介层芯片上并且与第一焊盘间隔开的第二焊盘;以及电连接到第二焊盘和基板的接合线。第二焊盘通过再分布图案电连接到第一焊盘。中介层芯片的占用面积大于第一半导体芯片的占用面积。
Description
优先权声明
本申请要求于2018年7月13日在韩国知识产权局提交的韩国专利申请No.10-2018-0081705的优先权,其全部内容通过引用结合于此。
技术领域
本发明构思涉及半导体封装件。更具体地,本发明构思涉及芯片堆叠封装件(例如,堆叠式封装件(PoP))以及可用于制造芯片堆叠封装件的半导体封装件。
背景技术
提供半导体封装件以提供用于电子产品的集成电路。半导体封装件通常配置为使得半导体芯片安装在印刷电路板(PCB)上,并且接合线或凸块用于将半导体芯片电连接到印刷电路板。随着电子工业的不断发展,已经进行了许多研究,旨在增加半导体封装件的功能并提高半导体封装件的可靠性和耐用性。
发明内容
根据本发明构思的一个方面,提供了一种半导体封装件,该半导体封装件包括:第一基板;第一半导体芯片,其设置并安装在第一基板上;中介层芯片,其位于第一半导体芯片上;第一焊盘,其设置在中介层芯片上;第二焊盘,其设置在中介层芯片上并与第一焊盘间隔开;以及接合线,其电连接到第二焊盘和第一基板,并且其中,第二焊盘通过中介层芯片电连接到第一焊盘,并且中介层芯片具有大于第一半导体芯片的占用面积的占用面积。
根据本发明构思的另一方面,还提供了一种半导体封装件,该半导体封装件包括:第一基板;第一半导体芯片,其设置并安装在第一基板上;虚设芯片,其设置在第一半导体芯片上并且具有大于第一半导体芯片的占用面积的占用面积;再分布层,其位于虚设芯片的顶表面上;多个焊球焊盘,其位于再分布层上;接合线焊盘,其连接到再分布层并通过再分布层电连接到焊球焊盘中的至少一个;以及模塑层,其设置在第一基板上并覆盖再分布层和接合线焊盘,并且其中,模塑层具有多个开口,这些多个开口通向焊球焊盘并在焊球焊盘处开口。
根据本发明构思的又一方面,提供了一种半导体封装件,该半导体封装件包括:第一基板,其包括基板焊盘;第一半导体芯片,其设置并安装在第一基板上;中介层芯片,其设置在第一半导体芯片上并包括再分布层,该再分布层包括布线图案;焊球,其位于中介层芯片的顶表面上;以及接合线,从中介层芯片的顶表面延伸,并且其中,接合线耦接到基板焊盘,焊球通过再分布层电连接到接合线,并且中介层芯片在与第一基板的上表面平行的方向上具有大于第一半导体芯片的宽度的宽度。
根据本发明构思的又一方面,提供了一种半导体封装件,该半导体封装件包括:第一基板,其包括绝缘体、以及在绝缘体的顶表面处的导电材料的第一基板焊盘和第二基板焊盘;第一半导体芯片,其依照设置在第一基板的第一基板焊盘上并与第一基板的第一基板焊盘电连接的方式倒装安装在第一基板上;中介层,其位于第一半导体芯片上,该中介层具有包括再分布层的上部,该再分布层包括布线图案;导电材料的多个第一焊盘,其设置在中介层上;导电材料的多个第二焊盘,其设置在中介层上并与多个第一焊盘横向向外隔开;接合线,其将设置在中介层上的第二焊盘分别与第二基板焊盘电连接;以及模塑层,其设置在第一基板上并且中介层、第一半导体芯片和接合线被封装在其中,并且其中,第二焊盘通过中介层的再分布层的布线图案电连接到第一焊盘,并且模塑层中具有多个开口,这些多个开口通向设置在中介层上的多个第一焊盘并在这些多个第一焊盘处开口。
附图说明
图1A是根据本发明构思的半导体封装件的第一示例的平面图。
图1B是沿图1A的线I-II截取的截面图。
图1C是图1B的部分III的放大视图。
图1D是根据本发明构思的半导体封装件的第一示例的一种形式的开口和第一焊盘的截面图。
图1E是根据本发明构思的半导体封装件的第一示例的另一种形式的开口和第一焊盘的截面图。
图1F是根据本发明构思的半导体封装件的第一示例的另一种形式的开口和第一焊盘的截面图。
图1G是根据本发明构思的半导体封装件的第一示例的另一种形式的开口和第一焊盘的截面图。
图1H是根据本发明构思的半导体封装件的第一示例的又一种形式的开口和第一焊盘的截面图。
图2A是根据本发明构思的半导体封装件的第二封装件的平面图。
图2B是沿图2A的线I'-II'截取的截面图。
图3A是根据本发明构思的半导体封装件的第二示例的平面图。
图3B是沿图3A的线I”-II”截取的截面图。
图3C是在根据本发明构思的半导体封装件的第二示例在其制造过程期间的截面图。
图3D是根据本发明构思的半导体封装件的第二示例的连接结构的截面图。
图3E是根据本发明构思的另一种形式的连接结构的截面图。
图3F是根据本发明构思的又一种形式的连接结构的截面图。
图4A是根据本发明构思的半导体封装件的第二封装件的示例的布局图。
图4B是具有图4A中所示布局的第二封装件的第二基板和第二半导体芯片之间的电连接的平面图。
图5A是根据本发明构思的具有图4A和图4B的第二封装件的半导体封装件的示例的布局图。
图5B是具有根据本发明构思的图4A和图4B的第二封装件和图5A所示的布局的半导体封装件的示例的沿与图5A的线I”-II”的方向对应的方向截取的截面图。
图6A是根据本发明构思的半导体封装件的第二封装件的另一示例的布局图。
图6B是具有图6A中所示布局的第二封装件的第二基板和第二半导体芯片之间的电连接的平面图。
图7是根据本发明构思的半导体封装件的第一封装件的另一示例的布局图。
图8是根据本发明构思的半导体封装件的第二封装件的另一示例的布局图。
图9A是根据本发明构思的半导体封装件的另一示例的布局图。
图9B是沿与图9A的线I”-II”的方向对应的方向截取的并且具有图9A中所示的布局的半导体封装件的示例的截面图。
图10A是根据本发明构思的半导体封装件的另一示例的布局图。
图10B是沿与图10A的线I”-II”的方向对应的方向截取的并且具有图10A中所示的布局的半导体封装件的示例的截面图。
图11是根据本发明构思的半导体封装件的又一示例的截面图。
具体实施方式
现在将参考附图详细描述根据本发明构思的半导体封装件的各种示例。在整个附图中,相同的附图标记表示相同的组件。而且,为了简单起见,描述可以将封装件称为具有单数的特定元件或特征。然而,如附图中所示,封装件的示例可以具有多个类似的元件或特征,书面描述同样适用于这些元件或特征。而且,除非另有说明,否则为了简洁起见,可不再详细描述结合一个示例描述的并且与后续示例中的那些特征或方面类似(如从附图中清楚看出的那样)的本发明构思的特征和方面。
在图1A、图1B和图1C中示出了根据本发明构思的半导体封装件的第一示例。该半导体封装件(下文中又称作第一封装件10)可以包括第一基板100、第一半导体芯片200、芯片形式的中介层300(下文中称为“中介层芯片300”)、接合线520和模制材料体390(下文中称为“第一模塑层390”)。印刷电路板或具有再分布布线的结构可以用作第一基板100。第一基板100可以具有在其顶表面上设置有基板焊盘的绝缘体(一层或多层绝缘材料)。基板焊盘可以包括第一基板焊盘121和第二基板焊盘122。第二基板焊盘122可以比第一基板焊盘121更靠近第一基板100的边缘区域。第一基板焊盘121和第二基板焊盘122可以通过内部互连线130(由实线示意性地示出)电连接到外部端子110。如下文所使用的短语“电连接到第一基板100”可表示“电连接到内部互连线130”。外部端子110可以设置在第一基板100的绝缘体的底表面上。外部端子110可以包括焊球。外部端子110可以耦接到外部设备。基板焊盘121和122、外部端子110和内部互连线130由诸如金属的导电材料形成。
第一半导体芯片200可以倒装芯片式地安装在第一基板100上。第一半导体芯片200可以是逻辑芯片或应用处理器(AP)。第一半导体芯片200可以是片上系统。第一半导体芯片200可以在其中具有集成电路,该集成电路可以包括逻辑电路、存储电路或者它们的组合。第一芯片焊盘210可以设置在第一半导体芯片200的底部,即,在第一半导体芯片200的面对第一基板100的表面处。第一芯片焊盘210可以电连接到第一半导体芯片200的集成电路。因此,第一半导体芯片200的底表面可以是芯片的有源表面。第一半导体芯片200的顶表面200a可以是非有源表面。因此,短语“电连接到第一焊盘410”可以具有与“电连接到第一半导体芯片200”本质上相同的含义。同样,因此,短语“电连接到第一半导体芯片200”可以具有与“电连接到第一半导体芯片200的集成电路”本质上相同的含义。
连接端子220可以设置在第一基板100和第一半导体芯片200之间,并且可以电连接到第一基板100和第一半导体芯片200。连接端子220可以包括焊球、凸块和柱中的一个或多个。连接端子220由诸如金属的导电材料制成。底填充层290可以设置在第一基板100和第一半导体芯片200之间的间隙中,并且可以封装连接端子220。底填充层290可以包括介电聚合物。
在根据本发明构思的半导体封装件的另一示例中,可以使用热压接合技术将第一半导体芯片200安装在第一基板100上。在这种情况下,第一半导体芯片200在物理上接触第一基板100,并且第一芯片焊盘210直接耦接到第一基板焊盘121。
中介层芯片300设置在第一半导体芯片200上。中介层芯片300可以包括基底基板310和再分布层330。中介层芯片300不包括集成电路或晶体管。基底基板310可以是虚设芯片。半导体基板可以用作基底基板310。该半导体基板可以是由硅、硅锗或碳化硅构成的基板(板状体)。基底基板310具有面向相反方向的顶表面和底表面。基底基板310的底表面面对第一半导体芯片200。包括基底基板310的中介层芯片300可以具有相对高的导热率。中介层芯片300可以具有大于印刷电路板的导热率的导热率。例如,中介层芯片300可以具有等于或大于约30W/mK的导热率,并且优选地,中介层芯片300的导热率为约30W/mK至约2000W/mK。第一半导体芯片200可在其操作期间产生热。如箭头所示,可以通过中介层芯片300迅速释放从第一半导体芯片200产生的热。因此,第一半导体芯片200可以具有卓越的热特性和操作可靠性。
第一半导体芯片200的性能越高,第一半导体芯片200产生的热量越大。根据其中中介层芯片300具有如上所述的热释放功能的本发明构思的示例,高性能半导体芯片可以用作第一半导体芯片200。
如图1A所示,中介层芯片300可以具有等于或大于第一半导体芯片200的长度L1的长度L2。中介层芯片300的宽度W2可以等于或大于第一半导体芯片200的宽度W1。在这种情况下,中介层芯片300完全覆盖第一半导体芯片200的顶表面200a。而且,中介层芯片300可以具有大于第一半导体芯片200的平面面积的平面面积,使得中介层芯片300的边缘区域不位于第一半导体芯片200上。由于第一半导体芯片200的顶表面200a完全覆盖中介层芯片300或与中介层芯片300重叠,所以从第一半导体芯片200产生的热可以快速地传递到中介层芯片300。中介层芯片300可以相对较薄,因此第一封装件10可以相对紧凑。
可以在第一半导体芯片200和中介层芯片300之间设置粘合层380。中介层芯片300可以通过粘合层380附接到第一半导体芯片200。粘合层380可以延伸到中介层芯片300的边缘区域的底表面上。粘合层380可以包括介电聚合物和多个颗粒。颗粒可以分布在介电聚合物中。颗粒可以包括导热材料。例如,颗粒可以具有大于粘合层380的导热率的导热率。颗粒可以包括金属,但是本发明构思不限于此。颗粒可以使粘合层380具有相对高的导热率。例如,粘合层380可以具有等于或大于约0.2W/mK的导热率,并且优选地,粘合层380的导热率为约0.2W/mK至约10W/mK。从第一半导体芯片200产生的热可以立即通过粘合层380传递到中介层芯片300。
再分布层330设置在基底基板310的顶表面上。再分布层330可以包括一层或多层介电材料的介电部分(例如,至少一个介电层331)和再分布图案333。介电层331可以由介电聚合物或含硅介电材料形成。介电聚合物可以是例如光敏聚酰亚胺(PSPI)、聚苯并恶唑(PBO)、酚类聚合物、苯并环丁烯(BCB)基聚合物、或者它们的组合。含硅介电材料可以是氧化硅、氮化硅、氮氧化硅、原硅酸四乙酯(TEOS)、或者它们的组合。
再分布图案333可以包括过孔部分(一个或多个过孔)和线部分(导电线或“迹线”)。再分布图案333的过孔部分在介电层331之一中竖直延伸。再分布图案333的线部分可以设置在介电层331之一的表面上。再分布图案333的线部分连接至再分布图案333的过孔部分。短语“电连接到再分布层330”可以具有与“电连接到再分布图案333”本质上相同的含义。再分布图案333可以由诸如铜的金属形成。再分布图案333可以包括多个离散线部分和与离散线部分接触的相应一个(或一些)过孔。
中介层芯片300可以设置有位于介电层331的最上面的一个上的第一焊盘410和第二焊盘420。如图1A所示,第一焊盘410可以以第一间距P1布置。第一间距P1可以大于第二基板焊盘122的间距P2。第一焊盘410包括金属,例如铝。
第一焊球511可以分别设置在第一焊盘410上。第一半导体芯片200可以通过第一焊球511电连接到外部半导体芯片或外部封装件。第一焊球511包括导电材料,例如锡、银、铋、或者它们的任何合金。第一焊球511可以以与第一间距P1类似的间距布置。在另一示例中,省略了第一焊球511。
第二焊盘420可以比第一焊盘410更靠近中介层芯片300的侧表面。第二焊盘420可以通过再分布图案333电连接到第一焊盘410中的至少一个。可以执行单次工艺以与第一焊盘410一起形成第二焊盘420。例如,可以在再分布层330上形成导电层。可以图案化导电层以形成第一焊盘410和第二焊盘420。在这种情况下,第二焊盘420可以包括与第一焊盘410的材料相同的材料,并且可以具有与第一焊盘410的厚度大体相同的厚度。因此,第二焊盘420可以由例如铝形成。可替换地,第二焊盘420可以与第一焊盘410分开形成。在这种情况下,第二焊盘420可以包括与第一焊盘410的材料不同的材料。例如,第二焊盘420可以由镍、铜、铝、焊料、或者它们的任何合金形成。焊料可以包括锡、银、铋、或者它们的任何合金。
在其中中介层芯片300的平面面积大于第一半导体芯片200的平面面积的本发明构思的示例中,第一焊盘410和第二焊盘420的布局享有高自由度。
接合线520可以耦接到第二焊盘420和第二基板焊盘122中的一个。因此,第二焊盘420可以通过接合线520电连接到内部互连线130。因为在这样的示例中中介层芯片300的平面面积大于第一半导体芯片200的平面面积,所以接合线520可以与第一半导体芯片200相隔相对远的距离。因此,接合线520可以容易地电连接到第一基板100。接合线520可以由诸如金或铜的金属形成。
第一模塑层390可以设置在第一基板100和中介层芯片300上。第一模塑层390可以覆盖并保护接合线520和第二焊盘420。因此,第二焊盘420可以不被外来物质(例如,湿气或空气)损坏。第一模塑层390可以具有开口395。可以执行钻孔工艺以形成开口395。如图1C所示,开口395可以分别暴露第一焊盘410的顶表面。然而,第一焊盘410的侧表面可以由第一模塑层390覆盖。在形成开口395之后,第一焊球511可以相应地形成在由开口395暴露的第一焊盘410上。此时,开口395仍然可以视为通向第一焊盘410并且在第一焊盘410(的顶表面)处开口。第一焊球511的最上表面的水平高度可以高于第一模塑层390的最上表面的水平高度。
第一模塑层390可以覆盖并保护再分布层330。例如,第一模塑层390可以防止再分布图案333由外来物质造成的损坏(例如,腐蚀)。第一模塑层390可以填充第一基板100的顶表面和中介层芯片300的边缘区域的底表面之间的间隙。第一模塑层390可以由诸如环氧塑封料(EMC)的介电聚合物形成。
图1D至图1H示出了根据本发明构思的开口和第一焊盘的其他形式,每个都对应于图1B的部分III的放大视图。
参考图1D,开口395可以完全暴露第一焊盘410的顶表面。开口395还可以暴露第一焊盘410的侧表面。第一焊球511可以设置在第一焊盘410的暴露的顶表面上。第一焊球511可以与限定开口395的侧面的第一模塑层390的表面间隔开。
参考图1E,开口395可以暴露第一焊盘410的顶表面的一部分。开口395可以覆盖第一焊盘410的顶表面的另一部分和第一焊盘410的侧表面。第一焊球511可以设置在第一焊盘410的顶表面上并且可以填充开口395。因此,第一焊球511可以接触限定开口395的侧面的第一模塑层390的表面。
参考图1F和图1G,开口395可以暴露第一焊盘410的一部分。第一焊球511可以设置在第一焊盘410的顶表面上。第一模塑层390可以接触第一焊球511的一部分和第一焊盘410的侧表面。在图1F所示的示例中,第一焊球511的最上表面位于比第一模塑层390的最上表面的水平高的水平处。在图1G所示的示例中,第一焊球511的最上表面位于比第一模塑层390的最上表面的水平高度低的水平高度处。在另一个示例中,第一焊球511的最上表面位于与第一模塑层390的最上表面相同的水平处。
参考图1H,开口395暴露第一焊盘410的顶表面。在第一焊盘410的顶表面上没有设置焊球。
图2A和图2B示出了根据本发明构思的可以构成堆叠式封装件(PoP)的第二封装件。
参考图2A和图2B,第二封装件20可以包括第二基板600、第二半导体芯片700和第二模塑层800。印刷电路板或再分布层结构可以用作第二基板600。上焊盘620可以设置在第二基板600的顶表面上。上焊盘620可以由诸如铜、铝或镍的金属形成。
第二半导体芯片700可以安装在第二基板600上。第二半导体芯片700可以是存储器芯片。第二半导体芯片700可以设置在第二基板600的中心区域上。粘合膜780可以插入在第二基板600和第二半导体芯片700之间。粘合膜780可以包括介电树脂。第二芯片焊盘710可以设置在第二半导体芯片700的顶表面上,并且可以电连接到第二半导体芯片700的集成电路。短语“电连接到第二半导体芯片700”可以具有与“电连接到第二半导体芯片700的集成电路”本质上相同的含义。短语“电连接到第二芯片焊盘710”可以具有与“电连接到第二半导体芯片700”本质上相同的含义。
一个或多个连接件720可以从靠近第二半导体芯片700的顶表面的位置延伸。连接件720可以耦接到第二芯片焊盘710和上焊盘620。连接件720可以是接合线。连接件720由诸如金属的导电材料制成。第二半导体芯片700可以通过连接件720电连接到第二基板600。短语“电连接到第二基板600”可以具有与“电连接到第二基板600中的内部线630”本质上相同的含义。
第二模塑层800可以设置在第二基板600上以覆盖第二半导体芯片700。第二模塑层800可以封装连接件720。第二模塑层800可以由诸如环氧塑封料的介电聚合物形成。
上焊盘620可以与第二半导体芯片700横向间隔开。当在平面图中观察时,上焊盘620可以设置在第二基板600的边缘区域上。第二基板600的绝缘体可以设置在第二基板600的具有下焊盘610的底表面上。下焊盘610可以通过第二基板600的内部线630分别电连接到上焊盘620。在图2B中,实线示意性地示出了内部线630。内部线630和下焊盘610包括金属。如图2A所示,下焊盘610可以以第二间距P10布置。第二间距P10和下焊盘610的尺寸可以是标准化的。例如,第二间距P10可以符合JEDEC标准。第二间距P10可以大于上焊盘620的间距P20。每个下焊盘610的尺寸(表面积或占用面积)可以大于每个上焊盘620的尺寸。下焊盘610可以不与上焊盘620对准。
第二焊球512可以分别设置在下焊盘610上,并且可以分别耦接到下焊盘610。第二焊球512包括导电材料,例如锡、银、铋、或者它们的任何合金。第二焊球512可以以与第二间距P10相同或相似的间距布置。
图3A至图3C示出了根据本发明构思的半导体封装件的示例,在这种情况下是堆叠式封装件。
参考图2A、图3A和图3B,半导体封装件PKG1包括第一封装件10和第二封装件20。第一封装件10可以与上面参考图1A和图1B讨论的第一封装件10相同。第二封装件20可以与上面参考图2A和图2B讨论的第二封装件20相同。第二封装件20设置在第一封装件10上。第二封装件20可以通过一个或多个连接结构510电连接到第一封装件10。
参考图3C,第二封装件20可以设置在第一封装件10上,其中第二焊球512与相应的第一焊球511对准。之后,可以执行回流工艺。可以执行回流工艺以热处理第一焊球511和第二焊球512。当执行回流工艺时,可以将彼此对应的第一焊球511和第二焊球512焊接以形成图3B的连接结构510。下面将参考图3D至图3F描述连接结构510的示例。
在图3D和图3E的示例中,连接结构510接触限定开口395的侧面的第一模塑层390的表面。连接结构510可以包括彼此连接并且因此彼此成一体的上部512A和下部511A。连接结构510的上部512A可以源自图3C的第二焊球512中的一个。如图3D所示,连接结构510可以在第一焊盘410的顶表面上具有宽度,该宽度可以大于连接结构510的最小宽度。在这种情况下,连接结构510的下部511A源自图1F或图1G的第一焊球511。如图3E所示,连接结构510可以在第一焊盘410的顶表面上具有宽度,该宽度可以对应于连接结构510的最小宽度。在这种情况下,连接结构510的下部511A源自图1C或图1E所示的第一焊球511。可替换地,连接结构510的形成过程可以包括将图3C中所示的第二焊球512中的一个耦接到图1H中所示的第一焊盘410。
在图3F的示例中,连接结构510与第一模塑层390间隔开,即,连接结构510不接触限定开口395的侧面的第一模塑层390的表面。连接结构510的下部511A可以源自图1D中所示的第一焊球511。连接结构510的上部512A可以源自图3C中所示的第二焊球512中的一个。连接结构510的上部512A连接到连接结构510的下部511A并且因此与连接结构510的下部511A成一体。
返回参考图2A、图3A、图3B和图3C,每个连接结构510可包括焊球、凸块和柱中的一个或多个。当在平面图中观察时,如图3A所示,第一焊盘410和相应的一个下焊盘610中的每一个与相应的连接结构510重叠。连接结构510可以以与第一焊盘410的第一间距P1和下焊盘610的第二间距P10大体相同的间距布置。中介层芯片300可以用作第二半导体芯片700和第一半导体芯片200之间的电接口路由或第二半导体芯片700和外部端子110之间的电接口路由。第二半导体芯片700可以通过连接结构510、第一焊盘410、再分布图案333、第二焊盘420和接合线520电连接到第一半导体芯片200或电连接到外部端子110。
如果未设置第一焊盘410、中介层芯片300和接合线520,则连接结构510将必须直接耦接到第二基板焊盘122和相应的下焊盘610。在这种情况下,在第一基板100的边缘区域上,第二基板焊盘122将与第一半导体芯片200间隔开。因此,第二间距P10将相对较大。例如,在具有图1A的布局的本发明构思的示例中,第二间距P10将大于第二基板焊盘122的间距P2。因此,难以将连接结构510直接耦接到第二基板焊盘122和下焊盘610。相反,在根据本发明构思的示例中,设置了中介层芯片300、第一焊盘410、第二焊盘420和接合线520;因此,在第一焊盘410和连接结构510的布置中存在很大的设计自由度。特别地,第一焊盘410可以与下焊盘610对准。第一焊盘410的第一间距P1可以与第二间距P10大体相同。因此,连接结构510可以容易地连接到第一焊盘410和下焊盘610。
某些应用可能要求第二半导体芯片700是高性能芯片。第二半导体芯片700可以包括多个第二芯片焊盘710。第二半导体芯片700的存储容量和/或存储速度越高,第二芯片焊盘710的数量越大。因此,根据本发明构思的PoP的示例可具有相对大数量的连接件720、相对大数量的上焊盘620和相对大数量的下焊盘610。第二间距P10的标准化可增加下焊盘610的数量,因此可进一步分布下焊盘610。因为设置了中介层芯片300,所以第一焊盘410和连接结构510可以容易地设置在与下焊盘610的位置对应的位置处。因此,即便第二半导体芯片700是高性能芯片,也可以通过连接结构510、第一焊盘410和再分布图案333容易地将第二半导体芯片700电连接到第一半导体芯片200或外部端子110。
在一些示例中,中介层芯片300的形状在水平面上的投影的面积(即中介层芯片300的投影面积或“占用面积”)相对较大。这种投影面积在下文中可称为“平面面积”。中介层芯片300的平面面积越大,布置第一焊盘410的自由度就越大。因此可以更自由地设计连接结构510的布置。例如,第一焊盘410和连接结构510中的相应的第一焊盘410和连接结构510可以与第一半导体芯片200竖直并置。换句话说,在平面图中,一些第一焊盘410及其相关的连接结构510可以位于由第一半导体芯片200界定的区域内。其他的第一焊盘410和连接结构510可以不与第一半导体芯片200竖直并置。因此,在平面图中,第一焊盘410中的其他焊盘及其相关的连接结构510位于由第一半导体芯片200界定的区域之外。
可以在第一封装件10和第二封装件20之间设置间隙。例如,第一模塑层390可以与第二基板600间隔开,并且可以在第一模塑层390的顶表面和第二基板600的底表面之间设置间隙。间隙可以被诸如空气的气体占据并且在空间上与半导体封装件PKG1外部的环境连通。
图4A至图5B中示出了根据本发明构思的另一示例的半导体封装件PKG2,即第二PoP。
参考图4A、图4B、图5A和图5B,半导体封装件PKG2包括第一封装件10和第二封装件20'。第一封装件10可以与上面参考图1A和图1B讨论的第一封装件10相同。
第二封装件20'可以包括第二基板600、第二半导体芯片700和第二模塑层800。可以设置多个第二半导体芯片700。每个第二半导体芯片700可以具有面向相反方向的第一侧表面700c和第二侧表面700d。如图4A和图4B所示,每个第二半导体芯片700的第一侧表面700c可以面对第二半导体芯片700中的另一个。每个第二半导体芯片700的第二侧表面700d可以不面对任何其他第二半导体芯片700。第二半导体芯片700的第二侧表面700d可以比第二半导体芯片700的第一侧表面700c更靠近第二基板600的边缘区域。第二芯片焊盘710可以设置在第二半导体芯片700的顶表面上。如图4B所示,第二芯片焊盘710可以与第二半导体芯片700的第二侧表面700d相邻。如图4B和图5B所示,连接件720可以耦接到第二芯片焊盘710和上焊盘620。上焊盘620可以与第二半导体芯片700横向间隔开。上焊盘620可以与连接到该上焊盘620的第二半导体芯片700的第二侧表面700d相邻。如图4A所示,上焊盘620可以通过内部线630耦接到下焊盘610。可以设置大量下焊盘610以考虑提供多个第二半导体芯片700。第二间距P10可以是标准化的。第二间距P10可以大于上焊盘620的间距P20。
因为设置了中介层芯片300,所以连接结构510可以以高自由度布置。如图5A所示,第一焊盘410可以容易地与下焊盘610对准。因此,连接结构510可以连接到相应的第一焊盘410和相应的下焊盘610。每个第二半导体芯片700可以通过连接结构510、第一焊盘410、再分布图案333和接合线520电连接到第一半导体芯片200或外部端子110。
以下将描述第二半导体芯片700之间的电连接的示例。
第二半导体芯片700可以包括第一子半导体芯片701和第二子半导体芯片702。各个第一子半导体芯片701不是彼此相邻地并排设置的。如图4A所示,还可以在第二基板600的顶表面上设置第一芯片连接焊盘641。第一芯片连接焊盘641可以通过内部线630彼此电连接。第一芯片连接焊盘641可与下焊盘610电分离。如图4B所示,连接件720可以耦接到第二芯片焊盘710和第一芯片连接焊盘641。第一子半导体芯片701可以通过第一芯片连接焊盘641彼此电连接。因此,尽管第一子半导体芯片701在物理上彼此分离,但是各个第一子半导体芯片701可以执行由特定标准定义的单个半导体芯片的功能。特定标准可以是JEDEC标准。
各个第二子半导体芯片702不是彼此相邻地并排设置的。还可以在第二基板600的顶表面上设置第二芯片连接焊盘642。如图4B所示,第二子半导体芯片702可以通过连接件720耦接到第二芯片连接焊盘642。如图4A所示,第二芯片连接焊盘642可以通过内部线630彼此电连接。因此,第二子半导体芯片702可以彼此电连接。虽然第二子半导体芯片702在物理上彼此分离,但是各个第二子半导体芯片702可以执行由特定标准(例如,JEDEC标准)定义的单个半导体芯片的功能。第二芯片连接焊盘642可以与下焊盘610和第一芯片连接焊盘641电分离。
在另一示例中,第一芯片连接焊盘641连接到第二芯片连接焊盘642,因此第一子半导体芯片701和第二子半导体芯片702可以执行单个半导体芯片的功能。在又一示例中,省略了第一芯片连接焊盘641,并且每个第一子半导体芯片701可以用作单个半导体芯片。在又一示例中,省略了第二芯片连接焊盘642,并且每个第二子半导体芯片702可以用作单个半导体芯片。
图6A和图6B示出了根据本发明构思的半导体封装件PKG2的第二封装件的另一种形式。
半导体封装件PKG2具有第二封装件20”,该第二封装件20”包括第二基板600、第二半导体芯片700和第二模塑层800。第二半导体芯片700可以与上面参考图4A、图4B、图5A和图5B描述的那些第二半导体芯片700大体相同,除了在每个第二半导体芯片700的顶表面处第二芯片焊盘710与第一侧表面700c相邻之外。一个或多个上焊盘620可以设置在第二基板600的中心区域上。第一芯片连接焊盘641和第二芯片连接焊盘642可以设置在第二基板600的顶表面上。
上焊盘620和第二芯片焊盘710的平面布置不限于图4A至图6B中所示的那些。例如,第二芯片焊盘710可以包括与第二半导体芯片700的第一侧表面700c相邻的第一子芯片焊盘和与第二半导体芯片700的第二侧表面700d相邻的第二子芯片焊盘。在另一示例中,第二芯片焊盘710包括与第二半导体芯片700的第三侧表面相邻的第三子芯片焊盘。第二半导体芯片700的第三侧表面邻接第一侧表面700c和第二侧表面700d。
图7至图9B中示出了根据本发明构思的另一示例的半导体封装件PKG3。
半导体封装件PKG3包括第一封装件10'和第二封装件20”'。第一封装件10'可以与上面参考图1A至图1C描述的那些第一封装件大体相同,除了以下内容之外:如图7所示,当在平面图中观察时,第一焊盘410中的一个或多个位于第一基板100的中心区域上。每个第一焊盘410可以通过再分布图案333、第二焊盘420和接合线520电连接到第二基板焊盘122中的一个。第一间距P1可以大于第二基板焊盘122的间距P2。
如图8和图9B所示,上焊盘620与第二半导体芯片700间隔开。当在平面图中观察时,上焊盘620可以设置在第二基板600的边缘区域旁边。上焊盘620可以通过内部线630电连接到下焊盘610。下焊盘610不仅可以设置在第二基板600的中心区域上,而且可以设置在第二基板600的边缘区域上。如图8所示,第二间距P10可以大于上焊盘620的间距P20。
如图9A和图9B所示,连接结构510可以分别设置在第一焊盘410和下焊盘610之间。连接结构510可以以与第一间距P1和第二间距P10大体相同的间距布置。连接结构510可以耦接到相应的第一焊盘410和相应的下焊盘610。
图10A和图10B中示出了根据本发明构思的另一示例的半导体封装件PKG4。
半导体封装件PKG4包括第一封装件10”和第二封装件20”'。第一封装件10”可以与上面参考图1A至图1C描述的那些第一封装件大体相同,除了当在平面图中观察时第一焊盘410不位于第一半导体芯片200上之外。第二封装件20”'可以与上面参考图8和图9B描述的那些第二封装件大体相同。例如,下焊盘610可以设置在第二基板600的边缘区域上。下焊盘610的第二间距P10可以大于上焊盘620的间距P20。连接结构510可以耦接到相应的第一焊盘410和相应的下焊盘610。如图10A所示,当在平面图中观察时,连接结构510可以位于下焊盘610和第一焊盘410上。当在平面图中观察时,连接结构510不位于第一半导体芯片200上。
图11示出了根据本发明构思的示例的半导体封装件PKG5。
半导体封装件PKG5包括第一封装件10和第二半导体芯片700。第一封装件10可以与上面参考图1A至图1C描述的那些第一封装件大体相同。第二半导体芯片700的底表面可以是有源表面。因此,第二芯片焊盘710可以设置在第二半导体芯片700的底表面处。连接结构510可以设置在第一焊盘410和第二芯片焊盘710之间,并且可以耦接到第一焊盘410和第二芯片焊盘710。
作为根据本发明构思的半导体封装件PKG5的另一种形式,第二半导体芯片700安装在参考图6A和图6B描述的第二封装件20”上。
根据本发明构思,中介层芯片可以具有这样的高导热率,其使得从第一半导体芯片产生的热可以通过中介层芯片迅速释放。因此,第一半导体芯片可以具有卓越的操作可靠性。
因为设置了中介层芯片,所以可以以高自由度布置第一焊盘和连接结构。因此,第一焊盘和连接结构可以容易地与下焊盘对准。连接结构可以毫不费力地耦接到第一焊盘和下焊盘。
最后,上面已经详细描述了本发明构思的示例。然而,本发明构思可以以许多不同方式付诸实践,并且不应被解释为限于上述示例。相反,描述了这些示例,使得本公开彻底和完整,并且将本发明构思完全传达给本领域技术人员。因此,本发明构思的真实精神和范围不受上述实施例的限制,而是受随附权利要求的限制。
Claims (25)
1.一种半导体封装件,包括:
第一基板;
第一半导体芯片,其设置并安装在所述第一基板上;
中介层芯片,其位于所述第一半导体芯片上;
第一焊盘,其设置在所述中介层芯片上;
第二焊盘,其设置在所述中介层芯片上并与所述第一焊盘间隔开;以及
接合线,其电连接到所述第二焊盘和所述第一基板,
其中,所述第二焊盘通过所述中介层芯片电连接到所述第一焊盘,并且
所述中介层芯片具有大于所述第一半导体芯片的占用面积的占用面积。
2.根据权利要求1所述的半导体封装件,其中,所述中介层芯片具有在30 W/mK至2000W/mK的范围内的导热率。
3.根据权利要求1所述的半导体封装件,还包括:焊球,其位于所述第一焊盘上。
4.根据权利要求1所述的半导体封装件,其中,所述中介层芯片完全覆盖所述第一半导体芯片的顶表面。
5.根据权利要求1所述的半导体封装件,还包括:基板焊盘,其位于所述第一基板上并且耦接到所述接合线,
其中,所述半导体封装件包括邻近所述半导体封装件的一侧的多个所述第一焊盘,并且包括邻近所述半导体封装件的所述一侧的多个所述基板焊盘,所述多个第一焊盘具有第一间距,所述多个第一焊盘在与所述半导体封装件的所述一侧平行的方向上以所述第一间距彼此隔开,所述多个基板焊盘具有第二间距,所述多个基板焊盘在与所述半导体封装件的所述一侧平行的方向上以所述第二间距彼此隔开,并且所述第一间距大于所述第二间距。
6.根据权利要求1所述的半导体封装件,还包括:模塑层,其位于所述第一基板和所述中介层芯片上,
其中,所述模塑层覆盖所述第二焊盘但不覆盖所述第一焊盘。
7.根据权利要求1所述的半导体封装件,还包括:
上封装件,其位于所述中介层芯片上;和
连接结构,其介于所述上封装件和所述第一焊盘之间并且将所述上封装件和所述第一焊盘电连接。
8.根据权利要求7所述的半导体封装件,其中,所述上封装件包括:
第二基板;
第二半导体芯片,其设置并安装在所述第二基板上;
多个上焊盘,其位于所述第二基板的顶表面上,所述多个上焊盘电连接到所述第二半导体芯片;以及
多个下焊盘,其位于所述第二基板的底表面上并且电连接到所述多个上焊盘,
其中,所述多个下焊盘的间距大于所述多个上焊盘的间距。
9.根据权利要求8所述的半导体封装件,其中,所述第二半导体芯片是存储器芯片,并且所述半导体封装件包括设置并安装在所述第二基板上的至少一个其他存储器芯片。
10.根据权利要求1所述的半导体封装件,其中,当在平面图中观察时,所述第一焊盘位于由所述第一半导体芯片界定的区域内。
11.一种半导体封装件,包括:
第一基板;
第一半导体芯片,其设置并安装在所述第一基板上;
虚设芯片,其设置在所述第一半导体芯片上并具有大于所述第一半导体芯片的占用面积的占用面积;
再分布层,其位于所述虚设芯片的顶表面上;
多个焊球焊盘,其位于所述再分布层上;
接合线焊盘,其连接到所述再分布层并通过所述再分布层电连接到所述多个焊球焊盘中的至少一个;以及
模塑层,其设置在所述第一基板上并覆盖所述再分布层和所述接合线焊盘,
其中,所述模塑层具有多个开口,所述多个开口通向所述多个焊球焊盘并在所述多个焊球焊盘处开口。
12.根据权利要求11所述的半导体封装件,其中
当在平面图中观察时,所述多个焊球焊盘中的至少一个位于由所述第一半导体芯片界定的区域内,并且所述多个焊球焊盘中的另一个与由所述第一半导体芯片界定的所述区域间隔开。
13.根据权利要求11所述的半导体封装件,还包括:
多个基板焊盘,其位于所述第一基板的顶表面上;以及
接合线,其耦接到所述接合线焊盘和所述多个基板焊盘之一,
其中,所述多个焊球焊盘的间距大于所述多个基板焊盘的间距。
14.根据权利要求11所述的半导体封装件,还包括:
上封装件;以及
多个连接结构,其介于所述上封装件和所述多个焊球焊盘之间,
其中,所述上封装件通过所述连接结构电连接到所述再分布层。
15.根据权利要求14所述的半导体封装件,其中,所述模塑层和所述上封装件之间具有间隙。
16.一种半导体封装件,包括:
第一基板,其包括基板焊盘;
第一半导体芯片,其设置并安装在所述第一基板上;
中介层芯片,其设置在所述第一半导体芯片上并且包括包含布线图案的再分布层;
焊球,其位于所述中介层芯片的顶表面上;以及
接合线,其从所述中介层芯片的所述顶表面延伸,所述接合线耦接到所述基板焊盘,
其中,所述焊球通过所述再分布层电连接到所述接合线,并且
所述中介层芯片在与所述第一基板的上表面平行的方向上的宽度大于所述第一半导体芯片在所述方向上的宽度。
17.根据权利要求16所述的半导体封装件,其中,当在平面图中观察时,所述第一半导体芯片完全位于由所述中介层芯片界定的区域内。
18.根据权利要求16所述的半导体封装件,其中,所述中介层芯片具有在30 W/mK至2000 W/mK的范围内的导热率。
19.根据权利要求16所述的半导体封装件,还包括:粘合层,其位于所述第一半导体芯片和所述中介层芯片之间,
其中,所述粘合层具有在0.2 W/mK至10 W/mK的范围内的导热率。
20.根据权利要求16所述的半导体封装件,还包括:
第一焊盘,其位于所述中介层芯片和所述焊球之间;
第二焊盘,其位于所述中介层芯片的所述顶表面上,所述第二焊盘耦接到所述接合线;以及
模塑层,其位于所述中介层芯片上,
其中,所述模塑层覆盖所述第二焊盘但不覆盖所述焊球。
21.根据权利要求16所述的半导体封装件,其中,所述第一半导体芯片具有面向所述第一基板的有源表面。
22.一种半导体封装件,包括:
第一基板,其包括绝缘体、以及在所述绝缘体的顶表面处的导电材料的第一基板焊盘和第二基板焊盘;
第一半导体芯片,其依照设置在所述第一基板的第一基板焊盘上并与所述第一基板焊盘电连接的方式倒装安装在所述第一基板上;
中介层,其位于所述第一半导体芯片上,所述中介层具有上部,该上部包括包含布线图案的再分布层;
导电材料的多个第一焊盘,其设置在所述中介层上;
导电材料的多个第二焊盘,其设置在所述中介层上并与所述多个第一焊盘横向向外隔开;
接合线,其将设置在所述中介层上的所述多个第二焊盘分别与所述第二基板焊盘电连接;和
模塑层,其设置在所述第一基板上,并且所述中介层、所述第一半导体芯片和所述接合线被封装在所述模塑层中,
其中,所述多个第二焊盘通过所述中介层的所述再分布层的所述布线图案电连接到所述多个第一焊盘,并且
所述模塑层中具有多个开口,所述多个开口通向设置在所述中介层上的所述多个第一焊盘并在所述多个第一焊盘处开口。
23.根据权利要求22所述的半导体封装件,其中,所述多个第一焊盘中的相应第一焊盘设置为邻近所述中介层的一侧,
所述多个第二焊盘中的相应第二焊盘设置为邻近所述中介层的所述一侧,
所述多个第一焊盘中的所述相应第一焊盘具有第一间距,所述各个第一焊盘在与所述中介层的所述一侧平行的方向上以所述第一间距彼此间隔开,
所述多个第二焊盘中的所述相应第二焊盘具有第二间距,所述相应第二焊盘在与所述中介层的所述一侧平行的方向上以所述第二间距彼此间隔开,并且
所述第一间距大于所述第二间距。
24.根据权利要求22所述的半导体封装件,其中,所述中介层具有在30W/mK至2000W/mK的范围内的导热率。
25.根据权利要求22所述的半导体封装件,还包括:
第二半导体芯片,其设置在所述模塑层上;以及
多个电连接件,其依照设置成与所述多个第一焊盘接触的方式分别介于所述第二半导体芯片和设置在所述中介层上的所述多个第一焊盘之间,
其中,所述第二半导体芯片通过所述多个电连接件中的至少一些电连接到所述再分布层。
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CN113517253A (zh) * | 2020-04-09 | 2021-10-19 | 南亚科技股份有限公司 | 半导体封装件 |
CN113871369A (zh) * | 2021-09-17 | 2021-12-31 | 合肥维信诺科技有限公司 | 芯片封装结构及其制备方法 |
WO2024007406A1 (zh) * | 2022-07-08 | 2024-01-11 | 长鑫存储技术有限公司 | 一种半导体封装件 |
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CN113517253A (zh) * | 2020-04-09 | 2021-10-19 | 南亚科技股份有限公司 | 半导体封装件 |
CN112563222A (zh) * | 2020-12-11 | 2021-03-26 | 华天科技(南京)有限公司 | 一种实现倒装凸点芯片互叠的三维封装结构及其制备方法 |
CN113871369A (zh) * | 2021-09-17 | 2021-12-31 | 合肥维信诺科技有限公司 | 芯片封装结构及其制备方法 |
WO2024007406A1 (zh) * | 2022-07-08 | 2024-01-11 | 长鑫存储技术有限公司 | 一种半导体封装件 |
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US20200020637A1 (en) | 2020-01-16 |
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JP2020013996A (ja) | 2020-01-23 |
KR20200007509A (ko) | 2020-01-22 |
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