TWI685071B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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TWI685071B
TWI685071B TW107104989A TW107104989A TWI685071B TW I685071 B TWI685071 B TW I685071B TW 107104989 A TW107104989 A TW 107104989A TW 107104989 A TW107104989 A TW 107104989A TW I685071 B TWI685071 B TW I685071B
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package
semiconductor package
semiconductor
die
hbm
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TW107104989A
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TW201832328A (zh
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林子閎
張嘉誠
彭逸軒
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聯發科技股份有限公司
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Abstract

本發明提供了一種半導體封裝結構。該半導體封裝結構包括：一第一半導體封裝和一第二半導體封裝，位於該第一半導體封裝的一部分上。該第一半導體封裝包括：一第一RDL結構，一第一半導體晶粒以及一模塑料。該第一半導體晶粒設置在該第一RDL結構的一第一表面上並且電性耦接至該第一RDL結構。該第一模塑料設置在該第一RDL結構的該第一表面上並且圍繞該第一半導體晶粒。該第二半導體封裝包括：一第一記憶體晶粒和一第二記憶體晶粒，垂直地堆疊於該第一記憶體晶粒上。該第二記憶體晶粒通過穿過該第二記憶體晶粒的矽通孔(TSV)互連結構電性耦接至該第一記憶體晶粒。

Description

半導體封裝結構
本發明涉及封裝技術，特別係涉及一種半導體封裝結構。
PoP(Package-on-Package，封裝上封裝/堆疊封裝)結構係一種用來垂直地組合SOC(System-On-Chip，系統單晶片)和記憶體封裝的積體電路封裝方式。兩個或者更多的封裝通過標準接口來安裝(即堆疊)於彼此的頂上，以在他們之間路由信號。PoP封裝允許在設備中具有更高的元件密度，其中設備諸如為行動電話、個人數位助理(personal digital assistants，PDA)，以及數位相機。
對於具有更高集成度以及改善的性能、帶寬、延遲、功率、重量以及形狀因子的記憶體應用，信號墊與接地墊之間的比率在改善耦合效應方面變得重要。
因此，本發明之主要目的即在於提供一種半導體封裝結構。
根據本發明至少一個實施例的一種半導體封裝結構，包括：一第一半導體封裝，包括：一第一重分佈層結構，具有一第一表面以及一相對於該第一表面的第二表面；一第一 半導體晶粒，設置在該第一表面上並且電性耦接至該第一重分佈層結構；以及一模塑料，設置在該第一表面上並且圍繞該第一半導體晶粒；以及一第二半導體封裝，位於該第一半導體封裝的一部分上，並且包括：一第一記憶體晶粒；以及一第二記憶體晶粒，垂直地堆疊於該第一記憶體晶粒上，其中該第二記憶體晶粒通過穿過該第二記憶體晶粒的矽通孔互連結構電性耦接至該第一記憶體晶粒。
本發明實施例，可以降低半導體封裝結構的橫向尺寸以及有效地避免封裝翹曲。
500A、500B、500C、500D，500E，500F‧‧‧半導體封裝 結構
A-A’‧‧‧剖面線
200‧‧‧基座
300A、300B、300C‧‧‧SOC封裝
400‧‧‧HBM封裝
202‧‧‧封裝附著面
204‧‧‧凸塊附著面
208、318、360、338‧‧‧導電跡線
206‧‧‧絕緣層
210、216、304‧‧‧接墊
212、214、321‧‧‧防焊罩層
220、604、322、452‧‧‧導電結構
302、302A、302B‧‧‧邏輯晶粒
316、326‧‧‧RDL結構
312‧‧‧模塑料
301、401‧‧‧前表面
303、403‧‧‧背面
310、314‧‧‧通孔
313‧‧‧晶粒附著面
315‧‧‧凸塊附著面
317、337‧‧‧IMD層
320、340‧‧‧RDL接觸墊
411、311、211、711A、711B‧‧‧邊界
600‧‧‧記憶體晶粒
602‧‧‧TSV互連結構
610‧‧‧控制器晶粒
D1、D2‧‧‧直徑
P1、P2‧‧‧間距
330‧‧‧底部填充材料
700A、700B‧‧‧散熱結構
704‧‧‧熱界面材料
720A、720B‧‧‧空間
702‧‧‧環形部分
706‧‧‧覆蓋部分
722A、722B‧‧‧內表面
333、335‧‧‧表面
通過閱讀接下來的詳細描述以及參考圖式所做的示例，可以更容易地理解本發明，其中：第1A圖為根據本發明一些實施例的半導體封裝結構的平面示意圖，其中該半導體封裝結構包括：一SOC封裝以及堆疊於其上的DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)封裝；第1B和1C圖為第1A圖所示的半導體封裝結構沿線A-A’的剖面示意圖；第1D圖為第1B和1C圖所示的半導體封裝結構的DRMA封裝的放大示意圖；第2A圖為根據本發明一些實施例的半導體封裝結構的平面示意圖，其中該半導體封裝結構包括：一SOC封裝以及堆疊於其上的DRAM封裝；以及第2B~2E圖為第2A圖所示的半導體封裝結構沿線A-A’ 的剖面示意圖。
以下描述為實現本發明的一種或複數種方式。該描述僅出於說明本發明的一般原理目的，並且不意味著限制。本發明的範圍可通過參考所附的申請專利範圍來確定。
本發明通過參考特定的實施例以及參考確定的圖式的方式來描述，但是本發明不限制於此，並且本發明僅受申請專利範圍的限制。描述的圖式僅是示意圖並且不是限制。在圖式中，出於說明目的和非按比例繪製，可能誇大了一些元件的尺寸。在圖式中的尺寸和相對尺寸不對應本發明實際中的真實尺寸。
在一些技術中，HBM(High Bandwidth Memory，高帶寬記憶體)一般與SOC放置在同一個封裝裡並且HBM和SOC並排佈置(side by side arrangement)，但是這會增加封裝的尺寸(橫向尺寸)並且導致嚴重的翹曲(warpage)問題。然而，本發明的一些實施例，通過將HBM和SOC分別放置在兩個封裝中，並且將HBM封裝堆疊在SOC封裝的一部分上，從而能夠縮小封裝的橫向尺寸並且降低封裝的翹曲問題。
第1A圖為根據本發明一些實施例的半導體封裝結構500A/500B的平面示意圖，其中該半導體封裝結構500A/500B包括：一SOC封裝以及至少一個堆疊於其上的高帶寬記憶體(High Bandwidth Memory，HBM)封裝(如高帶寬DRAM封裝)。第1A圖也示出了SOC封裝、HBM封裝和基座的佈置。在第1A圖中，省略了散熱結構。第1B圖為第1A圖 所示的半導體封裝結構500A沿線A-A’的剖面示意圖。第1D圖為第1B/1C圖所示的半導體封裝結構500A/500B中的DRAM封裝的放大示意圖。
在一些實施例中，該半導體封裝結構500A/500B為一PoP半導體封裝結構。該半導體封裝結構500A/500B包括：至少兩個安裝於基座200上的垂直堆疊的晶圓級半導體封裝。例如，該垂直堆疊的晶圓級半導體封裝包括：一SOC封裝300A和兩個垂直地堆疊於其上的HBM封裝400，如第1A和1B圖所示。需要注意的是，該半導體封裝結構500A/500B中整合的HBM封裝400的數目不限制於實施例公開的數量。
如第1A和1B圖所示，基座200可以包括：一封裝基底，例如PCB(Printed Circuit Board，印刷電路板)。在一些實施例中，該基座200具有一封裝附著面202和一相對於該封裝附著面202的凸塊附著面204。例如，該基座200可以為一單層或多層結構。該基座200可以包括：一導電跡線(conductive traces)208，一絕緣層206，一接墊(pad)210與216，一防焊罩層212與214，以及一導電結構220。在一些實施例中，該導電跡線可以包括：信號跡線段和接地跡線段，用於SOC封裝和HBM封裝的I/O(input/output，輸入/輸出)連接。該導電跡線可以電性連接至對應的接墊210與216。其中，接墊210放置在接近封裝附著面202的位置，以及接墊216放置在接近凸塊附著面204的位置。另外，接墊210暴露於防焊罩層212的開口，以及接墊216暴露於防焊罩層214的開口。接墊210可以用于SOC封裝直接安裝於其上。接墊216可以 用于導電結構220(如焊料球)直接形成於其上。
如第1A和1B圖所示，SOC封裝300A通過接合製程安裝於基座200的封裝附著面202上。SOC封裝300A通過導電結構322安裝於基座200上。在一些實施例中，SOC封裝300A為一半導體封裝，包括：一邏輯晶粒302，一RDL(Redistribution Layer，重分佈層)結構316以及一模塑料312。例如，該SOC封裝300A可以包括或不包括整合於其中的DRAM晶粒。該邏輯晶粒302可以包括：CPU(Central Processing Unit，中央處理單元)、GPU(Graphic Processing Unit，圖像處理單元)、DRAM控制器或者他們的任意組合。
如第1A和1B圖所示，該邏輯晶粒302具有一前表面301和一相對於該前表面301的背面303。邏輯晶粒302可以通過覆晶技術裝配。邏輯晶粒302的背面303接近或對齊SOC封裝300A的頂面。邏輯晶粒302的接墊304設置在前表面301上以電性連接至邏輯晶粒302的電路(未示出)。在一些實施例中，接墊304屬於邏輯晶粒302的互連結構(未示出)的最上層金屬層。邏輯晶粒302的接墊304接觸對應的通孔(vias)310。邏輯晶粒302的接墊304面向基座200。需要注意的是，SOC封裝300A中的邏輯晶粒302的數量不限制於本實施例。
在一些實施例中，如第1A和1B圖所示，SOC封裝300A的RDL結構316具有一晶粒附著面313和一相對於該晶粒附著面313的凸塊附著面315。該SOC封裝300A的邏輯晶粒302設置在RDL結構316的晶粒附著面313上。邏輯晶 粒302的接墊304通過通孔310電性耦接至RDL結構316，其中該通孔310位於邏輯晶粒302的前表面301與RDL結構316的晶粒附著面313之間。RDL結構316接觸通孔310。在一些實施例中，RDL結構316包括：一導電跡線318，一金屬間介電(Intermetal Dielectric，IMD)層317，一防焊罩層321以及一RDL接觸墊320。例如，導電跡線318設置在對應的IMD層317中。導電跡線318電性連接至對應的RDL接觸墊320，其中該RDL接觸墊320接近凸塊附著面315。另外，RDL接觸墊320填充防焊罩層321的開口。
如第1A和1B圖所示，導電跡線318可以設計為自邏輯晶粒302的一個或複數個接墊304向外扇出，以提供邏輯晶粒302與RDL接觸墊320之間的電連接。因此，RDI接觸墊320可以具有比邏輯晶粒302的接墊304更大的接合間距(中心點之間的距離)，並且RDL接觸墊320更適合於球柵陣列或者另一封裝安裝系統。
但是，需要注意的是，第1A和1B圖中所示的導電跡線318的數量，IMD層317的數量以及RDL接觸墊320的數量僅係示例而不是對本發明的限制。
在一些實施例中，如第1A和1B圖所示，SOC封裝300A的模塑料312位於RDL結構316和邏輯晶粒302上。模塑料312接觸邏輯晶粒302的背面303以及RDL結構316的晶粒附著面313；在一些實施例中，模塑料312可以與邏輯晶粒302的背面303對齊。在一些實施例中，模塑料312可以由非導電材料形成，例如環氧樹脂、樹脂、可塑聚合物，等等。 模塑料312可以在基本為液體時(諸如以環氧樹脂或樹脂的形式)應用，並且接著通過化學反應固化。在其他的一些實施例中，模塑料312可以為UV(ultraviolet，紫外)或熱固化聚合物，作為能夠設置在邏輯晶粒302周圍的膠體或可塑固體而應用，並且接著通過UV或者熱固化製程進行固化。模塑料312可以按照模塑(沒有示出)進行固化。
在一些實施例中，如第1A和1B圖所示，SOC封裝300A的導電結構322位于RDL結構316的凸塊附著面315與基座200的封裝附著面202之間。另外，導電結構322電性耦接至RDL結構316的RDL接觸墊320以及基座200的接墊210。導電結構322通過RDL接觸墊320耦接至導電跡線318。在一些實施例中，導電結構322可以包括：導電凸塊結構，諸如銅凸塊或者焊料凸塊結構，導電柱結構，導電線結構或者導電膏(conductive paste)結構。
在一些實施例中，如第1A和1B圖所示，半導體封裝結構500A的複數個HBM封裝400彼此隔開，並且通過接合製程堆疊在SOC封裝300A上。在一些實施例中，每個HBM封裝400均為符合引腳佈置規則(如JEDEC寬I/O記憶體規範)的高帶寬DRAM封裝。每個HBM封裝400設置在SOC封裝300A的一部分上(或者設置在邏輯晶粒302的一部分上)。因此，從第1A圖所示的平面示意圖來看，每個HBM封裝400的邊界411被SOC封裝300A的模塑料312的邊界311所圍繞。每個HBM封裝400位於RDL結構316的凸塊附著面315與基座200之間，如第1B圖所示。另外，每個HBM封裝400設置 在RDL結構316的凸塊附著面315的一部分上並且通過RDL結構316與邏輯晶粒302隔開。在一些實施例中，每個HBM封裝400緊鄰導電結構322並且電性耦接至SOC封裝300A的RDL結構316。每個HBM封裝400嵌入於基座200中並且被SOC封裝300A的導電結構322圍繞。另外，每個HBM封裝400被基座200圍繞。
在一些實施例中，每個HBM封裝400的背面403與基座200的凸塊附著面204同平面。在一些實施例中，每個HBM封裝400的背面403位於基座200的封裝附著面202與凸塊附著面204之間。在一些實施例中，每個HBM封裝400的背面403超過基座200的凸塊附著面204。
在一些實施例中，如第1A，1B和1D圖所示，每個HBM封裝400包括：複數個記憶體晶粒600，一個堆疊在另一個的頂上。每個HBM封裝400中的記憶體晶粒600可以通過覆晶技術裝配。每個HBM封裝400具有一前表面401和一相對於該前表面的背面403。另外，每個記憶體晶粒600包括：TSV(through silicon via，矽通孔)互連結構602和導電結構604。其中，TSV互連結構602設置為穿過對應的記憶體晶粒600。導電結構604位於對應的記憶體晶粒600的前表面上。例如，記憶體晶粒600之一可以堆疊在另一記憶體晶粒600的背面403上，並且通過TSV互連結構602和記憶體晶粒600之一的導電結構604電性連接至另一記憶體晶粒600。在一些實施例中，每個HBM封裝400包括：TSV互連結構602而不是RDL結構。另外，每個HBM封裝400可以進一步包括：一 控制器晶粒610，電性耦接至導電結構452。記憶體晶粒600可以堆疊在控制器晶粒610上，並且電性耦接至控制器晶粒610。例如，每個HBM封裝400的控制器晶粒610可以用來控制對應的記憶體晶粒600。需要注意的是，記憶體晶粒600的數量不限制於公開的實施例。
在一些實施例中，如第1A和1B圖所示，每個HBM封裝400包括：複數個導電結構452，接觸RDL結構316的凸塊附著面315並且電性耦接至RDL結構316。例如，SOC封裝300A的每個導電結構322具有第一直徑D1，HBM封裝400的每一個導電結構452具有第二直徑D2，其中第二直徑D2小於第一直徑D1。另外，每個HBM封裝400的導電結構452的直徑也可以設置為小於第一直徑D1和第二直徑D2。因此，導電結構452也可以作為微凸塊。
在一些實施例中，如第1A和1B圖所示，SOC封裝300A的導電結構322以第一間距P1重複佈置，並且每個HBM封裝400的導電結構452以第二間距P2佈置，其中第二間距P2小於第一間距P1。另外，每個HBM封裝400的導電結構452可以以小於第一間距P1和第二間距P2的間距來佈置。
在一些實施例中，如第1B圖所示，底部填充材料330可以通過回流製程引入SOC封裝300A，HBM封裝400和基座200之間的間隙。底部填充材料330可以用於補償基座200，SOC封裝300A和HBM封裝400之間的不同的CTE(Thermal Expansion，熱膨脹)係數。在一些實施例中，SOC封裝300A 的導電結構322以及每個HBM封裝400的導電結構452可以被底部填充材料330圍繞。在一些實施例中，底部填充材料330可以為CUF(Capillary Underfill，毛細底部填充材料)、MUF(Molded Underfill，模塑底部填充材料)或者他們的組合。
在一些實施例中，如第1B圖所示，SOC封裝300A進一步包括：一散熱結構700A，位於SOC封裝300A和HBM封裝400上方。散熱結構700A可以通過熱界面材料704(或者熱膏)連接至基座的封裝附著面202，以形成容納SOC封裝300A和HBM封裝400的空間720A。例如，散熱結構700A通過熱界面材料704連接至SOC封裝300A的背面303。另外，散熱結構700A的邊界711A可以對齊基座200的邊界211，如第1B圖所示。
在一些實施例中，如第1B圖所示，散熱結構700A包括：一位於基座200的上方的環形部分702，以及一位於該環形部分702上方的覆蓋部分706。例如，散熱結構700A的環形部分702連接基座200的封裝附著面202的沒有被SOC封裝300A和HBM封裝400覆蓋的部分。散熱結構700A的環形部分702圍繞SOC封裝300A和HBM封裝400。另外，散熱結構700A的覆蓋部分706覆蓋SOC封裝300A和HBM封裝400。散熱結構700A的覆蓋部分706通過熱界面材料704連接至環形部分702。覆蓋部分706的內表面722A通過熱界面材料704連接至SOC封裝300A。因此，SOC封裝300A和HBM封裝400產生的熱可以更容易地擴散至散熱結構700A。
在一些實施例中，散熱結構700A的環形部分702 和覆蓋部分706可以由金屬材料形成，例如銅、不銹鋼或者其他合適的金屬材料。在一些實施例中，熱界面材料704主要由基質材料(matrix material)和大體積分數的電絕緣但是導熱的填料構成。例如，基質材料可以包括：環氧樹脂、矽樹脂、尿烷、丙烯酸酯或者其他適合的基質材料。另外，膠帶(adhesive tapes)也適合於作為基質材料。例如，該填料包括：氧化鋁、氮化硼、氧化鋅或者他們的組合。
第1C圖為第1A圖所示的半導體封裝結構500B沿線A-A’的平面示意圖。以下實施例的元件，有相同或者相似於先前參考第1A和1B圖已描述了的，出於簡潔而不再重複。半導體封裝結構500B與半導體封裝結構500A之間的不同在於：半導體封裝結構500B包含一整體的(one-piece)散熱結構700B，即一體式(all-in-one)散熱結構。例如，散熱結構700B在剖面示意圖中具有顛倒的U形，如第1C圖所示。散熱結構700B的底面721通過熱界面材料704連接至基座200的封裝附著面202上未被SOC封裝300A和HBM封裝400覆蓋的部分。散熱結構700B和基座200共同形成容納SOC封裝300A和HBM封裝400的空間720B。另外，散熱結構700B的內表面722B通過熱界面材料704連接至SOC封裝300A的背面303。另外，散熱結構700B的邊界711B對齊基座200的邊界211，如第1C圖所示。另外，散熱結構700B的內表面722B通過熱界面材料704連接至SOC封裝300A，以有助於擴散由SOC封裝300A和HBM封裝400所產生的熱。
在一些實施例中，半導體封裝結構(如半導體封 裝結構500A和500B)的HBM封裝400直接位於邏輯晶粒302的一部分的下方。HBM封裝400可以位於SOC封裝300A和基座200之間的間隙之間。另外，HBM封裝400可以嵌入於基座200的一部分中，或者穿過基座200以降低半導體封裝結構的高度。在一些實施例中，相同HBM封裝400中的DRAM晶粒600和SOC封裝300A的邏輯晶粒302可以彼此重疊並且分別連接至RDL結構316的凸塊附著面315和晶粒附著面313。因此，可以進一步降低SOC封裝300A和HBM封裝400之間沿大致平行於RDL的晶粒附著面313(或凸塊附著面315)的傳輸路徑。半導體封裝結構500A/500B在網絡應用中具有低阻抗。
在一些實施例中，半導體封裝結構(如半導體封裝結構500A和500B)包括：散熱結構(如散熱結構700A和700B)，位於SOC封裝300A和HBM封裝400上方並且連接至基座200以形成容納SOC封裝300A和HBM封裝400的空間(如空間720A和720B)。散熱結構700A例如由環形部分702和覆蓋部分706組成。例如，散熱結構700B可以為一整體結構。另外，散熱結構可以通過熱界面材料704連接至SOC封裝300A，以有助於擴散由SOC封裝300A和HBM封裝400產生的熱。
第2A圖為根據本發明一些實施例的半導體封裝結構500C(或500D，500E，500F)的平面示意圖，其中該半導體封裝結構500C/500D/500E/500F包括：SOC封裝300B(或300C)以及堆疊於其上的四個HBM封裝400。第2A圖也示出 了SOC封裝、HBM封裝以及基座的佈置。在第2A圖中，省略了散熱結構。第2B圖為第2A圖所示的半導體封裝結構500C沿線A-A’的剖面示意圖。以下實施例中描述的元件，有相同或者類似於先前參考第1A~1D圖已描述了的，出於簡潔而不再重複。
在一些實施例中，如第2A及2B圖所示，半導體封裝結構500C與半導體封裝結構500A(第1A~1B圖)之間的不同在於：半導體封裝結構500C包括：一SOC封裝300B。在一些實施例中，該SOC封裝300B包括：一第一邏輯晶粒302A與一緊鄰該第一邏輯晶粒302A的第二邏輯晶粒302B。該第一邏輯晶粒302A與第二邏輯晶粒302B可以通過導電跡線360彼此電性耦接。另外，第一邏輯晶粒302A與第二邏輯晶粒302B可以電性耦接至RDL結構316。例如，根據提高單個邏輯晶粒的製造產量的職責，將邏輯晶粒302(第1A~1C圖)分為第一邏輯晶粒302A與第二邏輯晶粒302B。在一些實施例中，四個HBM封裝400垂直堆疊在第一邏輯晶粒302A與第二邏輯晶粒302B中的任一個上，如第2A和2B圖所示。需要注意的是，半導體封裝結構500C(或500D，500E，500F)中整合的HBM封裝400的數量不限制於本實施例。
在一些實施例中，如第2A和2B圖所示，SOC封裝300B進一步包括：一RDL結構326，位於模塑料312的上方並且通過模塑料312與RDL結構316分開。另外，RDL結構316和RDL結構326分別與模塑料312的相對表面333和335接觸。在一些實施例中，RDL結構326包括：導電跡線338， IMD層337和RDL接觸墊340。另外，導電跡線(第2A圖)位於RDL結構326中並且電性連接至第一邏輯晶粒302A和第二邏輯晶粒302B。
在一些實施例中，如第2A及2B圖所示，SOC封裝300B進一步包括：通孔314，穿過模塑料312。因此，通孔314可以作為TPV(Through Package Vias，穿過封裝的通孔)。通孔314可以設置為圍繞SOC封裝300B的第一邏輯晶粒302A和第二邏輯晶粒302B。另外，每個通孔314均具有分別接觸並且電性耦接至RDL結構316和326的兩端。
在一些實施例中，如第2A和2B圖所示，第一邏輯晶粒302A和第二邏輯晶粒302B以及HBM封裝400均位於RDL結構316的晶粒附著面的上方。HBM封裝400可以通過RDL結構316，通孔314和RDL結構326在空間上遠離SOC封裝300B的導電結構332。另外，RDL結構316位於SOC封裝300B的導電結構322和通孔314之間。RDL結構326位於HBM封裝400和通孔314之間。因此，第一邏輯晶粒302A與第二邏輯晶粒302B的接墊304面向基座200。另外，HBM封裝400的導電結構452和模塑料312分別接觸RDL結構326的相對表面。因此，HBM封裝400通過RDL結構326和通孔314電性耦接至RDL結構316。
在一些實施例中，如第2B圖所示，散熱結構700A的環形部分702圍繞SOC封裝300B。另外，散熱結構700A的覆蓋部分706覆蓋SOC封裝300B和HBM封裝400。覆蓋部分706的內表面722A通過熱界面材料704連接至SOC封裝 300B和HBM封裝400。因此，SOC封裝300B和HBM封裝400產生的熱可以更容易地擴散至散熱結構700A。
第2C圖為第2A圖所示的半導體封裝結構500D沿線A-A’的剖面示意圖。以下實施例中的元件，有相同或者類似於先前參考第1A~1C，2A及2B圖已描述了的，出於簡潔而不再重複。半導體封裝結構500D和500C之間的不同在於：半導體封裝結構500D包括：一整體的散熱結構700B。散熱結構700B的內表面722B通過熱界面材料704連接至SOC封裝300B和HBM封裝400。另外，散熱結構700B的佈置相同或者類似於先前參考第1C圖的描述，因此出於簡潔而不再重複。
第2D圖為第2A圖所示的半導體封裝結構500E沿線A-A’的剖面示意圖。以下實施例描述的元件，有相同或者類似於先前參考第1A~1C和2A~2C圖已描述了的，出於簡潔而不再重複。
在一些實施例中，如第2A和2D圖所示，半導體封裝結構500E與半導體封裝結構500C(第2A~2B圖)之間的不同在於：半導體封裝結構500E的SOC封裝300C中的邏輯晶粒的前表面背向基座200。在SOC封裝300C中，RDL結構326位於導電結構322和通孔314之間，RDL結構316位於HBM封裝400和通孔314之間。因此，第一邏輯晶粒302A和第二邏輯晶粒302B位於RDL結構316的晶粒附著面313上，以及HBM封裝(連同導電結構452)位於RDL結構316的凸塊附著面315上。因為HBM封裝400位於SOC封裝300C的 上方，因此HBM封裝400通過SOC封裝300C與基座分開。第一邏輯晶粒302A和第二邏輯晶粒302C的接墊304背向基座200。另外，SOC封裝300C的導電結構322位於RDL結構326上，並且第一邏輯晶粒302A和第二邏輯晶粒302B通過RDL結構316、通孔314和RDL結構326耦接至導電結構322。
在一些實施例中，如第2D圖所示，散熱結構700A的環形部分702圍繞SOC封裝300C。另外，散熱結構700A的覆蓋部分706覆蓋SOC封裝300C和HBM封裝400。散熱結構700A的覆蓋部分706的內表面722A通過熱界面材料704連接至SOC封裝300C和HBM封裝400。因此，SOC封裝300C和HBM封裝400產生的熱能夠更容易地擴散至散熱結構700A。
第2E圖為第2A圖所示的半導體封裝結構500F沿線A-A’的剖面示意圖。以下實施例描述的元件，有相同或者類似於先前參考第1A~1C以及2A~2D圖已描述了的，出於簡潔而不再重複。半導體封裝結構500F與500E之間的不同在於：半導體封裝結構500F包括：一整體的散熱結構700B。散熱結構700B的內表面722B通過熱界面材料704連接至SOC封裝300C和HBM封裝400。另外，散熱結構700B的佈置相同或者類似於先前參考第1C和2C圖所描述的情況，因此出於簡潔而不再重複。
如前所述，半導體封裝結構(如半導體封裝結構500C~500F)的SOC封裝(如SOC封裝300B和300C)包括：兩個RDL結構(如RDL結構316和326)，分別設置在模塑料 312的相對表面。因此，HBM封裝400的導電結構452和SOC封裝的導電結構332可以接觸不同的RDL結構316和326。另外，SOC封裝的邏輯晶粒(如第一和第二邏輯晶粒302A、302B)的接墊304可以面向或者背向基座200，以增加設計靈活性。
本發明的各實施例提供了半導體封裝結構500A~500F。半導體封裝結構500A~500F可以提供複數個堆疊在SOC封裝(如SOC封裝300A~300C)的HBM封裝(如HBM封裝400)。HBM封裝可以由三維堆疊的具有TSV互連結構的DRMA晶粒構成，其中TSV互連結構穿過DRAM晶粒。在一些實施例中，HBM封裝可以安裝在SOC封裝的RDL結構的凸塊附著面上並且嵌入在基座中。SOC封裝和HBM封裝之間的橫向傳輸路徑(大致平行於RDL結構的晶粒附著面(或凸塊附著面))可以進一步降低。在一些實施例中，半導體封裝結構的SOC封裝可以包括：兩個RDL結構，分別設置在模塑料的相對表面，以有助於其上的HBM封裝的接合，以及通過穿過模塑料的TPV(如通孔314)電性連接至邏輯晶粒。因此，半導體封裝結構500A~500F在網絡應用中，可以滿足低阻抗、高帶寬和快速轉變的要求。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
500A‧‧‧半導體封裝結構
200‧‧‧基座
300A‧‧‧SOC封裝
400‧‧‧HBM封裝
202‧‧‧封裝附著面
204‧‧‧凸塊附著面
208、318‧‧‧導電跡線
206‧‧‧絕緣層
210、216、304‧‧‧接墊
212、214、321‧‧‧防焊罩層
220、322、452、604‧‧‧導電結構
302‧‧‧邏輯晶粒
316‧‧‧RDL結構
312‧‧‧模塑料
301、401‧‧‧前表面
303、403‧‧‧背面
310‧‧‧通孔
313‧‧‧晶粒附著面
315‧‧‧凸塊附著面
317‧‧‧IMD層
320‧‧‧RDL接觸墊
211、711A‧‧‧邊界
P1、P2‧‧‧間距
330‧‧‧底部填充材料
700A‧‧‧散熱結構
704‧‧‧熱界面材料
720A‧‧‧空間
702‧‧‧環形部分
706‧‧‧覆蓋部分
722A‧‧‧內表面

Claims (7)

  1. 一種半導體封裝結構，包括：一第一半導體封裝，包括：一第一重分佈層結構，具有一第一表面以及一相對於該第一表面的第二表面；一第一半導體晶粒，電性耦接至該第一重分佈層結構；以及一模塑料，設置在該第一表面上並且圍繞該第一半導體晶粒；一第一導電結構，設置在該第一重分佈層結構的該第二表面上；以及一第二半導體封裝，位於該第一半導體封裝的一部分上，並且包括：一第一記憶體晶粒；以及一第二記憶體晶粒，垂直地堆疊於該第一記憶體晶粒上，其中該第二記憶體晶粒通過穿過該第二記憶體晶粒的矽通孔互連結構電性耦接至該第一記憶體晶粒；一第二導電結構，電性耦接至該第一半導體封裝；其中，該半導體封裝結構進一步包括：一基座，該第一半導體封裝以及該第二半導體封裝通過該第一導電結構安裝於該基座上；該第二半導體封裝嵌入於該基座中，該第一導電結構和該第二導電結構均接觸該第一重分佈層結構的該第二表面。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中該第 一導電結構具有第一直徑，該第二導電結構具有小於該第一直徑的第二直徑，且該第二直徑；及/或，以第一間距佈置該第一導電結構，以小於該第一間距的第二間距佈置該第二導電結構。
  3. 如申請專利範圍第1項所述的半導體封裝結構，其中，進一步包括：一散熱結構，位於該第一半導體封裝和該第二半導體封裝的上方，其中該散熱結構連接至該基座以形成用於容納該第一半導體封裝和該第二半導體封裝的空間。
  4. 如申請專利範圍第3項所述的半導體封裝結構，其中，該散熱結構包括：一環形部分，連接至該基座並且圍繞該第一半導體封裝；以及一覆蓋部分，覆蓋該第一半導體封裝以及該第二半導體封裝並且連接至該環形部分。
  5. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第二半導體晶粒，與所述第一半導體晶粒並排設置並且電性耦接至該第一重分佈層結構。
  6. 如申請專利範圍第1項所述的半導體封裝結構，其中，在平面視圖中，該模塑料的邊界圍繞該第二半導體封裝的邊界。
  7. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體晶粒為邏輯晶粒，該第一半導體封裝為系統單晶 片封裝，該第二半導體封裝為高帶寬記憶體封裝。
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