CN108447860A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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Publication number
CN108447860A
CN108447860A CN201810133272.7A CN201810133272A CN108447860A CN 108447860 A CN108447860 A CN 108447860A CN 201810133272 A CN201810133272 A CN 201810133272A CN 108447860 A CN108447860 A CN 108447860A
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Prior art keywords
semiconductor
encapsulation
semiconductor packages
redistribution layer
semiconductor package
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Granted
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CN201810133272.7A
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CN108447860B (zh
Inventor
林子闳
张嘉诚
彭逸轩
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明实施例提供了一种半导体封装结构，其包括：第一半导体封装和第二半导体封装，该第二半导体封装位于该第一半导体封装的一部分上。该第一半导体封装包括：第一RDL结构，第一半导体管芯以及模塑料。该第一半导体管芯设置在该第一RDL结构的第一表面上并且电性耦接至该第一RDL结构。该第一模塑料设置在该第一RDL结构的该第一表面上并且围绕该第一半导体管芯。该第二半导体封装包括：第一存储器管芯和第二存储器管芯，垂直地堆叠于该第一存储器管芯上。该第二存储器管芯通过穿过该第二存储器管芯的硅通孔(TSV)互连结构电性耦接至该第一存储器管芯。

Description

半导体封装结构
技术领域
本发明涉及封装技术，尤其涉及一种半导体封装结构。
背景技术
PoP(Package-on-Package，封装上封装，或堆叠封装)结构是一种用来垂直地组合SOC(System-On-Chip，片上系统)和存储器封装的集成电路封装方式。两个或者更多的封装通过标准接口安装(即堆叠)于彼此的顶上，以在他们之间路由信号。PoP封装允许在设备中具有更高的元件密度，诸如移动电话、个人数字助理(Personal Digital Assistant，PDA)，以及数码相机。
对于具有更高集成度和改善的性能、带宽、延迟、功率、重量以及形状因子的存储器应用，信号垫与接地垫之间的比率在改善耦合效应方面变得重要。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装结构。
本发明实施例提供了一种半导体封装结构，包括：第一半导体封装和位于该第一半导体封装的一部分上的第二半导体封装；其中，该第一半导体封装，包括：第一重分布层结构，具有第一表面以及相对于该第一表面的第二表面；第一半导体管芯，电性耦接至该第一重分布层结构；以及模塑料，设置在该第一表面上并且围绕该第一半导体管芯；其中，该第二半导体封装包括：第一和第二存储器管芯，其中该第二存储器管芯垂直地堆叠于该第一存储器管芯上，并且该第二存储器管芯通过穿过其的硅通孔互连结构电性耦接至该第一存储器管芯。
其中，该第一半导体封装进一步包括：第一导电结构，设置在该第一重分布层结构的该第二表面上；该第二半导体封装进一步包括：第二导电结构，电性耦接至该第一半导体封装。
其中，该第一导电结构具有第一直径，该第二导电结构具有小于该第一直径的第二直径，且该第二直径小于该第一直径；
或者，该第一导电结构以第一间距重复地设置，以及该第二导电结构以小于该第一间距的第二间距重复地设置。
其中，进一步包括：基座，该第一半导体封装和该第二半导体封装通过该第一导电结构安装于该基座上。
其中，该第二半导体封装嵌入于该基座中，并且该第一和第二导电结构均接触该第一重分布层结构的该第二表面。
其中，进一步包括：散热结构，位于该第一半导体封装和该第二半导体封装的上方，其中该散热结构连接至该基座以形成用于容纳该第一半导体封装和该第二半导体封装的空间。
其中，该散热结构包括：环形部分和覆盖部分，其中该环形部分连接至该基座并且围绕该第一半导体封装，该覆盖部分覆盖该第一半导体封装和该第二半导体封装并且连接至该环形部分。
其中，该第一半导体封装进一步包括：第二半导体管芯，与所述第一半导体管芯并排设置并且电性耦接至该第一重分布层结构。
其中，在平面视图中，该模塑料的边界围绕该第二半导体封装的边界。
其中，该第二半导体封装的该第二导电结构通过穿过该模塑料的第一通孔电性耦接至该第一半导体封装的该第一重分布层结构。
其中，该第一半导体封装进一步包括：第二重分布层结构，位于该模塑料上并且通过该模塑料与该第一重分布层结构隔开，其中该第二半导体封装设置在该第二重分布层结构上，并且该第二导电结构通过该第二重分布层结构以电性耦接至该第一通孔。
其中，该第一半导体管芯的接垫面向该第一重分布层结构，并且该接垫通过直接设置于其上的第二通孔电性耦接至该第一重分布层结构，其中该第二通孔位于该第一半导体管芯与该第一重分布层结构的该第一表面之间。
其中，该第一半导体管芯的接垫背向该第一重分布层结构，并且该接垫电性耦接至该第二重分布层结构，并且该接垫通过该第二重分布层结构以及穿过该模塑料的第三通孔电性耦接至该第一重分布层结构。
其中，该第一半导体管芯为逻辑管芯，该第一半导体封装为片上系统封装，该第二半导体封装为高带宽存储器封装。
本发明实施例的有益效果是：
本发明实施例，可以降低半导体封装结构的横向尺寸以及有效地避免封装翘曲问题。
附图说明
通过阅读接下来的详细描述以及参考附图所做的示例，可以更容易地理解本发明，其中：
图1A为根据本发明一些实施例的半导体封装结构的平面示意图，其中该半导体封装结构包括：SOC封装和堆叠于其上的DRAM(Dynamic Random Access Memory，动态随机存取存储器)封装；
图1B和1C为图1A所示的半导体封装结构沿线A-A’的剖面示意图；
图1D为图1B和1C所示的半导体封装结构中的DRMA封装的放大示意图；
图2A为根据本发明一些实施例的半导体封装结构的平面示意图，该半导体封装结构包括：SOC封装和堆叠于其上的DRAM封装；以及
图2B～2E为图2A所示的半导体封装结构沿线A-A’的剖面示意图。
具体实施方式
以下描述为实现本发明的一种或多种方式。该描述仅出于说明本发明的一般原理目的，并且不意味着限制。本发明的范围可通过参考所附的权利要求来确定。
本发明通过参考某些实施例和某些附图的方式来描述，但是本发明不限制于此，并且本发明仅受权利要求的限制。描述的附图仅是示意图并且不是限制。在附图中，出于说明目的和非按比例绘制，可能夸大了一些元件的尺寸。在附图中的尺寸和相对尺寸不对应本发明实际中的真实尺寸。在一些技术中，HBM(High Bandwidth Memory，高带宽存储器)一般与SOC放置在同一个封装里并且HBM和SOC并排(side by side)布置，但是这会增加封装的尺寸(横向尺寸)并且导致严重的翘曲(warpage)问题。然而，本发明的一些实施例，通过将HBM和SOC分别放置在两个封装中，并且将HBM封装堆叠在SOC封装的一部分上，从而能够缩小封装的横向尺寸并且降低封装的翘曲问题。
图1A为根据本发明一些实施例的半导体封装结构500A/500B的平面示意图，其中该半导体封装结构500A/500B包括：SOC封装以及至少一个堆叠于其上的高带宽存储器(High Bandwidth Memory，HBM)封装(如高带宽DRAM封装)。图1A也示出了SOC封装、HBM封装和基座的布置。在图1A中，省略了散热结构。图1B为图1A所示的半导体封装结构500A沿线A-A’的剖面示意图。图1D为图1B/1C所示的半导体封装结构500A/500B中的DRAM封装的放大示意图。
在一些实施例中，该半导体封装结构500A/500B为PoP半导体封装结构。该半导体封装结构500A/500B包括：至少两个安装于基座200上的垂直堆叠的晶圆级半导体封装。例如，该垂直堆叠的晶圆级半导体封装包括：SOC封装300A和两个垂直地堆叠于其上的HBM封装400，如图1A和1B所示。需要注意的是，该半导体封装结构500A/500B中整合的HBM封装400的数目不限制于实施例公开的数量。
如图1A和1B所示，基座200可以包括封装基底，例如PCB(Printed Circuit Board，印刷电路板)。在一些实施例中，该基座200具有封装附着面202和相对于该封装附着面202的凸块附着面204。例如，该基座200可以为单层或多层结构。该基座200可以包括：导电迹线(conductive traces)208，绝缘层206，接垫(pad)210与216，阻焊层212与214，以及导电结构220。在一些实施例中，该导电迹线可以包括：信号迹线段和接地迹线段，用于SOC封装和HBM封装的I/O(Input/output,输入/输出)连接。该导电迹线可以电性连接至对应的接垫210与216。其中，接垫210放置在接近封装附着面202的位置，以及接垫216放置在接近凸块附着面204的位置。另外，接垫210暴露于阻焊层212的开口，以及接垫216暴露于阻焊层214的开口。接垫210可以用于SOC封装直接安装于其上。接垫216可以用于导电结构220(如焊料球)直接形成于其上。
如图1A和1B所示，SOC封装300A通过接合工艺安装于基座200的封装附着面202上。SOC封装300A通过导电结构322安装于基座200上。在一些实施例中，SOC封装300A为半导体封装，包括：逻辑管芯302，RDL(Redistribution Layer，重分布层)结构316以及模塑料312。例如，该SOC封装300A可以包括或不包括整合于其中的DRAM管芯。该逻辑管芯302可以包括：CPU(Central Processing Unit，中央处理单元)、GPU(Graphic Processing Unit，图像处理单元)、DRAM控制器或者他们的任意组合。
如图1A和1B所示，该逻辑管芯302具有前表面301和相对于该前表面301的背面303。逻辑管芯302可以通过倒装芯片技术装配。逻辑管芯302的背面303接近或对齐SOC封装300A的顶面。逻辑管芯302的接垫304设置在前表面301上以电性连接至逻辑管芯302的电路(未示出)。在一些实施例中，接垫304属于逻辑管芯302的互连结构(未示出)的最上层金属层。逻辑管芯302的接垫304接触对应的通孔(vias)310。逻辑管芯302的接垫304面向基座200。需要注意的是，SOC封装300A中的逻辑管芯302的数量不限制于本实施例。
在一些实施例中，如图1A和1B所示，SOC封装300A的RDL结构316具有管芯附着面313和相对于该管芯附着面313的凸块附着面315。该SOC封装300A的逻辑管芯302设置在RDL结构316的管芯附着面313上。逻辑管芯302的接垫304通过通孔310电性耦接至RDL结构316，其中该通孔310位于逻辑管芯302的前表面301与RDL结构316的管芯附着面313之间。RDL结构316接触通孔310。在一些实施例中，RDL结构316包括：导电迹线318，金属间介电(Intermetal Dielectric，IMD)层317，阻焊层321以及RDL接触垫320。例如，导电迹线318设置在对应的IMD层317中。导电迹线318电性连接至对应的RDL接触垫320，其中该RDL接触垫320接近凸块附着面315。另外，RDL接触垫320填充阻焊层321的开口。
如图1A和1B所示，导电迹线318可以设计为自逻辑管芯302的一个或多个接垫304向外扇出，以提供逻辑管芯302与RDL接触垫320之间的电连接。因此，RDL接触垫320可以具有比逻辑管芯302的接垫304更大的接合间距(中心点之间的距离)，并且RDL接触垫320更适合于球栅阵列或者另一封装安装系统。
但是，需要注意的是，图1A和1B中所示的导电迹线318的数量，IMD层317的数量以及RDL接触垫320的数量仅是示例而不是对本发明的限制。
在一些实施例中，如图1A和1B所示，SOC封装300A的模塑料312位于RDL结构316和逻辑管芯302上。模塑料312接触逻辑管芯302的背面303以及RDL结构316的管芯附着面313。在一些实施例中，模塑料312可以与逻辑管芯302的背面303对齐。在一些实施例中，模塑料312可以由非导电材料形成，例如环氧树脂、树脂、可塑聚合物，等等。模塑料312可以在基本为液体时(诸如以环氧树脂或树脂的形式)应用，并且接着通过化学反应固化。在其他的一些实施例中，模塑料312可以为UV(ultraviolet，紫外)或热固化聚合物，作为能够设置在逻辑管芯302周围的胶体或可塑固体而应用，并且接着通过UV或者热固化工艺进行固化。模塑料312可以按照模塑(没有示出)进行固化。
在一些实施例中，如图1A和1B所示，SOC封装300A的导电结构322位于RDL结构316的凸块附着面315与基座200的封装附着面202之间。另外，导电结构322电性耦接至RDL结构316的RDL接触垫320以及基座200的接垫210。导电结构322通过RDL接触垫320耦接至导电迹线318。在一些实施例中，导电结构322可以包括：导电凸块结构，诸如铜凸块或者焊料凸块结构，导电柱结构，导电线结构或者导电膏(conductive paste)结构。
在一些实施例中，如图1A和1B所示，半导体封装结构500A的多个HBM封装400彼此隔开，并且通过接合工艺堆叠在SOC封装300A上。在一些实施例中，每个HBM封装400均为符合引脚布置规则(如JEDEC宽I/O存储器规范)的高带宽DRAM封装。每个HBM封装400设置在SOC封装300A的一部分上(或者设置在逻辑管芯302的一部分上)。因此，从图1A所示的平面示意图来看，每个HBM封装400的边界411被SOC封装300A的模塑料312的边界311所违绕。每个HBM封装400位于RDL结构316的凸块附着面315与基座200之间，如图1B所示。另外，每个HBM封装400设置在RDL结构316的凸块附着面315的一部分上并且通过RDL结构316与逻辑管芯302隔开。在一些实施例中，每个HBM封装400紧邻导电结构322并且电性耦接至SOC封装300A的RDL结构316。每个HBM封装400嵌入于基座200中并且被SOC封装300A的导电结构322围绕。另外，每个HBM封装400被基座200围绕。
在一些实施例中，每个HBM封装400的背面403与基座200的凸块附着面204同平面。在一些实施例中，每个HBM封装400的背面403位于基座200的封装附着面202与凸块附着面204之间。在一些实施例中，每个HBM封装400的背面403超过基座200的凸块附着面204。
在一些实施例中，如图1A，1B和1D所示，每个HBM封装400包括：多个存储器管芯600，一个堆叠在另一个的顶上。每个HBM封装400中的存储器管芯600可以通过倒装芯片技术装配。每个HBM封装400具有前表面401和相对于该前表面的背面403。另外，每个存储器管芯600包括：TSV(Through Silicon Via，硅通孔)互连结构602和导电结构604。其中，TSV互连结构602设置为穿过对应的存储器管芯600。导电结构604位于对应的存储器管芯600的前表面上。例如，存储器管芯600之一可以堆叠在另一存储器管芯600的背面403上，并且通过TSV互连结构602和存储器管芯600之一的导电结构604电性连接至另一存储器管芯600。在一些实施例中，每个HBM封装400包括：TSV互连结构602而非RDL结构。另外，每个HBM封装400可以进一步包括：控制器管芯610，电性耦接至导电结构452。存储器管芯600可以堆叠在控制器管芯610上，并且电性耦接至控制器管芯610。例如，每个HBM封装400的控制器管芯610可以用来控制对应的存储器管芯600。需要注意的是，存储器管芯600的数量不限制于公开的实施例。
在一些实施例中，如图1A和1B所示，每个HBM封装400包括：多个导电结构452，接触RDL结构316的凸块附着面315并且电性耦接至RDL结构316。例如，SOC封装300A的每个导电结构322具有第一直径D1，HBM封装400的每一个导电结构452具有第二直径D2，其中第二直径D2小于第一直径D1。另外，每个HBM封装400的导电结构452的直径也可以设置为小于第一直径D1和第二直径D2。因此，导电结构452也可以作为微凸块。
在一些实施例中，如图1A和1B所示，SOC封装300A的导电结构322以第一间距P1重复布置，并且每个HBM封装400的导电结构452以第二间距P2布置，其中第二间距P2小于第一间距P1。另外，每个HBM封装400的导电结构452可以以小于第一间距P1和第二间距P2的间距来布置。
在一些实施例中，如图1B所示，底部填充材料330可以通过回流工艺引入SOC封装300A，HBM封装400和基座200之间的间隙。底部填充材料330可以用于补偿基座200，SOC封装300A和HBM封装400之间的不同的CTE(Thermal Expansion，热膨胀)系数。在一些实施例中，SOC封装300A的导电结构322以及每个HBM封装400的导电结构452可以被底部填充材料330围绕。在一些实施例中，底部填充材料330可以为CUF(Capillary Underfill，毛细底部填充材料)、MUF(Molded Underfill，模塑底部填充材料)或者他们的组合。
在一些实施例中，如图1B所示，SOC封装300A进一步包括：散热结构700A，位于SOC封装300A和HBM封装400上方。散热结构700A可以通过热界面材料704(或者热膏)连接至基座的封装附着面202，以形成容纳SOC封装300A和HBM封装400的空间720A。例如，散热结构700A通过热界面材料704连接至SOC封装300A的背面303。另外，散热结构700A的边界711A可以对齐基座200的边界211，如图1B所示。
在一些实施例中，如图1B所示，散热结构700A包括：位于基座200的上方的环形部分702，以及位于该环形部分702上方的覆盖部分706。例如，散热结构700A的环形部分702连接基座200的封装附着面202的没有被SOC封装300A和HBM封装400覆盖的部分。散热结构700A的环形部分702围绕SOC封装300A和HBM封装400。另外，散热结构700A的覆盖部分706覆盖SOC封装300A和HBM封装400。散热结构700A的覆盖部分706通过热界面材料704连接至环形部分702。覆盖部分706的内表面722A通过热界面材料704连接至SOC封装300A。因此，SOC封装300A和HBM封装400产生的热可以更容易地扩散至散热结构700A。
在一些实施例中，散热结构700A的环形部分702和覆盖部分706可以由金属材料形成，例如铜、不锈钢或者其他合适的金属材料。在一些实施例中，热界面材料704主要由基质材料(matrix material)和大体积分数的电绝缘但是导热的填料构成。例如，基质材料可以包括：环氧树脂、硅树脂、尿烷、丙烯酸酯或者其他适合的基质材料。另外，胶带(adhesivetapes)也适合于作为基质材料。例如，该填料包括：氧化铝、氮化硼、氧化锌或者他们的组合。
图1C为图1A所示的半导体封装结构500B沿线A-A’的平面示意图。以下实施例的元件，有相同或者相似于先前参考图1A和1B已描述了的，出于简洁而不再重复。半导体封装结构500B与半导体封装结构500A之间的不同在于：半导体封装结构500B包含整体的(one-piece)散热结构700B，即一体式(all-in-one)散热结构。例如，散热结构700B在剖面示意图中具有颠倒的U形，如图1C所示。散热结构700B的底面721通过热界面材料704连接至基座200的封装附着面202上未被SOC封装300A和HBM封装400覆盖的部分。散热结构700B和基座200共同形成容纳SOC封装300A和HBM封装400的空间720B。另外，散热结构700B的内表面722B通过热界面材料704连接至SOC封装300A的背面303。另外，散热结构700B的边界711B对齐基座200的边界211，如图1C所示。另外，散热结构700B的内表面722B通过热界面材料704连接至SOC封装300A，以有助于扩散由SOC封装300A和HBM封装400所产生的热。
在一些实施例中，半导体封装结构(如半导体封装结构500A和500B)的HBM封装400直接位于逻辑管芯302的一部分的下方。HBM封装400可以位于SOC封装300A和基座200之间的间隙之间。另外，HBM封装400可以嵌入于基座200的一部分中，或者穿过基座200以降低半导体封装结构的高度。在一些实施例中，相同HBM封装400中的DRAM管芯600和SOC封装300A的逻辑管芯302可以彼此重叠并且分别连接至RDL结构316的凸块附着面315和管芯附着面313。因此，可以进一步降低SOC封装300A和HBM封装400之间沿大致平行于RDL的管芯附着面313(或凸块附着面315)的传输路径。半导体封装结构500A/500B在网络应用中具有低阻抗。
在一些实施例中，半导体封装结构(如半导体封装结构500A和500B)包括：散热结构(如散热结构700A和700B)，位于SOC封装300A和HBM封装400上方并且连接至基座200以形成容纳SOC封装300A和HBM封装400的空间(如空间720A和720B)。散热结构700A例如由环形部分702和覆盖部分706组成。例如，散热结构700B可以为一整体结构。另外，散热结构可以通过热界面材料704连接至SOC封装300A，以有助于扩散由SOC封装300A和HBM封装400产生的热。
图2A为根据本发明一些实施例的半导体封装结构500C(或500D，500E，500F)的平面示意图，其中该半导体封装结构500C/500D/500E/500F包括：SOC封装300B(或300C)以及堆叠于其上的四个HBM封装400。图2A也示出了SOC封装、HBM封装以及基座的布置。在图2A中，省略了散热结构。图2B为图2A所示的半导体封装结构500C沿线A-A’的剖面示意图。以下实施例中描述的元件，有相同或者类似于先前参考图1A～1D已描述了的，出于简洁而不再重复。
在一些实施例中，如图2A及2B所示，半导体封装结构500C与半导体封装结构500A(图1A～1B)之间的不同在于：半导体封装结构500C包括：SOC封装300B。在一些实施例中，该SOC封装300B包括：第一逻辑管芯302A与紧邻该第一逻辑管芯302A的第二逻辑管芯302B。该第一逻辑管芯302A与第二逻辑管芯302B可以通过导电迹线360彼此电性耦接。另外，第一逻辑管芯302A与第二逻辑管芯302B可以电性耦接至RDL结构316。例如，根据提高单个逻辑管芯的制造产量的职责，将逻辑管芯302(第1A～1C图)分为第一逻辑管芯302A与第二逻辑管芯302B。在一些实施例中，四个HBM封装400垂直堆叠在第一逻辑管芯302A与第二逻辑管芯302B中的任一个上，如第2A和2B图所示。需要注意的是，半导体封装结构500C(或500D，500E，500F)中整合的HBM封装400的数量不限制于本实施例。
在一些实施例中，如图2A和2B所示，SOC封装300B进一步包括：RDL结构326，位于模塑料312的上方并且通过模塑料312与RDL结构316分开。另外，RDL结构316和RDL结构326分别与模塑料312的相对表面333和335接触。在一些实施例中，RDL结构326包括：导电迹线338，IMD层337和RDL接触垫340。另外，导电迹线(图2A)位于RDL结构326中并且电性连接至第一逻辑管芯302A和第二逻辑管芯302B。
在一些实施例中，如图2A及2B所示，SOC封装300B进一步包括：通孔314，穿过模塑料312。因此，通孔314可以作为TPV(Through Package Vias，穿过封装的通孔)。通孔314可以设置为围绕SOC封装300B的第一逻辑管芯302A和第二逻辑管芯302B。另外，每个通孔314均具有分别接触并且电性耦接至RDL结构316和326的两端。
在一些实施例中，如图2A和2B所示，第一逻辑管芯302A和第二逻辑管芯302B以及HBM封装400均位于RDL结构316的管芯附着面的上方。HBM封装400可以通过RDL结构316，通孔314和RDL结构326在空间上远离SOC封装300B的导电结构332。另外，RDL结构316位于SOC封装300B的导电结构322和通孔314之间。RDL结构326位于HBM封装400和通孔314之间。因此，第一逻辑管芯302A与第二逻辑管芯302B的接垫304面向基座200。另外，HBM封装400的导电结构452和模塑料312分别接触RDL结构326的相对表面。因此，HBM封装400通过RDL结构326和通孔314电性耦接至RDL结构316。
在一些实施例中，如图2B所示，散热结构700A的环形部分702围绕SOC封装300B。另外，散热结构700A的覆盖部分706覆盖SOC封装300B和HBM封装400。覆盖部分706的内表面722A通过热界面材料704连接至SOC封装300B和HBM封装400。因此，SOC封装300B和HBM封装400产生的热可以更容易地扩散至散热结构700A。
图2C为图2A所示的半导体封装结构500D沿线A-A’的剖面示意图。以下实施例中的元件，有相同或者类似于先前参考图1A～1C，2A及2B已描述了的，出于简洁而不再重复。半导体封装结构500D和500C之间的不同在于：半导体封装结构500D包括：整体的散热结构700B。散热结构700B的内表面722B通过热界面材料704连接至SOC封装300B和HBM封装400。另外，散热结构700B的布置相同或者类似于先前参考图1C的描述，因此出于简洁而不再重复。
图2D为图2A所示的半导体封装结构500E沿线A-A’的剖面示意图。以下实施例描述的元件，有相同或者类似于先前参考图1A～1C和2A～2C已描述了的，出于简洁而不再重复。
在一些实施例中，如图2A和2D所示，半导体封装结构500E与半导体封装结构500C(图2A～2B)之间的不同在于：半导体封装结构500E的SOC封装300C中的逻辑管芯的前表面背向基座200。在SOC封装300C中，RDL结构326位于导电结构322和通孔314之间，RDL结构316位于HBM封装400和通孔314之间。因此，第一逻辑管芯302A和第二逻辑管芯302B位于RDL结构316的管芯附着面313上，以及HBM封装(连同导电结构452)位于RDL结构316的凸块附着面315上。因为HBM封装400位于SOC封装300C的上方，因此HBM封装400通过SOC封装300C与基座分开。第一逻辑管芯302A和第二逻辑管芯302C的接垫304背向基座200。另外，SOC封装300C的导电结构322位于RDL结构326上，并且第一逻辑管芯302A和第二逻辑管芯302B通过RDL结构316、通孔314和RDL结构326耦接至导电结构322。
在一些实施例中，如图2D所示，散热结构700A的环形部分702围绕SOC封装300C。另外，散热结构700A的覆盖部分706覆盖SOC封装300C和HBM封装400。散热结构700A的覆盖部分706的内表面722A通过热界面材料704连接至SOC封装300C和HBM封装400。因此，SOC封装300C和HBM封装400产生的热能够更容易地扩散至散热结构700A。
图2E为图2A所示的半导体封装结构500F沿线A-A’的剖面示意图。以下实施例描述的元件，有相同或者类似于先前参考图1A～1C以及2A～2D已描述了的，出于简洁而不再重复。半导体封装结构500F与500E之间的不同在于：半导体封装结构500F包括：一整体的散热结构700B。散热结构700B的内表面722B通过热界面材料704连接至SOC封装300C和HBM封装400。另外，散热结构700B的布置相同或者类似于先前参考图1C和2C所描述的情况，因此出于简洁而不再重复。
如前所述，半导体封装结构(如半导体封装结构500C～500F)的SOC封装(如SOC封装300B和300C)包括：两个RDL结构(如RDL结构316和326)，分别设置在模塑料312的相对表面。因此，HBM封装400的导电结构452和SOC封装的导电结构332可以接触不同的RDL结构316和326。另外，SOC封装的逻辑管芯(如第一和第二逻辑管芯302A、302B)的接垫304可以面向或者背向基座200，以增加设计灵活性。
本发明的各实施例提供了半导体封装结构500A～500F。半导体封装结构500A～500F可以提供多个堆叠在SOC封装(如SOC封装300A～300C)的HBM封装(如HBM封装400)。HBM封装可以由三维堆叠的具有TSV互连结构的DRMA管芯构成，其中TSV互连结构穿过DRAM管芯。在一些实施例中，HBM封装可以安装在SOC封装的RDL结构的凸块附着面上并且嵌入在基座中。SOC封装和HBM封装之间的横向传输路径(大致平行于RDL结构的管芯附着面(或凸块附着面))可以进一步降低。在一些实施例中，半导体封装结构的SOC封装可以包括：两个RDL结构，分别设置在模塑料的相对表面，以有助于其上的HBM封装的接合，以及通过穿过模塑料的TPV(如通孔314)电性连接至逻辑管芯。因此，半导体封装结构500A～500F在网络应用中，可以满足低阻抗、高带宽和快速转变的要求。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (14)

1.一种半导体封装结构，其特征在于，包括：第一半导体封装和位于该第一半导体封装的一部分上的第二半导体封装；
其中，该第一半导体封装，包括：第一重分布层结构，具有第一表面以及相对于该第一表面的第二表面；第一半导体管芯，电性耦接至该第一重分布层结构；以及模塑料，设置在该第一表面上并且围绕该第一半导体管芯；
其中，该第二半导体封装包括：第一和第二存储器管芯，其中该第二存储器管芯垂直地堆叠于该第一存储器管芯上，并且该第二存储器管芯通过穿过其的硅通孔互连结构电性耦接至该第一存储器管芯。
2.如权利要求1所述的半导体封装结构，其特征在于，该第一半导体封装进一步包括：第一导电结构，设置在该第一重分布层结构的该第二表面上；该第二半导体封装进一步包括：第二导电结构，电性耦接至该第一半导体封装。
3.如权利要求2所述的半导体封装结构，其特征在于，该第一导电结构具有第一直径，该第二导电结构具有小于该第一直径的第二直径，且该第二直径小于该第一直径；
或者，该第一导电结构以第一间距重复地设置，以及该第二导电结构以小于该第一间距的第二间距重复地设置。
4.如权利要求2所述的半导体封装结构，其特征在于，进一步包括：基座，该第一半导体封装和该第二半导体封装通过该第一导电结构安装于该基座上。
5.如权利要求4所述的半导体封装结构，其特征在于，该第二半导体封装嵌入于该基座中，并且该第一和第二导电结构均接触该第一重分布层结构的该第二表面。
6.如权利要求4所述的半导体封装结构，其特征在于，进一步包括：
散热结构，位于该第一半导体封装和该第二半导体封装的上方，其中该散热结构连接至该基座以形成用于容纳该第一半导体封装和该第二半导体封装的空间。
7.如权利要求6所述的半导体封装结构，其特征在于，该散热结构包括：环形部分和覆盖部分，其中该环形部分连接至该基座并且围绕该第一半导体封装，该覆盖部分覆盖该第一半导体封装和该第二半导体封装并且连接至该环形部分。
8.如权利要求1所述的半导体封装结构，其特征在于，该第一半导体封装进一步包括：第二半导体管芯，与所述第一半导体管芯并排设置并且电性耦接至该第一重分布层结构。
9.如权利要求1所述的半导体封装结构，其特征在于，在平面视图中，该模塑料的边界围绕该第二半导体封装的边界。
10.如权利要求2所述的半导体封装结构，其特征在于，该第二半导体封装的该第二导电结构通过穿过该模塑料的第一通孔电性耦接至该第一半导体封装的该第一重分布层结构。
11.如权利要求10所述的半导体封装结构，其特征在于，该第一半导体封装进一步包括：第二重分布层结构，位于该模塑料上并且通过该模塑料与该第一重分布层结构隔开，其中该第二半导体封装设置在该第二重分布层结构上，并且该第二导电结构通过该第二重分布层结构以电性耦接至该第一通孔。
12.如权利要求11所述的半导体封装结构，其特征在于，该第一半导体管芯的接垫面向该第一重分布层结构，并且该接垫通过直接设置于其上的第二通孔电性耦接至该第一重分布层结构，其中该第二通孔位于该第一半导体管芯与该第一重分布层结构的该第一表面之间。
13.如权利要求11所述的半导体封装结构，其特征在于，该第一半导体管芯的接垫背向该第一重分布层结构，并且该接垫电性耦接至该第二重分布层结构，并且该接垫通过该第二重分布层结构以及穿过该模塑料的第三通孔电性耦接至该第一重分布层结构。
14.如权利要求1所述的半导体封装结构，其特征在于，该第一半导体管芯为逻辑管芯，该第一半导体封装为片上系统封装，该第二半导体封装为高带宽存储器封装。
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