CN113937073A - 半导体封装件 - Google Patents
半导体封装件 Download PDFInfo
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- CN113937073A CN113937073A CN202110383497.XA CN202110383497A CN113937073A CN 113937073 A CN113937073 A CN 113937073A CN 202110383497 A CN202110383497 A CN 202110383497A CN 113937073 A CN113937073 A CN 113937073A
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Abstract
一种半导体封装件包括:第一半导体芯片,所述第一半导体芯片包括半导体基板和位于所述半导体基板的顶表面上的再分布图案,所述再分布图案具有暴露所述再分布图案的内侧壁的孔;第二半导体芯片,所述第二半导体芯片位于所述第一半导体芯片的顶表面上;和凸块结构,所述凸块结构设置在所述第一半导体芯片与所述第二半导体芯片之间。所述凸块结构设置在所述孔中,并且与所述再分布图案的所述内侧壁接触。
Description
相关申请的交叉引用
本专利申请要求于2020年7月13日在韩国知识产权局提交的韩国专利申请No.10-2020-0086234的优先权,其公开内容通过引用整体合并于此。
技术领域
本发明构思的实施例涉及半导体封装件,并且更具体地,涉及包括凸块结构的半导体封装件。
背景技术
已经研发出堆叠半导体芯片的技术以提高半导体器件的集成密度和性能。例如,在多芯片封装技术中,可以将多个半导体芯片安装在单个半导体封装件中。在系统级封装技术中,不同种类的半导体芯片可以堆叠在能够操作为一个系统的单个半导体封装件中。为了使电子设备小型化,可能需要减小半导体封装件的厚度。另外,可能需要半导体封装件具有能够在半导体封装件的运行中有效地散发从堆叠的半导体芯片产生的热的散热性质。
发明内容
本发明构思的实施例可以提供一种小型化的半导体封装件。
本发明构思的实施例还可以提供一种能够减小堆叠的半导体芯片之间的距离并改善热性质的半导体封装件。
在一方面,半导体封装件可以包括:第一半导体芯片,所述第一半导体芯片包括半导体基板和位于所述半导体基板的顶表面上的再分布图案,所述再分布图案具有暴露所述再分布图案的内侧壁的孔;第二半导体芯片,所述第二半导体芯片位于所述第一半导体芯片的顶表面上;和凸块结构,所述凸块结构设置在所述第一半导体芯片与所述第二半导体芯片之间。所述凸块结构可以设置在所述孔中,并且可以与所述再分布图案的所述内侧壁接触。
在一方面,半导体封装件可以包括:第一半导体芯片,所述第一半导体芯片包括半导体基板和设置在所述半导体基板的顶表面上的再分布图案,所述再分布图案具有孔;第二半导体芯片,所述第二半导体芯片位于所述第一半导体芯片的顶表面上;焊料图案,所述焊料图案设置在所述孔中,以与所述再分布图案的内侧壁接触;和柱图案,所述柱图案设置在所述焊料图案与所述第二半导体芯片之间。
在一方面,半导体封装件可以包括:封装基板;第一半导体芯片,所述第一半导体芯片安装在所述封装基板上;第二半导体芯片,所述第二半导体芯片设置在所述第一半导体芯片的顶表面上;和凸块结构,所述凸块结构设置在所述第一半导体芯片与所述第二半导体芯片之间。所述第一半导体芯片可以包括:第一半导体基板;第一电路层,所述第一电路层设置在所述第一半导体基板的底表面上,并且包括第一集成电路;第一贯穿结构,所述第一贯穿结构设置在所述第一半导体基板中;第一再分布图案,所述第一再分布图案设置在所述第一半导体基板的顶表面上,并且连接到所述第一贯穿结构;第一保护层,所述第一保护层位于所述第一再分布图案的顶表面上;和上绝缘层,所述上绝缘层位于所述第一半导体基板与所述第一再分布图案之间。所述第二半导体芯片可以包括:第二半导体基板;第二电路层,所述第二电路层设置在所述第二半导体基板的底表面上,并且包括第二集成电路;和芯片焊盘,所述芯片焊盘设置在所述第二电路层的底表面上,并且电连接到所述第二集成电路。所述第一再分布图案可以具有暴露所述第一再分布图案的内侧壁的孔。所述凸块结构可以包括:焊料图案,所述焊料图案设置在所述孔中,以与所述第一再分布图案的所述内侧壁接触;和柱图案,所述柱图案位于所述焊料图案与所述第二半导体芯片的所述芯片焊盘之间。
附图说明
鉴于附图和随附的详细描述,本发明构思将变得更加容易理解。
图1A是示出根据本发明构思的示例实施例的半导体封装件的截面图。
图1B是图1A的区域“I”的放大图。
图1C是示出根据本发明构思的示例实施例的凸块结构、第一再分布图案和贯穿结构的布置的俯视图。
图1D是图1A的区域“II”的放大图,并且对应于沿着图1C的线III-III'截取的截面图。
图1E是示出电连接第一半导体芯片和第二半导体芯片的工艺的截面图。
图2A是示出根据本发明构思的示例实施例的凸块结构和第一再分布图案的视图。
图2B是示出根据本发明构思的示例实施例的第一再分布图案和第一保护层的视图。
图2C是示出根据本发明构思的示例实施例的半导体封装件的视图。
图2D是示出根据本发明构思的示例实施例的凸块结构和第一贯穿结构的电连接的视图。
图3是示出根据本发明构思的示例实施例的半导体封装件的截面图。
图4A是示出根据本发明构思的示例实施例的半导体封装件的截面图。
图4B是图4A的区域“IV”的放大图。
具体实施方式
在整个说明书中,相同的附图标记或相同的参考标记可以表示相同的元件或组件。
在下文中将描述根据本发明构思的示例实施例的半导体封装件。
图1A是示出根据本发明构思的示例实施例的半导体封装件的截面图。图1B是图1A的区域“I”的放大图。图1C是示出根据本发明构思的示例实施例的凸块结构、第一再分布图案和贯穿结构的布置的俯视图。图1D是图1A的区域“II”的放大图,并且对应于沿着图1C的线III-III'截取的截面图。
参照图1A、图1B、图1C和图1D,半导体封装件可以包括第一半导体芯片100、第二半导体芯片200和凸块结构300。半导体封装件还可以包括封装基板900和外部端子950。封装基板900可以包括绝缘基体层910、基板焊盘920和内部互连线930。绝缘基体层910可以包括单层或多层。基板焊盘920可以在封装基板900的顶表面处暴露。基板焊盘920的顶表面可以与封装基板900的顶表面共面。否则,基板焊盘920的顶表面可以设置在与封装基板900的顶表面不同的水平高度处。内部互连线930可以设置在绝缘基体层910中,并且可以连接到基板焊盘920。在本说明书中,将理解的是,当组件被称为“电连接”到另一组件时,它可以直接连接到其他组件,或者可以存在中间组件。在本说明书中,将理解的是,当组件被称为电连接到封装基板900时,它可以电连接到内部互连线930。基板焊盘920和内部互连线930可以包括金属,例如铜、铝、钨和/或钛。例如,封装基板900可以是具有电路图案的印刷电路板。或者,可以将再分布层用作封装基板900。当将再分布层用作封装基板900时,绝缘基体层910可以包括光敏聚合物或可光成像电介质(PID)材料。当将再分布层用作封装基板900时,内部互连线930可以包括晶种层和位于晶种层上的金属层。
外部端子950可以设置在封装基板900的底表面上,并且可以连接到内部互连线930。例如,外部端子950可以与在封装基板900的底表面处暴露的下基板焊盘940接触。外部电信号可以通过外部端子950传输到内部互连线930。外部端子950可以包括焊料球。外部端子950可以包括诸如焊料材料的金属。焊料材料可以包括锡(Sn)、银(Ag)、锌(Zn)和/或其任何合金。
除非上下文另外指出,否则本文所使用的术语“接触”或“与……接触”是指直接连接(即,触及)。当涉及到方向、布局、位置、形状、尺寸、量或其他度量时,如本文所使用的诸如“相同”、“相等”、“平面”或“共面”的术语不一定表示完全相同的方向、布局、位置、形状、尺寸、量或其他度量,而是旨在包含在例如由于制造工艺而可能发生的可接受的变化内的几乎相同的方向、布局、位置、形状、尺寸、量或其他度量。除非上下文或其他陈述另有指示,否则在本文中可以使用术语“基本上”来强调这种含义。例如,被描述为“基本上相同”、“基本上相等”或“基本上平面”的项可以完全相同、相等或平面,或者可以在例如由于制造工艺而可能发生的可接受的变化内的相同、相等或平面。当涉及到方向、布局、位置、形状、尺寸、量或其他度量时,如本文所使用的诸如“相同”、“相等”、“平面”或“共面”的术语不一定表示完全相同的方向、布局、位置、形状、尺寸、量或其他度量,而是旨在包含在例如由于制造工艺而可能发生的可接受的变化内的几乎相同的方向、布局、位置、形状、尺寸、量或其他度量。除非上下文或其他陈述另有指示,否则在本文中可以使用术语“基本上”来强调这种含义。例如,被描述为“基本上相同”、“基本上相等”或“基本上平面”的项可以完全相同、相等或平面,或者可以在例如由于制造工艺而可能发生的可接受的变化内的相同、相等或平面。
第一半导体芯片100可以安装在封装基板900的顶表面上。第一半导体芯片100可以包括第一半导体基板110、第一电路层120、第一芯片焊盘150、第一贯穿基板140、第一再分布图案160和第一保护层180。例如,第一半导体基板110可以包括诸如硅、锗或硅锗的半导体材料。第一半导体基板110可以具有彼此相对的顶表面110a和底表面110b。
第一电路层120可以设置在第一半导体基板110的底表面110b上。第一电路层120可以包括第一绝缘层121、第一集成电路123和第一互连结构125,如图1B所示。第一集成电路123可以设置在第一半导体基板110的底表面110b上。例如,第一集成电路123可以包括晶体管。第一集成电路123可以包括逻辑电路、存储电路和/或它们的组合。第一绝缘层121可以设置在第一半导体基板110的底表面110b上,并且可以覆盖第一集成电路123。即使在附图中未示出,第一绝缘层121也可以包括多个堆叠的层。第一绝缘层121可以包括含硅绝缘材料。例如,含硅绝缘材料可以包括氧化硅、氮化硅、氮氧化硅和/或原硅酸四乙酯。第一互连结构125可以设置在第一绝缘层121中。第一互连结构125可以电连接到第一集成电路123。在本说明书中,可以理解的是,当组件被称为电连接到半导体芯片时,它可以电连接到半导体芯片的集成电路。第一互连结构125可以包括互连图案和连接到该互连图案的通路图案。互连图案可以具有在平行于第一半导体基板110的底表面110b的方向上延伸的长轴。通路图案的长轴可以平行于与第一半导体基板110的底表面110b相交的方向。通路图案可以设置在多个互连图案之间,并且可以连接到互连图案。每个互连图案的宽度可以大于直接连接到其的通路图案的宽度。第一互连结构125可以包括诸如铜、铝、钛或钨的金属。
第一芯片焊盘150可以在第一半导体芯片100的底表面处暴露。第一芯片焊盘150可以设置在第一电路层120的底表面上。第一芯片焊盘150可以通过第一互连结构125电连接到第一集成电路123。第一芯片焊盘150可以包括与第一互连结构125的材料不同的材料。第一芯片焊盘150可以包括诸如铝的金属。第一芯片焊盘150可以是多个芯片焊盘150。
第一半导体芯片100还可以包括第一下绝缘图案130,如图1B所示。第一下绝缘图案130可以设置在第一绝缘层121的底表面上,并且可以覆盖第一芯片焊盘150的边缘部分。例如,第一下绝缘图案130可以接触第一芯片焊盘的侧表面以及每个第一芯片焊盘150的底表面的边缘部分。第一下绝缘图案130可以暴露第一芯片焊盘150的至少一部分。例如,第一下绝缘图案130可以暴露每个第一芯片焊盘150的中央部分。第一下绝缘图案130可以包括绝缘聚合物或硅基绝缘材料。
半导体封装件还可以包括接合凸块350。如图1A所示,接合凸块350可以设置在封装基板900与第一半导体芯片100之间,并且可以电连接到封装基板900和第一半导体芯片100。例如,接合凸块350可以连接到基板焊盘920和第一芯片焊盘150。接合凸块350可以接触基板焊盘920的顶表面和第一芯片焊盘150的底表面。接合凸块350可以包括焊料球、凸块或柱。接合凸块350可以包括导电材料。接合凸块350可以是多个接合凸块350。
第一贯穿结构140可以设置在第一半导体基板110中。第一贯穿结构140可以穿透第一半导体基板110的顶表面110a和底表面110b。第一贯穿结构140还可以穿透第一电路层120的至少一部分。例如,第一贯穿结构140还可以穿透第一绝缘层121的上部,如图1B所示。第一贯穿结构140还可以通过第一互连结构125电连接到第一芯片焊盘150和第一集成电路123中的至少一者。第一贯穿结构140可以是多个第一贯穿结构140,并且每个第一贯穿结构140可以电连接到至少一个相应的第一芯片焊盘150。
在图1A和图1D中,第一再分布图案160可以设置在第一半导体基板110的顶表面110a上。在本说明书中,可以理解的是,当组件被称为在另一组件“上”时,它可以直接在其他组件上,或者可以存在中间组件。例如,在一些实施例中,第一上绝缘层170还可以设置在第一半导体基板110的顶表面110a与第一再分布图案160之间。第一上绝缘层170可以包括含硅绝缘材料。即使在附图中未示出,第一上绝缘层170也可以包括多个堆叠的层。如果第一再分布图案160与第一半导体基板110的顶表面110a直接接触,则第一再分布图案160与第一半导体基板110之间的接合强度可能相对弱。然而,根据实施例,可以通过第一上绝缘层170将第一再分布图案160稳定地固定到第一半导体基板110。
第一再分布图案160可以覆盖第一贯穿结构140。例如,第一再分布图案160的一个端部可以设置在第一贯穿结构140的顶表面上,并且可以与第一贯穿结构140接触。第一再分布图案160可以电连接到第一贯穿结构140。因此,第一再分布图案160可以通过第一贯穿结构140电连接到第一集成电路123和封装基板900。
如图1D所示,第一再分布图案160可以具有第一孔169。第一孔169可以穿透第一再分布图案160的顶表面,并且可以暴露第一再分布图案160的内侧壁160c。第一孔169还可以穿透第一再分布图案160的底表面以暴露第一上绝缘层170或第一半导体基板110。第一孔169可以不与第一贯穿结构140垂直交叠。在本说明书中,术语“垂直”可以表示“垂直于第一半导体基板110的顶表面110a”。像图1C所示,当在俯视图中观察时,第一孔169可以与第一贯穿结构140间隔开。当在俯视图中观察时,第一孔169可以具有圆角四边形形状。第一孔169的平面形状可以被不同地修改。例如,当在俯视图中观察时,第一孔169可以具有八边形形状或圆形形状。
第一再分布图案160可以包括晶种图案161和导电图案162。例如,晶种图案161可以包括钛或铜中的至少一者。第一再分布图案160的底表面可以表示晶种图案161的底表面。导电图案162可以设置在晶种图案161上,并且可以与晶种图案161的顶表面接触。导电图案162可以包括诸如铜、镍或其任何合金的金属。导电图案162可以通过使用晶种图案161作为电极的电镀工艺来形成。导电图案162的厚度可以大于晶种图案161的厚度。厚度可以指在垂直于第一半导体基板110的顶表面110a的方向上测量的厚度或高度。再分布图案160的顶表面可以指导电图案162的顶表面。为了图示的简洁和方便起见,第一再分布图案160的晶种图案161和导电图案162没有在除图1D之外的其他附图中分别示出。然而,在其他附图中,第一再分布图案160可以包括晶种图案161和导电图案162。
第一保护层180可以设置在第一半导体基板110的顶表面110a上。例如,第一保护层180可以覆盖第一再分布图案160的顶表面和外侧壁以及第一上绝缘层170的顶表面。第一保护层180可以接触第一再分布图案160的顶表面和外侧壁以及第一上绝缘层170的顶表面。第一保护层180可以是有机绝缘层。例如,第一保护层180可以包括光敏聚合物或可光成像电介质材料。例如,光敏聚合物或可光成像电介质材料可以包括光敏聚酰亚胺、聚苯并恶唑、酚基聚合物或苯并环丁烯基聚合物中的至少一种。第一保护层180可以不延伸到第一再分布图案160的第一孔169中。第一保护层180可以不覆盖第一再分布图案160的内侧壁160c。第一保护层180可以具有第一开口189。第一开口189可以穿透第一保护层180的顶表面180a和底表面。第一开口189可以连接到第一孔169。第一开口189可以暴露第一保护层的内侧壁180c。第一保护层180的内侧壁180c可以与第一再分布图案160的内侧壁160c共面。
第二半导体芯片200可以设置在第一半导体芯片100上。第二半导体芯片200的种类可以与第一半导体芯片100的种类不同。例如,第一半导体芯片100可以是逻辑芯片,并且第二半导体芯片200可以是存储芯片。或者,第二半导体芯片200的种类可以与第一半导体芯片100的种类相同。例如,第一半导体芯片100和第二半导体芯片200均可以是存储芯片。如图1A所示,第二半导体芯片200的宽度可以等于第一半导体芯片100的宽度。或者,第二半导体芯片200的宽度可以与第一半导体芯片100的宽度不同。
第二半导体芯片200可以包括第二半导体基板210、第二电路层220和第二芯片焊盘250。第二半导体基板210可以包括作为第一半导体基板110的示例描述的材料中的至少一种。第二电路层220可以设置在第二半导体基板210的底表面210b上。第二电路层220可以包括第二绝缘层221、第二集成电路223和第二互连结构225,如图1D所示。第二集成电路223可以设置在第二半导体基板210的底表面210b上。例如,第二集成电路223可以包括晶体管。第二集成电路223可以包括逻辑电路、存储电路和/或它们的组合。第二绝缘层221可以设置在第二半导体基板210的底表面210b上,并且可以覆盖第二集成电路223。即使在附图中未示出,第二绝缘层221也可以包括多个堆叠的层。第二绝缘层221可以包括含硅绝缘材料。第二互连结构225可以设置在第二绝缘层221中。第二互连结构225可以电连接到第二集成电路223。第二互连结构225可以包括互连图案和连接到互连图案的通路图案。互连图案可以具有在平行于第二半导体基板210的底表面210b的方向上延伸的长轴。通路图案的长轴可以平行于与第二半导体基板210的底表面210b相交的方向。通路图案可以设置在多个互连图案之间,并且可以连接到互连图案。每个互连图案的宽度可以大于直接连接到其的通路图案的宽度。第二互连结构225可以包括诸如铜、铝、钛或钨的金属。
第二芯片焊盘250可以在第二半导体芯片200的底表面处暴露。第二芯片焊盘250可以设置在第二电路层220的底表面上。第二芯片焊盘250可以通过第二互连结构225电连接到第二集成电路223。第二芯片焊盘250可以包括与第二互连结构225的材料不同的材料。例如,第二芯片焊盘250可以包括诸如铝的金属。
第二半导体芯片200还可以包括第二下绝缘图案230。第二下绝缘图案230可以设置在第二电路层220的底表面上,并且可以暴露第二芯片焊盘250。第二下绝缘图案230可以覆盖第二芯片焊盘250的边缘部分。例如,第二下绝缘图案230可以接触第二电路层220的底表面、第二芯片焊盘250的侧表面以及第二芯片焊盘250的底表面的边缘部分。第二下绝缘图案230可以包括硅基绝缘材料或绝缘聚合物。
凸块结构300可以设置在第一半导体芯片100与第二半导体芯片200之间,并且可以电连接到第一半导体芯片100和第二半导体芯片200。凸块结构300可以包括焊料图案310和柱图案320。焊料图案310可以设置在第一再分布图案160的第一孔169中,并且可以覆盖第一再分布图案160的内侧壁160c。例如,焊料图案310可以与第一再分布图案160的内侧壁160c接触。焊料图案310还可以设置在第一保护层180的第一开口189中,并且可以与第一保护层180的内侧壁180c接触。焊料图案310可以包括锡(Sn)、银(Ag)、锌(Zn)和/或其任何合金。焊料图案310的底表面310b可以对应于凸块结构300的底表面。焊料图案310的底表面310b可以被设置在比第一再分布图案160的顶表面低的水平高度处。在本说明书中,术语“水平高度”可以表示垂直的水平高度。可以在垂直于第一半导体基板110的顶表面110a的方向上测量两个表面之间的水平高度差。在一些实施例中,焊料图案310的底表面310b可以与第一再分布图案160的底表面共面。焊料图案310的底表面310b和侧壁的形状可以对应于第一孔169的底表面169b和侧壁的形状。如图1C所示,焊料图案310的平面形状可以对应于第一孔169的平面形状。当在俯视图中观察时,焊料图案310可以具有圆角四边形形状。焊料图案310的平面形状可以进行各种修改。例如,当在俯视图中观察时,焊料图案310可以具有八边形形状或圆形形状。
柱图案320可以设置在焊料图案310与第二半导体芯片200之间。例如,柱图案320可以设置在焊料图案310与第二芯片焊盘250之间,并且可以连接到焊料图案310和第二芯片焊盘250。柱图案320的下部可以被焊料图案310围绕。例如,柱图案320的底表面320b可以与焊料图案310接触。柱图案320的下部的侧壁可以被焊料图案310覆盖。例如,柱图案320的下部的侧壁可以与焊料图案310接触。然而,本发明构思的实施例不限于此。柱图案320的至少一部分可以设置在第一开口189中。例如,柱图案320的底表面320b可以设置在比第一保护层180的顶表面180a低的水平高度处。因此,可以减小凸块结构300的高度A1。柱图案320的宽度可以是基本上一致的。柱图案320的顶表面320a可以对应于凸块结构300的顶表面。柱图案320可以包括诸如铜的导电材料。如图1C所示,当在俯视图中观察时,柱图案320可以具有圆角四边形形状。或者,当在俯视图中观察时,柱图案320可以具有八边形形状或圆形形状。在下文中将描述第一半导体芯片100和第二半导体芯片200与凸块结构300之间的电连接。
图1E是对应于图1A的区域“II”的放大图,以示出电连接第一半导体芯片和第二半导体芯片的工艺。在图1E中,为了图示的简洁和方便,省略了第一集成电路和第一互连结构。
参照图1E,可以准备第二半导体芯片200。如上所述,第二半导体芯片200可以包括第二半导体基板210、第二电路层220、第二芯片焊盘250和第二下绝缘图案230。此时,可以在第二半导体芯片200的第二芯片焊盘250上形成初始凸块结构300P。初始凸块结构300P可以包括柱图案320和初始焊料图案310P。初始焊料图案310P可以具有焊料球形状。例如,初始焊料图案310P的下部可以具有诸如半球的形状。第二半导体芯片200可以以在第一再分布图案160的第一孔169中设置初始焊料图案310P的方式设置在第一半导体芯片100上。可以执行初始焊料图案310P的回流工艺。回流工艺可以在等于或高于初始焊料图案310P的熔点的温度下执行。然而,本发明构思的实施例不限于此。即使初始凸块结构300P的中心轴可能因工艺误差而偏离第一孔169的中心轴,但是由于在第一孔169中设置了初始焊料图案310P,所以在完成回流工艺之后,焊料图案310可以与第一再分布图案160的内侧壁160c良好接触。结果,可以形成图1A至图1D中描述的凸块结构300,并且第一半导体芯片100和第二半导体芯片200可以通过凸块结构300彼此电连接。如图1A所示,凸块结构300可以包括彼此横向间隔开的多个凸块结构300。第一孔169可以包括彼此分离的多个第一孔169。如果省略第一孔169,则在回流工艺中,多个初始焊料图案310P可能具有流动性,并且因此可能彼此接触。在这种情况下,在凸块结构300之间可能发生电短路。然而,根据实施例,第一孔169可以分别物理隔离初始焊料图案310P。由于每个初始焊料图案310P设置在相应一个第一孔169中,因此即使初始焊料图案310P具有流动性,它们也不会彼此接触。因此,可以防止在多个焊料图案310之间发生电短路。结果,可以改善凸块结构300和包括该凸块结构300的半导体封装件的可靠性。
再次参照图1A至图1D,凸块结构300可以通过第一再分布图案160电连接到第一贯穿结构140。由于提供了第一再分布图案160,所以凸块结构300和第一贯穿结构140可以不垂直彼此对齐。因此,可以自由地设计凸块结构300和第一贯穿结构140的布置。
模制层400可以设置在封装基板900的顶表面上,以覆盖第一半导体芯片100和第二半导体芯片200。不同于图1A,在一些实施例中,模制层400可以覆盖第一半导体芯片100和第二半导体芯片200的侧壁,但是可以暴露第二半导体芯片200的顶表面。模制层400可以包括诸如环氧模塑化合物(EMC)的绝缘聚合物。
第一底部填充层410可以设置在封装基板900与第一半导体芯片100之间的第一间隙区域中,以密封或围绕接合凸块350。第一底部填充层410可以包括诸如环氧模塑化合物(EMC)的绝缘聚合物。在一些实施例中,第一底部填充层410可以包括与模制层400的材料不同的材料。
第二底部填充层420可以设置在第一半导体芯片100的顶表面与第二半导体芯片200的底表面之间的第二间隙区域中。第二底部填充层420可以密封或围绕凸块结构300。第二底部填充层420可以覆盖柱图案320的侧壁。第二底部填充层420可以包括诸如环氧模塑化合物(EMC)的绝缘聚合物。然而,第二底部填充层420可以包括与模制层400的材料不同的材料。例如,第二底部填充层420的绝缘聚合物可以具有与模制层400的绝缘聚合物的化学结构、数均分子量、取代基或组成比不同的化学结构、数均分子量、取代基或组成比。
如果省略了第一孔169和第一开口189,则凸块结构300的底表面可以设置在与第一保护层180的顶表面180a相同或比第一保护层180的顶表面180a高的水平高度处。在这种情况下,第一半导体芯片100与第二半导体芯片200之间的距离A2可以等于或大于凸块结构300的高度A1。然而,根据实施例,由于凸块结构300的一部分设置在第一孔169中,所以第一半导体芯片100与第二半导体芯片200之间的距离A2可以小于凸块结构300的高度A1。因此,第一半导体芯片100与第二半导体芯片200之间的距离A2可以减小,并且半导体封装件的高度可以减小。这里,第一半导体芯片100与第二半导体芯片200之间的距离A2可以是第二下绝缘图案230的底表面与设置在第一再分布图案160上的第一保护层180的顶表面180a之间的距离。第一半导体芯片100与第二半导体芯片200之间的距离A2可以基本上等于第二底部填充层420的厚度。第二底部填充层420的厚度可以对应于在设置在第一再分布图案160上的第一保护层180的顶表面180a上设置的第二底部填充层420的厚度。换句话说,可以在与第一再分布图案160垂直交叠的位置处测量第二底部填充层420的厚度。凸块结构300的高度A1可以被定义为柱图案320的顶表面320a与焊料图案310的底表面310b之间的距离。第二底部填充层420的厚度可以小于柱图案320的顶表面320a与焊料图案310的底表面310b之间的距离。
如果凸块结构300的高度A1大于30μm,则半导体封装件的高度可以增加。在一些实施例中,凸块结构300的高度A1可以在大约5μm至大约30μm的范围内。
如果第一半导体芯片100与第二半导体芯片200之间的距离A2大于20μm,则可能难以使半导体封装件小型化。在一些实施例中,第一半导体芯片100与第二半导体芯片200之间的距离A2可以在大约3μm至大约20μm的范围内。因此,可以使半导体封装件进一步小型化。
第一孔169的深度和第一开口189的深度之和可以基本上对应于凸块结构300的高度A1与第一半导体芯片100和第二半导体芯片200之间的距离A2之差。第一孔169的深度与第一开口189的深度之和可以是第一保护层180的顶表面180a与第一孔169的底表面169b之间的水平高度差A3。如果第一保护层180的顶表面180a与第一孔169的底表面169b之间的水平高度差A3小于2μm,则即使在第一孔169中设置凸块结构300,也可能难以充分减小半导体封装件的高度。如果第一保护层180的顶表面180a与第一孔169的底表面169b之间的水平高度差A3大于20μm,则第一再分布图案160和第一保护层180的厚度之和可能太大。在这种情况下,可能难以减小第一半导体芯片100的高度。但是,根据一些实施例,第一保护层180的顶表面180a与第一孔169的底表面169b之间的水平高度差A3可以在大约2μm至大约10μm的范围内。因此,可以减小半导体封装件的高度(或厚度)。
第二底部填充层420可以具有相对低的热导率。例如,第二底部填充层420的热导率可以低于凸块结构300的热导率。特别地,第二底部填充层420的热导率可以低于焊料图案310的热导率和柱图案320的热导率。第二底部填充层420的热导率可以低于第一再分布图案160的热导率、第一贯穿结构140的热导率、第二芯片焊盘250的热导率和第二互连结构225的热导率。随着第二底部填充层420的厚度增加,半导体封装件的散热性质可能劣化。例如,如果第二底部填充层420的厚度大于20μm,则半导体封装件的散热性质可能劣化。然而,根据实施例,由于减小了第二底部填充层420的厚度,所以在半导体封装件的运行中从第一半导体芯片100产生的热可以迅速地释放或散发到外部。第二底部填充层420的厚度可以在大约3μm至大约20μm的范围内。因此,可以改善半导体封装件的热性质。
图2A是示出根据本发明构思的示例实施例的凸块结构和第一再分布图案的视图。图2A是对应于图1A的区域“II”的放大图,并且是对应于图1C的线III-III'的截面图。在下文中,出于说明简洁和方便的目的,将省略对与以上实施例相同的组件和/或特征的描述。
参照图2A,半导体封装件可以包括第一半导体芯片100、第二半导体芯片200和凸块结构300。第一半导体芯片100可以包括第一半导体基板110、第一贯穿结构140、第一上绝缘层170、第一再分布图案160和第一保护层180。第一再分布图案160可以与参照图1A至图1D描述的基本上相同。然而,第一孔169可以穿透第一再分布图案160的顶表面,但是可以不穿透第一再分布图案160的底表面160b。第一孔169的底表面169b可以设置在第一再分布图案160中。第一孔169的底表面169b可以处于比第一再分布图案160的底表面160b高的水平高度处。因此,第一孔169的底表面169b可以暴露第一再分布图案160。第一保护层180的顶表面180a与第一孔169的底表面169b之间的水平高度差A3可以在大约2μm至大约10μm的范围内。
凸块结构300可以包括焊料图案310和柱图案320,并且焊料图案310可以设置在第一再分布图案160的第一孔169中,从而与第一孔169的底表面169b和第一再分布图案160的内侧壁160c接触。例如,焊料图案310的底表面310b和侧壁可以与第一再分布图案160接触。焊料图案310与第一再分布图案160之间的接触区域可以增加,从而焊料图案310可以更好地电连接到第一再分布图案160。焊料图案310的底表面310b可以设置在比第一再分布图案160的底表面160b高的水平高度处。焊料图案310可以与第一上绝缘层170间隔开。
图2B是示出根据本发明构思的示例实施例的第一再分布图案和第一保护层的视图。图2B是对应于图1A的区域“II”的放大图,并且是对应于图1C的线III-III'的截面图。在下文中,出于说明简洁和方便的目的,将省略对与以上实施例相同的组件和/或特征的描述。
参照图2B,半导体封装件可以包括第一半导体芯片100、第二半导体芯片200和凸块结构300。
第一保护层180可以具有第一开口189。第一开口189的宽度可以大于第一孔169的宽度。例如,在第一保护层180的底表面处第一开口189的宽度可以大于在第一再分布图案160的顶表面160a处第一孔169的宽度。因此,第一开口189可以暴露第一再分布图案160的顶表面160a和第一保护层180的内侧壁180c。第一保护层180的内侧壁180c可以不与第一再分布图案160的内侧壁160c对准。第一孔169和第一开口189可以通过不同的工艺形成。
焊料图案310可以填充第一孔169,并且可以与第一再分布图案160的内侧壁160c接触。焊料图案310还可以设置在第一开口189中。焊料图案310可以延伸到第一再分布图案160的暴露的顶表面160a上和第一保护层180的内侧壁180c上。因此,焊料图案310的侧壁可以具有阶梯形状。
图2C是示出根据本发明构思的示例实施例的半导体封装件的视图。图2C是对应于图1A的区域“II”的放大图,并且是对应于图1C的线III-III'的截面图。在下文中,出于说明简洁和方便的目的,将省略对与以上实施例相同的组件和/或特征的描述。
参照图2C,半导体封装件可以包括第一半导体芯片100、第二半导体芯片200和凸块结构300。第一半导体芯片100可以包括第一半导体基板110、第一贯穿结构140、第一上绝缘层170、第一再分布图案160和第一保护层180,并且还可以包括第一下再分布图案163和第一下保护层183。第一半导体基板110、第一贯穿结构140、第一上绝缘层170、第一再分布图案160和第一保护层180可以与参照图1A至图1D描述的基本上相同。然而,第一再分布图案160可以不与第一贯穿结构140直接接触。
第一下再分布图案163可以设置在第一半导体基板110的顶表面110a与第一再分布图案160之间。例如,第一下再分布图案163可以设置在第一上绝缘层170与第一再分布图案160之间。第一下再分布图案163可以设置在第一贯穿结构140上,并且可以与第一贯穿结构140接触。第一下再分布图案163可以包括与第一再分布图案160的材料基本上相同的材料。
第一下保护层183可以设置在第一下再分布图案163和第一上绝缘层170上,以覆盖第一下再分布图案163和第一上绝缘层170。第一下保护层183可以是有机绝缘层。例如,第一下保护层183可以包括光敏聚合物或可光成像电介质材料。第一下保护层183可以包括与第一保护层180的材料相同的材料,并且第一保护层180与第一下保护层183之间的界面可以不可见或不明显。然而,本发明构思的实施例不限于此。
导电图案165可以设置在第一下保护层183中,并且可以穿透第一下保护层183。导电图案165可以设置在第一下再分布图案163上,并且可以连接到第一下再分布图案163。导电图案165可以包括例如金属。
第一再分布图案160可以设置在第一下保护层183和导电图案165上。例如,第一再分布图案160可以接触第一下保护层183和导电图案165的顶表面。第一再分布图案160可以与第一上绝缘层170间隔开。第一再分布图案160可以通过导电图案165和第一下再分布图案163连接到第一贯穿结构140。第一再分布图案160可以具有第一孔169。凸块结构300可以设置在第一孔169中,并且焊料图案310可以与第一再分布图案160的内侧壁160c接触。第一下再分布图案163可以不具有第一孔169。凸块结构300可以与第一下再分布图案163间隔开。
在某些实施例中,第一下再分布图案163可以包括多个堆叠的第一下再分布图案163,并且第一下保护层183可以包括多个堆叠的第一下保护层183。在这种情况下,第一下保护层183可以设置在第一下再分布图案163之间。
图2D是示出根据本发明构思的一些实施例的凸块结构和第一贯穿结构的电连接的视图。图2D是对应于图1A的区域“II”的放大图,并且是对应于图1C的线III-III'的截面图。在下文中,出于说明简洁和方便的目的,将省略对与以上实施例相同的组件和/或特征的描述。
参照图2D,半导体封装件可以包括第一半导体芯片100、第二半导体芯片200和凸块结构300。第一半导体芯片100可以包括第一半导体基板110、第一贯穿结构140、第一上绝缘层170、第一再分布图案160和第一保护层180,并且还可以包括第一下再分布图案163、第一下保护层183和导电图案165。第一贯穿结构140、第一再分布图案160、第一保护层180、第一下再分布图案163、第一下保护层183和导电图案165可以与参照图2C描述的基本上相同。
然而,第一下保护层183可以具有下开口188。下开口188可以穿透第一下保护层183的顶表面和底表面,并且可以连接到第一再分布图案169的第一孔169。第一下再分布图案163可以具有下孔168。下孔168可以穿透第一下再分布图案163的顶表面。下孔168可以通过下开口188连接到第一孔169和第一开口189。
凸块结构300可以设置在第一开口189、第一孔169、下开口188和下孔168中。焊料图案310可以与第一下再分布图案163的内侧壁163c和第一再分布图案160的内侧壁160c接触。焊料图案310可以通过第一再分布图案160和第一下再分布图案163电连接到第一贯穿结构140。焊料图案310还可以覆盖第一下保护层183的内侧壁和第一保护层180的内侧壁。
在图2A至图2D的实施例中,半导体封装件还可以包括如在图1A至图1D的实施例中描述的封装基板900、模制层400、第一底部填充层410和接合凸块350中的至少一者。第一半导体芯片100还可以包括第一电路层120和第一下绝缘图案130。图1A至图1D的实施例、图2A的实施例、图2B的实施例、图2C的实施例和图2D的实施例可以彼此组合。例如,在图2B和图2C中,第一孔169穿透第一再分布图案160的顶表面和底表面。或者,第一孔169可以穿透第一再分布图案160的顶表面,但是可以不穿透第一再分布图案160的底表面。在这种情况下,第一孔169的底表面可以设置在第一再分布图案160中,并且焊料图案310的底表面和侧壁可以与第一再分布图案160接触。
在图2A至图2D的半导体封装件中,凸块结构300的高度、第一半导体芯片100与第二半导体芯片200之间的距离、第二底部填充层420的厚度以及第一保护层180的顶表面与第一孔169的底表面之间的水平高度差可以满足以上在图1A至图1D的实施例中描述的条件。
图3是示出根据本发明构思的示例实施例的半导体封装件的截面图。将参照图3和图1D描述本实施例,并且出于说明简洁和方便的目的,将省略对与以上实施例相同的组件和/或特征的描述。
参照图3,半导体封装件可以包括封装基板900、第一半导体芯片100、多个第二半导体芯片200和多个凸块结构300。半导体封装件还可以包括多个外部端子950、模制层400、第一底部填充层410和多个第二底部填充层420。半导体封装件可以是三维(3D)堆叠封装件。
第一半导体芯片100可以安装在封装基板900上。第一半导体芯片100可以包括第一半导体基板110、第一电路层120、第一下绝缘图案130、第一贯穿结构140、第一再分布图案160和第一保护层180。
多个第二半导体芯片200可以安装在第一半导体芯片100的顶表面上。第二半导体芯片200可以在横向上彼此间隔开。在本说明书中,术语“横向”可以表示“在平行于第一半导体基板110的顶表面110a的方向上”。第二半导体芯片200的种类可以不同于第一半导体芯片100的种类。例如,第二半导体芯片200的输入/输出(I/O)端子的尺寸、功能和/或数目可以不同于第一半导体芯片100的I/O端子的尺寸、功能和/或数目。I/O端子可以是芯片焊盘。在一些实施例中,每个第二半导体芯片200的宽度可以小于第一半导体芯片100的宽度。每个第二半导体芯片200可以执行与第一半导体芯片100的功能不同的功能。例如,第一半导体芯片100可以是逻辑芯片,并且第二半导体芯片200可以是存储芯片。存储芯片可以包括诸如DRAM芯片或SRAM芯片的易失性存储芯片。或者,存储芯片可以包括诸如NAND闪存芯片的非易失性存储芯片。每个第二半导体芯片200可以包括如在图1A至图1D的实施例中描述的第二半导体基板210、第二电路层220和第二芯片焊盘250。第二半导体芯片200还可以包括第二下绝缘图案230。
凸块结构300可以设置在第一半导体芯片100与第二半导体芯片200之间。每个第二半导体芯片200可以通过凸块结构300连接到第一半导体芯片100和封装基板900。每个凸块结构300可以包括焊料图案310和柱图案320。焊料图案310可以设置在第一再分布图案160的第一孔169中,并且可以与第一再分布图案160的内侧壁160c接触。因此,可以使半导体封装件小型化,并且可以改善半导体封装件的热性质。多个柱图案320的节距P1可以小于多个外部端子950的节距P2。
第二底部填充层420可以分别设置在第一半导体芯片100与第二半导体芯片200之间的第二间隙区域中,以密封或围绕凸块结构300。
模制层400可以覆盖第一半导体芯片100和第二半导体芯片200的侧壁,但是可以暴露第二半导体芯片200的顶表面。或者,模制层400还可以覆盖第二半导体芯片200的顶表面。
半导体封装件还可以包括散热结构700。散热结构700可以设置在第二半导体芯片200的顶表面和模制层400的顶表面上。在一些实施例中,散热结构700还可以延伸到模制层400的侧壁上。散热结构700可以包括散热器、散热块或热界面材料(TIM)层。散热结构700可以包括例如金属。
图4A是示出根据本发明构思的示例实施例的半导体封装件的截面图。图4B是图4A的区域“IV”的放大图。在下文中,出于说明简洁和方便的目的,将省略对与以上实施例相同的组件和/或特征的描述。
参照图4A和图4B,半导体封装件可以包括封装基板900、外部端子950、内置基板(interposer substrate)800、内置凸块850、芯片堆叠1000、第三半导体芯片500和模制层400。封装基板900可以与参照图1A至图1D描述的基本上相同。多个外部端子950可以设置在封装基板900的底表面上。
内置基板800可以设置在封装基板900上。内置基板800可以包括金属焊盘820和金属互连线830。金属焊盘820可以在内置基板800的顶表面处暴露。金属互连线830可以设置在内置基板800中,并且可以连接到金属焊盘820。在本说明书中,可以理解的是,当组件被称为电连接到内置基板800时,它可以电连接到金属互连线830。金属焊盘820和金属互连线830可以包括诸如铜、铝、钨和/或钛的金属。内置凸块850可以设置在封装基板900与内置基板800之间,并且可以连接到封装基板900和内置基板800。例如,内置凸块850可以连接到基板焊盘920和金属互连线830。每个内置凸块850可以包括焊料球。内置凸块850可以包括诸如焊料材料的金属。
芯片堆叠1000可以安装在内置基板800的顶表面上。芯片堆叠1000可以包括第一半导体芯片100、第二半导体芯片200和多个凸块结构300。第一半导体基板100可以安装在内置基板800的顶表面上。第一半导体芯片100可以包括第一半导体基板110、第一芯片焊盘150、第一电路层120、第一贯穿结构140、第一再分布图案160和第一保护层180。第一半导体芯片100还可以包括第一下绝缘图案130,如图1B所示。接合凸块350可以设置在内置基板800与第一半导体芯片100之间。接合凸块350可以设置在金属焊盘820与第一芯片焊盘150之间,并且可以连接到金属焊盘820和第一芯片焊盘150。
第二半导体芯片200可以设置在第一半导体芯片100的顶表面上。凸块结构300可以设置在第一半导体芯片100与第二半导体芯片200之间。每个凸块结构300可以与上面描述的凸块结构基本上相同。例如,焊料图案310可以设置在第一孔169中,并且可以与第一再分布图案160的内侧壁160c直接接触,如图4B所示。因此,可以减小芯片堆叠1000的高度。
第二半导体芯片200可以包括多个堆叠的第二半导体芯片200。第二半导体芯片200的种类可以不同于第一半导体芯片100的种类。例如,第一半导体芯片100可以是逻辑芯片、缓冲芯片和片上系统(SOC)中的一种,并且第二半导体芯片200可以是逻辑芯片、存储芯片、缓冲芯片和片上系统(SOC)中的另一种。在本说明书中,存储芯片可以包括高带宽存储器(HBM)芯片。例如,第一半导体芯片100可以是逻辑芯片,并且第二半导体芯片200可以是HBM芯片。
在下文中,将详细描述第二半导体芯片200。每个第二半导体芯片200可以包括如在图1A至图1D的实施例中描述的第二半导体基板210、第二电路层220和第二芯片焊盘250。每个第二半导体芯片200还可以包括第二贯穿结构240、第二再分布图案260、第二上绝缘层270和第二保护层280。第二贯穿结构240、第二上绝缘层270、第二再分布图案260和第二保护层280可以分别与图1A至图1D的实施例中描述的第一贯穿结构140、第一上绝缘层170、第一再分布图案160和第一保护层180基本上相同。例如,第二上绝缘层270可以设置在第二半导体基板210的顶表面上。第二上绝缘层270可以包括硅基绝缘材料。第二贯穿结构240可以设置在第二半导体基板210中。第二贯穿结构240可以穿透第二半导体基板210和第二上绝缘层270。如图4B所示,第二贯穿结构240还可以穿透第二电路层220的第二绝缘层221的上部,并且可以连接到第二电路层220的第二互连结构225。第二贯穿结构240可以通过第二互连结构225电连接到第二芯片焊盘250和第二集成电路223中的至少一者。
第二再分布图案260可以设置在第二半导体基板210的顶表面上,并且可以连接到第二贯穿结构240。例如,第二再分布图案260可以覆盖第二上绝缘层270,并且可以与第二贯穿结构240的顶表面接触。每个第二再分布图案260可以具有第二孔269。第二孔269可以暴露第二再分布图案260的内侧壁260c。
第二保护层280可以设置在第二再分布图案260上。第二保护层280可以具有第二开口289,并且每个第二开口289可以连接到相应一个第二孔269。不同于图4B,第二开口289的底端的宽度可以大于第二孔269的顶端的宽度。在这种情况下,第二开口289可以暴露第二再分布图案260的顶表面和第二保护层280的内侧壁。在这种情况下,第二保护层280的内侧壁可以不与第二再分布图案260的内侧壁260c共面。第二保护层280的顶表面与第二孔269的底表面之间的水平高度差可以在大约2μm至大约10μm的范围内。
即使在附图中未示出,第二半导体芯片200还可以包括第二下再分布图案和第二下保护层。第二下再分布图案和第二下保护层分别可以与在图2C或图2D的实施例中描述的第一下再分布图案163和第一下保护层183基本上相同。
最上面的第二半导体芯片200可以不包括第二贯穿结构240、第二再分布图案260和第二保护层280。每个第二半导体芯片200还可以包括第二下绝缘图案230,如图4B所示。
在下文中,将描述多个第二半导体芯片200之间通过凸块结构300的电连接。其他凸块结构300可以设置在第二半导体芯片200之间。第二半导体芯片200可以包括彼此相邻的下半导体芯片和上半导体芯片。这里,上半导体芯片可以设置在下半导体芯片的顶表面上。在下半导体芯片与上半导体芯片之间的凸块结构300中,焊料图案310可以设置在下半导体芯片的第二孔269中,并且可以与相应的第二再分布图案260的内侧壁260c接触。因此,可以减小芯片堆叠1000的厚度和半导体封装件的厚度。例如,第二半导体芯片200之间的距离A4可以小于相应的凸块结构300的高度A1。相应的凸块结构300可以对应于彼此相邻的第二半导体芯片200之间的凸块结构300。第二半导体芯片200之间的距离A4可以是下半导体芯片的第二再分布图案260上的第二保护层280的顶表面与上半导体芯片的第二下绝缘图案230的底表面之间的距离。第二半导体芯片200之间的距离A4可以在大约3μm至大约20μm的范围内。凸块结构300的高度A1可以在大约5μm至大约30μm的范围内。
焊料图案310的底表面可以与第二上绝缘层270接触。在某些实施例中,第二孔269的底表面可以设置在第二再分布图案260中。在这种情况下,焊料图案310的底表面可以连接到第二再分布图案260。焊料图案310可以通过下半导体芯片的第二再分布图案260连接到第二贯穿结构240。柱图案320可以连接到上半导体芯片的第二芯片焊盘250。因此,上半导体芯片和下半导体芯片可以彼此电连接。
如图4A所示,多个柱图案320的节距P1可以小于外部端子950的节距P2。柱图案320的节距P1可以小于多个内置凸块850的节距P3。
半导体封装件还可以包括第一底部填充层410、第二底部填充层420、第三底部填充层430和第四底部填充层440。第一底部填充层410和第二底部填充层420可以与参照图1A至图1D描述的基本上相同。
第三底部填充层430可以设置在第二半导体芯片200之间的第三间隙区域中。例如,第三底部填充层430可以设置在第二半导体芯片200之间,以密封或围绕相应的凸块结构300。第二半导体芯片之间的距离可以基本上等于相应的第三底部填充层430的厚度。第三底部填充层430的厚度可以小于相应的凸块结构300的高度A1。例如,第三底部填充层430的厚度可以在大约3μm至大约20μm的范围内。第三底部填充层430的厚度可以等于上半导体芯片的第二下绝缘图案230的底表面与下半导体芯片的第二再分布图案260上的第二保护层280的顶表面之间的距离。第三底部填充层430可以包括绝缘聚合物。例如,第三底部填充层430可以包括环氧基聚合物。
第三半导体芯片500可以安装在内置基板800的顶表面上。第三半导体芯片500可以与芯片堆叠1000横向间隔开。第三半导体芯片500可以包括中央处理单元(CPU)或图形处理单元(GPU)。连接凸块360可以设置在第三半导体芯片500的芯片焊盘与相应的金属焊盘820之间。每个连接凸块360可以包括焊料球或柱中的至少一种。连接凸块360可以包括诸如焊料材料的金属。第三半导体芯片500可以通过连接凸块360和金属互连线830电连接到第一半导体芯片100、第二半导体芯片200和/或外部端子950。
第四底部填充层440可以设置在内置基板800与第三半导体芯片500之间的第四间隙区域中。第四底部填充层440可以密封或围绕连接凸块360。第四底部填充层440可以包括环氧基聚合物。
模制层400可以覆盖第一半导体芯片100和第二半导体芯片200的侧壁以及第三半导体芯片500的侧壁。模制层400可以暴露最上面的第二半导体芯片200的顶表面以及第一半导体芯片100的顶表面。或者,模制层400还可以覆盖最上面的第二半导体芯片200的顶表面和/或第三半导体芯片500的顶表面。模制层400可以包括环氧基聚合物。在一些实施例中,模制层400可以包括与第一底部填充层410、第二底部填充层420、第三底部填充层430和第四底部填充层440的材料不同的材料。
半导体封装件还可以包括散热结构700。散热结构700可以设置在最上面的第二半导体芯片200的顶表面、第三半导体芯片500的顶表面和模制层400的顶表面上。在一些实施例中,散热结构700还可以延伸到模制层400的侧壁上。
在图3的半导体封装件以及图4A和图4B的半导体封装件中,封装基板900、模制层400、第一底部填充层410和第二底部填充层420可以与图1A至图1D的实施例中描述的基本上相同。第一半导体基板110、第一电路层120、第一贯穿结构140、第一再分布图案160、第一保护层180和凸块结构300可以与在图1A至图1D的实施例中描述的基本上相同。在某些实施例中,第一再分布图案160和凸块结构300可以与在图2A的实施例中描述的基本上相同。在某些实施例中,第一再分布图案160和第一保护层180可以与在图2B的实施例中描述的基本上相同。在某些实施例中,第一半导体芯片100还可以包括如在图2C或图2D的实施例中描述的第一下再分布图案和第一下保护层。
根据本发明构思的实施例,凸块结构可以设置在第一半导体芯片与第二半导体芯片之间。第一半导体芯片可以包括具有第一孔的第一再分布图案。凸块结构可以设置在第一孔中,并且可以与第一再分布图案的内侧壁接触。凸块结构的底表面可以设置在比第一再分布图案的顶表面低的水平高度处。因此,可以减小第一半导体芯片与第二半导体芯片之间的距离,并且可以使半导体封装件小型化。
由于凸块结构设置在第一孔中,所以可以抑制或防止在凸块结构之间发生电短路。可以减小第一半导体芯片与第二半导体芯片之间的底部填充层的厚度,从而可以改善半导体封装件的散热性质。
尽管已经参照示例实施例描述了本发明构思,但是对于本领域技术人员将明显的是,在不脱离本发明构思的精神和范围的情况下,可以进行各种改变和修改。因此,应当理解的是,以上实施例不是限制性的,而是说明性的。因此,本发明构思的范围将由所附权利要求及其等同形式的最广泛的允许解释来确定,并且不应由前述描述来限制或限定。
Claims (20)
1.一种半导体封装件,所述半导体封装件包括:
第一半导体芯片,所述第一半导体芯片包括半导体基板和位于所述半导体基板的顶表面上的再分布图案,所述再分布图案具有暴露所述再分布图案的内侧壁的孔;
第二半导体芯片,所述第二半导体芯片位于所述第一半导体芯片的顶表面上;和
凸块结构,所述凸块结构设置在所述第一半导体芯片与所述第二半导体芯片之间,
其中,所述凸块结构设置在所述孔中,并且与所述再分布图案的所述内侧壁接触。
2.根据权利要求1所述的半导体封装件,其中,所述凸块结构包括:
焊料图案,所述焊料图案填充所述孔,并且与所述再分布图案的所述内侧壁直接接触;和
柱图案,所述柱图案设置在所述焊料图案与所述第二半导体芯片的芯片焊盘之间。
3.根据权利要求1所述的半导体封装件,
其中,所述第一半导体芯片还包括位于所述半导体基板中的贯穿结构,并且
其中,所述再分布图案电连接到所述贯穿结构。
4.根据权利要求3所述的半导体封装件,其中,当在俯视图中观察时,所述凸块结构与所述贯穿结构间隔开。
5.根据权利要求1所述的半导体封装件,其中,所述第一半导体芯片与所述第二半导体芯片之间的距离小于所述凸块结构的高度。
6.根据权利要求5所述的半导体封装件,
其中,所述第一半导体芯片与所述第二半导体芯片之间的距离在3μm至20μm的范围内,并且
其中,所述凸块结构的所述高度在5μm至30μm的范围内。
7.根据权利要求1所述的半导体封装件,所述半导体封装件还包括:
底部填充层,所述底部填充层设置在所述第一半导体芯片与所述第二半导体芯片之间的间隙区域中,并且覆盖所述凸块结构;
其中,所述底部填充层的厚度小于所述凸块结构的高度。
8.根据权利要求7所述的半导体封装件,其中,所述底部填充层的热导率低于所述凸块结构的热导率。
9.根据权利要求7所述的半导体封装件,其中,所述底部填充层的所述厚度在3μm至20μm的范围内。
10.一种半导体封装件,所述半导体封装件包括:
第一半导体芯片,所述第一半导体芯片包括半导体基板和设置在所述半导体基板的顶表面上的再分布图案,所述再分布图案具有孔;
第二半导体芯片,所述第二半导体芯片位于所述第一半导体芯片的顶表面上;
焊料图案,所述焊料图案设置在所述孔中,以与所述再分布图案的内侧壁接触;和
柱图案,所述柱图案设置在所述焊料图案与所述第二半导体芯片之间。
11.根据权利要求10所述的半导体封装件,
其中,所述第一半导体芯片还包括穿透所述半导体基板的贯穿结构,并且
其中,所述焊料图案通过所述再分布图案电连接到所述贯穿结构。
12.根据权利要求10所述的半导体封装件,
其中,所述孔的底表面设置在所述再分布图案中,并且
其中,所述焊料图案的底表面和侧壁与所述再分布图案接触。
13.根据权利要求10所述的半导体封装件,所述半导体封装件还包括:
上绝缘层,所述上绝缘层设置在所述再分布图案与所述半导体基板的顶表面之间,
其中,所述孔暴露所述上绝缘层,并且
其中,所述焊料图案与所述上绝缘层接触。
14.根据权利要求10所述的半导体封装件,所述半导体封装件还包括:
下再分布图案,所述下再分布图案设置在所述半导体基板与所述再分布图案之间;和
下保护层,所述下保护层设置在所述下再分布图案与所述再分布图案之间。
15.根据权利要求10所述的半导体封装件,
其中,所述第一半导体芯片还包括设置在所述再分布图案上并且具有开口的保护层,
其中,所述开口连接到所述孔并且暴露所述保护层的内侧壁,并且
其中,所述焊料图案覆盖所述保护层的所述内侧壁。
16.根据权利要求15所述的半导体封装件,其中,所述柱图案的底表面设置在比所述保护层的顶表面低的水平高度处。
17.根据权利要求16所述的半导体封装件,其中,所述保护层包括光敏聚合物。
18.根据权利要求10所述的半导体封装件,所述半导体封装件还包括:
封装基板,所述封装基板的顶表面上安装有所述第一半导体芯片,
其中,所述第一半导体芯片还包括第一集成电路,
其中,所述第二半导体芯片包括第二集成电路,并且
其中,所述柱图案包括与所述焊料图案的材料不同的材料。
19.一种半导体封装件,所述半导体封装件包括:
封装基板;
第一半导体芯片,所述第一半导体芯片安装在所述封装基板上;
第二半导体芯片,所述第二半导体芯片设置在所述第一半导体芯片的顶表面上;和
凸块结构,所述凸块结构设置在所述第一半导体芯片与所述第二半导体芯片之间,
其中,所述第一半导体芯片包括:
第一半导体基板;
第一电路层,所述第一电路层设置在所述第一半导体基板的底表面上,并且包括第一集成电路;
第一贯穿结构,所述第一贯穿结构设置在所述第一半导体基板中;
第一再分布图案,所述第一再分布图案设置在所述第一半导体基板的顶表面上,并且连接到所述第一贯穿结构;
第一保护层,所述第一保护层位于所述第一再分布图案的顶表面上;和
上绝缘层,所述上绝缘层位于所述第一半导体基板与所述第一再分布图案之间,
其中,所述第二半导体芯片包括:
第二半导体基板;
第二电路层,所述第二电路层设置在所述第二半导体基板的底表面上,并且包括第二集成电路;和
芯片焊盘,所述芯片焊盘设置在所述第二电路层的底表面上,并且电连接到所述第二集成电路;
其中,所述第一再分布图案具有暴露所述第一再分布图案的内侧壁的孔,并且
其中,所述凸块结构包括:
焊料图案,所述焊料图案设置在所述孔中,以与所述第一再分布图案的所述内侧壁接触;和
柱图案,所述柱图案位于所述焊料图案与所述第二半导体芯片的所述芯片焊盘之间。
20.根据权利要求19所述的半导体封装件,所述半导体封装件还包括:
底部填充层,所述底部填充层设置在所述第一半导体芯片与所述第二半导体芯片之间,并且覆盖所述凸块结构的侧壁,
其中,所述底部填充层的厚度小于所述焊料图案的底表面与所述柱图案的顶表面之间的距离,并且
其中,所述底部填充层的热导率小于所述焊料图案的热导率和所述柱图案的热导率。
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US5620131A (en) | 1995-06-15 | 1997-04-15 | Lucent Technologies Inc. | Method of solder bonding |
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US6878633B2 (en) | 2002-12-23 | 2005-04-12 | Freescale Semiconductor, Inc. | Flip-chip structure and method for high quality inductors and transformers |
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US8241963B2 (en) * | 2010-07-13 | 2012-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessed pillar structure |
US9754860B2 (en) | 2010-12-24 | 2017-09-05 | Qualcomm Incorporated | Redistribution layer contacting first wafer through second wafer |
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US9484291B1 (en) * | 2013-05-28 | 2016-11-01 | Amkor Technology Inc. | Robust pillar structure for semicondcutor device contacts |
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