CN107579061B - 包含互连的叠加封装体的半导体装置 - Google Patents

包含互连的叠加封装体的半导体装置 Download PDF

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Publication number
CN107579061B
CN107579061B CN201610532093.1A CN201610532093A CN107579061B CN 107579061 B CN107579061 B CN 107579061B CN 201610532093 A CN201610532093 A CN 201610532093A CN 107579061 B CN107579061 B CN 107579061B
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package
semiconductor
die
substrate
contact pads
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CN201610532093.1A
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CN107579061A (zh
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邱进添
H.塔吉娅
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Shengdai Information Technology (shanghai) Co Ltd
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Shengdai Information Technology (shanghai) Co Ltd
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Priority to CN201610532093.1A priority Critical patent/CN107579061B/zh
Priority to US15/619,812 priority patent/US10242965B2/en
Priority to KR1020170079029A priority patent/KR101963024B1/ko
Publication of CN107579061A publication Critical patent/CN107579061A/zh
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Abstract

公开了一种半导体装置。所述半导体装置包含垂直堆叠且互连的至少第一半导体封装体和第二半导体封装体。所述第二半导体封装体和主机装置之间的信号通信通过所述第一半导体封装体发生。本公开提高了产品的良率。

Description

包含互连的叠加封装体的半导体装置
技术领域
本公开涉及半导体装置。
背景技术
对于便携消费电子产品需求的强势增长正驱动对于高容量储存装置的需求。非易失性半导体存储器装置，例如闪速存储器存储卡，正被广泛应用，以满足对数字信息储存和交换的日益增长的需求。其便携性，多功能和坚固设计，以及其高可靠性和大容量，已使得这样的存储器装置被理想地使用于各种各样的电子装置中，包括例如数码照相机、数码音乐播放器、视频游戏控制器、PDA和移动电话。
尽管已知多种不同的封装配置，闪速存储器存储卡通常可以制造为系统级封装(SiP)或多芯片模块(MCM)，在这种情况下，多个裸芯安装并且互连到小足印(footprint)基板上。基板通常可以包含刚性的、电介质基底，所述基底具有蚀刻在其一侧或两侧上的导电层。在裸芯和(多个)导电层之间形成电连接，并且(多个)导电层提供用于将裸芯连接到主机装置的电引导结构。一旦建立裸芯和基板之间的电连接，组装件典型地被包装在提供保护性封装的模塑料中。
图1和图2示出了常规半导体封装体20的截面侧视图和俯视图(图2中无模塑料)。典型的封装体包含固定至基板26的多个半导体裸芯，例如闪速存储器裸芯22和控制器裸芯24。在裸芯制造工艺期间，可以在半导体裸芯22、24上形成多个裸芯接合垫28。类似地，可以在基板26上形成多个接触垫30。可以将裸芯22固定到基板26，然后将裸芯24安装到裸芯22上。然后可以通过在相应的裸芯接合垫28和接触垫30对之间固定引线键合体32，来将全部的裸芯电联接到基板。一旦建立全部电连接，可以将裸芯和引线键合体包封到模塑料34中，以密封封装体，并且保护裸芯和引线键合体。
为最高效地利用封装体足印(footprint)，上下叠置半导体裸芯是已知的，或者完全彼此重叠并在相邻的裸芯之间具有间隔层，或者如图1和图2所示具有偏移。在偏移配置中，裸芯堆叠在另一裸芯的顶部上，使得下面的裸芯的接合垫被暴露。偏移配置提供了堆叠体中的每个半导体裸芯上的接合垫都易于接近的优点。
随着半导体裸芯变得更薄，且为了增加半导体封装体中的存储器容量，半导体封装体中叠置的裸芯的数量持续增加。然而，这样可能造成从上面的裸芯向下到基板的长键合引线。长键合引线容易损坏或短路到其他引线键合体，并且还具有比短引线键合体更低的信噪比。此外，封装体中的大量的半导体裸芯可能不利地影响良率(yield)。
发明内容
概括来说，在一个示例中，本技术涉及一种半导体装置，包含：第一半导体封装体，该第一半导体封装体包含：第一基板、第一多个半导体裸芯、插入器层(具有固定到插入器层的表面的多个焊料球)、以及包封第一半导体封装体的至少一部分的第一模塑料，焊料球的至少一部分延伸穿过第一模塑料的表面；以及第二半导体封装体，该第二半导体封装体包含：第二基板(包含在第二基板的表面上的接触垫)，第二多个半导体裸芯，以及包封第二半导体封装体的至少一部分的第二模塑料；延伸穿过第一模塑料的焊料球的图案与第二基板的表面上的接触垫的图案相匹配，焊料球固定到接触垫，以将第一半导体封装体联接到第二半导体封装体。
在另一示例中，本技术涉及一种半导体装置，包含：第一半导体封装体，该第一半导体封装体包含：第一基板，第一多个半导体裸芯，插入器层(具有在插入器层表面中的多个接触垫)，以及包封第一半导体封装体的至少一部分的第一模塑料，接触垫通过第一模塑料的表面暴露；以及第二半导体封装体，该第二半导体封装体包含：第二基板(包含在第二基板的表面上的接触垫，以及固定到接触垫的焊料球)、，第二多个半导体裸芯，以及包封第二半导体封装体的至少一部分的第二模塑料；第二基板的接触垫上的焊料球的图案与插入器层的表面上的接触垫的图案相匹配，焊料球固定到接触垫，以将第一半导体封装体联接到第二半导体封装体。
在另一示例中，本技术涉及一种半导体装置，包含：第一半导体封装体，该第一半导体封装体包含：第一基板(包含在第一基板的表面上的第一组接触垫)、第一多个半导体裸芯、具有多个接触的插入器层，在插入器层、第一多个半导体裸芯和第一基板之间延伸的第一组引线键合体、在插入器层和第一基板之间延伸，绕过第一多个半导体裸芯的第二组引线键合体，以及包封第一半导体封装体的至少一部分的第一模塑料；第二半导体封装体，该第二半导体封装体包含：第二基板(包含在第二基板的表面上的第二组接触垫)、第二多个半导体裸芯、在第二多个半导体裸芯和第二基板之间延伸的第三组引线键合体、以及包封第二半导体封装体的至少一部分的第二模塑料；将插入器层上的多个接触与第二基板的表面上的第二组接触垫焊料连接，以电联接第一半导体封装体和第二半导体封装体。
在另一示例中，本技术涉及一种半导体装置，包含：第一半导体封装体，该第一半导体封装体包含：第一基板(包含在第一基板的表面上的第一组接触垫)、第一多个半导体裸芯、用于在第一半导体封装体和第二半导体封装体之间传输电压的插入器机构、用于在插入器机构、第一多个半导体裸芯和第一基板之间传输电压的第一电连接机构、用于在插入器机构和第一基板之间传输电压，绕过第一多个半导体裸芯的第二电连接机构、以及包封第一半导体封装体的至少一部分的第一模塑料；第二半导体封装体，该第二半导体封装体包含：第二基板(包含在第二基板的表面上的第二组接触垫)、第二多个半导体裸芯、用于在第二多个半导体裸芯和第二基板之间传输电压的第三电连接机构，以及包封第二半导体封装体的至少一部分的第二模塑料；以及连接机构，用于连接插入器层上的多个接触和第二基板的表面上的接触垫，以将第一半导体封装体和第二半导体封装体电联接。
附图说明
图1是常规半导体封装体的截面侧视图。
图2是常规基板和引线键合的半导体裸芯的俯视图。
图3是根据本发明的实施例的半导体装置总体制造工艺的流程图。
图4是根据本技术的实施例的制造工艺中的第一步骤的半导体装置的侧视图。
图5是根据本技术的实施例的制造工艺中的第二步骤的半导体装置的俯视图。
图6是根据本技术的实施例的制造工艺中的第三步骤的半导体装置的侧视图。
图7是根据本技术的实施例的制造工艺中的第四步骤的半导体装置的侧视图。
图8是根据本技术的实施例的制造工艺中的第五步骤的半导体装置的侧视图。
图9是根据本技术的实施例的制造工艺中的第五步骤的半导体装置的简化透视图。
图10是根据本技术的实施例的制造工艺中的第六步骤的半导体装置的侧视图。
图11是使用在根据本技术的实施例的半导体装置中的插入器层的俯视图。
图12是根据本技术的实施例的第一完成的半导体的侧视图。
图13示出了在根据本技术的实施例的制造工艺中的进一步的步骤中将要彼此固定的第一半导体封装体和第二半导体封装体。
图14示出了将第一半导体封装体和第二半导体封装体彼此固定，以形成根据本技术的实施例的完成的半导体装置。
图15和图16分别示出了根据本技术的进一步的实施例的插入器层和完成的半导体装置。
图17和图18分别示出了根据本技术的另一实施例的插入器层和完成的半导体装置。
具体实施方式
现在将参考附图描述本技术，其在实施例中涉及包含垂直堆叠且互连的半导体封装体的半导体装置。应当理解的是，本发明可以以多种不同形式来实施，而并不应理解为局限于本文所阐述的实施例。不如说，提供这些实施例以使得本公开彻底且完整，并且将本发明完全地传达给本领域技术人员。事实上，本发明意图覆盖这些实施例的替代方案、改动方案和等效方案，这些方案包含在由随附的权利要求所限定的本发明的范围和精神之内。此外，在下述对本发明的详细描述中，阐述许多具体细节是为了提供对本发明透彻的理解。然而，对于本领域普通技术的人员来说显而易见的是，在没有这些具体细节的情况下也可以实施本发明。
在本文所使用的，术语“顶部”和“底部”、“上”和“下”、“垂直”和“水平”仅是为示例和说明的目的，而并不意在限制本发明的描述，这是由于引用的项目可以在位置和取向上交换。同样，如本文所使用的，术语“实质上”、“近似地”和/或“大约”意味着具体的尺寸或参数可在对于给定应用的可接受的制造公差范围内变动。在一个实施例中，所述可接受的制造公差是±0.25％。
现在将参考图3的流程图以及图4至图18的俯视图和侧视图来解释本发明的一个实施例。尽管图4至图18中的每一个示出单独的半导体封装体100和/或150，或者其一部分，但应当理解的是，封装体100和150可以与基板面板上的多个其他封装体一起批量处理，以实现规模效益。基板面板上的封装体100、150的行和列的数量可以变化。
用于制造半导体封装体100的基板面板开始于多个基板102(再一次地，图4至图12示出了一个这样的基板)。基板102可以是各种不同的芯片载体介质，包含印刷电路板(PCB)、引线框架或带式自动键合(TAB)带。在这种情况下基板102是PCB，基板可以由具有顶部导电层105和底部导电层107的核心103形成，如图4所示。核心103可以由各种电介质材料形成，例如聚酰亚胺层压板、包含FR4和FR5的环氧树脂、双马来酰亚胺三嗪(bismaleimidetriazine，BT)，以及其他类似材料。尽管对于本发明并不关键，核心可以具有40微米(μm)至200微米(μm)之间的厚度，但是在可替代的实施例中，核心的厚度可能在该范围之外变化。在可替代的实施例中，核心103可以是陶瓷或有机物。
围绕核心的导电层105、107可以由铜或铜合金、镀铜或镀铜合金、合金42(42铁/58镍)、镀铜的钢、或已知用在基板面板上的其他金属和材料形成。导电层可以具有大约10μm至25μm的厚度，尽管在可替代的实施例中，层的厚度可能变化超出该范围。
图3是根据本发明的实施例的用于形成半导体装置180的制造工艺的流程图。在步骤200中，第一半导体封装体100的基板102可以钻孔，以限定基板102中的穿孔通孔104。通孔104为示例，而基板102可以包含比附图中示出的多很多的通孔104，并且它们可以在与图中示出的不同的位置上。接下来在步骤202中，在顶部导电层和底部导电层中的一者或两者上形成导电图案。(一个或多个)导电图案可以包含电迹线106、基板的顶部表面上的接触垫109、以及基板的底部表面上的接触垫108，如图5和图6中的示例所示。迹线106和接触垫109、108(其中仅一些在附图中编号)是示例，且基板102可以包含比图中示出的更多的迹线和/或接触垫，并且它们可以在与附图中示出的不同的位置上。在一个实施例中，在基板102的相对的边缘，基板102可以包含接触垫109的一个或多个行，如图5所示。
在实施例中，完成的半导体装置可以使用作为BGA(球栅阵列)封装体使用。基板102的下表面可以包含用于接收焊料球的接触垫108，如下文所解释的。在另一实施例中，完成的半导体装置180可以是LGA(连接盘栅格阵列)封装体，所述LGA封装体包含接触指，以在主机装置中可移除地联接完成的装置180。在这样的实施例中，下表面可以包含接触指，取代接收焊料球的接触垫。可以通过各种已知的工艺，例如包括各种光刻工艺，形成基板102上表面和/或下表面上的导电图案。
再次参考图3，接下来可以在步骤204中的自动光学检测(AOI)中检测基板102。一经检测，可以在步骤206中将焊接掩模110施加到基板。在施加焊接掩模之后，在步骤208中，可以通过已知的电镀或薄膜沉积工艺在接触垫以及导电图案上的任何其他要焊接的区域镀覆镍/金、合金42或其他类似材料。然后可以在自动化检测过程(步骤210)以及最终外观检查(步骤212)中检测和测试基板102，以检查电气运行，以及污染、划伤和变色(discoloration)。
假设基板102通过检测，接下来在步骤214可以将无源部件112(图5)固定到基板。一个或多个无源部件可以例如包含一个或多个电容器、电阻器和/或电感器，尽管可以设想有其他部件。示出的无源部件112仅为示例，而在其他实施例中其数量、类型和位置可以变化。
参考图7，接下来在步骤220可以将多个半导体裸芯124堆叠在基板102上。半导体裸芯124可以例如是存储器裸芯(例如NAND闪速存储器裸芯)，但也可以使用其他类型的裸芯124。半导体裸芯124可以以偏移阶梯式配置上下叠置以形成裸芯堆叠体120。可以使用裸芯贴附膜将裸芯固定到基板和/或彼此固定。例如，裸芯贴附膜可以是来自汉高集团股份有限及两合公司(Henkel AG&Co.KGaA)的8988UV环氧树脂，固化到B阶段，以将裸芯124初步地固定在堆叠体120中，并且随后固化到最终的C阶段，以将裸芯124永久地固定在堆叠体120中。
现在参考图8的侧视图，一旦形成裸芯堆叠体120，可以在步骤222中使用引线键合体130将堆叠体120中相应的裸芯124电连接到彼此以及至基板102。图9是示出了基板102和裸芯堆叠体120中的仅底部的两个裸芯124的简化透视图。如图所示，每个半导体裸芯124可以包含沿裸芯124的边缘的裸芯接合垫132的行。应当理解的是，每个裸芯124可以包含比图9中示出的多很多的裸芯接合垫132。可以使用引线键合体130将半导体裸芯的行中的每个裸芯接合垫132电连接到下个相邻的半导体裸芯的行中的相对应的裸芯接合垫132。可以使用引线键合体130将底部半导体裸芯124的每个裸芯接合垫132电连接到基板102上的接触垫的行中的相对应的接触垫109。
尽管可以通过各种技术形成引线键合体130，在一个实施例中，引线键合体130可以形成为球形键合和/或楔形键合。引线键合体130通常示出为垂直的直线列，从裸芯堆叠体120和基板中的一层到下一层，一个或多个引线键合体可以从一层到下一层对角地延伸。此外，引线键合体可以跳过裸芯堆叠体120中的一个或多个层。
如接下来的段落中所解释的，第二裸芯堆叠体可以堆叠在第一裸芯堆叠体120顶部上。为了给至第一裸芯堆叠体120中的最顶部的裸芯124的引线键合体提供空间，可以在堆叠体120中的最顶部的裸芯124的上表面上提供间隔层128(图7和8)。间隔层128也可以是用于将第二裸芯堆叠体粘附到第一裸芯堆叠体120的顶部上的粘附层。
间隔层128可以例如是具有已知成分的电绝缘粘附环氧树脂，例如来自日本的日东电气股份有限公司(Nitto Denko Corp)或加利福尼亚的汉高股份有限公司(HenkelCorporation)。在可替代的实施例中，可以提供间隔球以替代间隔层128，或者在间隔层128内提供间隔球。间隔球可以是聚合物球体，充当第一裸芯堆叠体与第二裸芯堆叠体之间的间隔体。这样的间隔球是本领域已知的，并且在例如在专利号为6,650,019，题为“制造包含堆叠的半导体裸芯的半导体封装体的方法(Method of Making a Semiconductor PackageIncluding Stacked Semiconductor Die)”的美国专利中公开。间隔层128可以具有足够的厚度，以防止第二裸芯堆叠体与到最顶部裸芯的引线键合体130接触。
参考图10的侧视图，接下来在步骤224中，可以将第二裸芯堆叠体122固定到第一裸芯堆叠体120的顶部上。在实施例中，可以按照与裸芯堆叠体120类似的方式形成第二裸芯堆叠体122，但在与裸芯堆叠体120相反的方向上呈阶梯式，以最小化裸芯堆叠体120与122的总共的足印(footprint)。裸芯堆叠体120和122可以相应包含8个半导体裸芯124，总共16个半导体裸芯。然而，应当理解的是，在其他实施例中，裸芯的总数量可以多于或少于16个。这样的其他实施例可以例如在封装体100中包含总共8个或32个半导体裸芯。
在形成裸芯堆叠体120、122之后，可以在步骤226中将插入器层134固定到上层堆叠体122中的上面的裸芯124，如图10所示。插入器层134可以与堆叠体122中的其他裸芯124以相同的方式和相同的程度来偏移。插入器层134可以是刚性层，例如由FR4或FR5形成，或者是柔性层，例如由聚酰亚胺带形成。如图11的俯视图部分地示出的，可以在上表面和插入器层134中形成导电图案。
插入器层134的导电图案可以包含两行接合垫136、接触垫138的图案以及电迹线，其中所述电迹线将两行接合垫136与其中一个相对应的接触垫138电连接。在将插入器层134安装到裸芯堆叠体122上之前或之后，可以在接触垫138上形成焊料球140。如下文所解释的，可以经由插入器层134的焊料球140，将第二半导体封装体150安装并且电连接到第一半导体封装体100。
在安装之后，接下来在步骤230中，可以将裸芯堆叠体122和插入器层134引线键合到彼此并且到基板102。如图10所示，引线键合体131可以沿插入器层134的一个边缘形成在接合垫136上，向下至第二裸芯堆叠体122中的每个裸芯124上的裸芯接合垫，然后向下至基板102的顶部表面上的接触垫109，如示出的沿封装体100的左边缘。在可替代的实施例中，间隔层128可以被替换为第一裸芯堆叠体120和第二裸芯堆叠体122之间的第二插入器层(未示出)。在这样的实施例中，作为如图10所示的制作从堆叠体122中的底部裸芯124到基板的跳线(jump)的替代，堆叠体120、122之间的插入器层可以将堆叠体122中的引线键合体131联接到封装体100的相对的侧面上的堆叠体120中的引线键合体130。
除了联接到插入器层的第一边缘上的接合垫136的引线键合体131之外，可以将第二组引线键合体133连接到沿插入器层的第二边缘的接合垫136。这些引线键合体133可以绕过堆叠体120和122中的裸芯，并且被直接连接到基板102上的接触垫109，如图10中的封装体100的右边缘上所示出的。如下文所解释的，引线键合体133可以经由插入器层134从第二半导体封装体150直接传输电压到基板102。这样的电压可以例如是非I/O电压，例如电源/接地、时钟信号或芯片使能信号。应当理解的是，在另一实施例中，包含引线键合体131和133的封装体100的侧面可以交换。
尽管图中示出了两个分离的堆叠体120、122，但应当理解的是，封装体100中的半导体裸芯可以以各种其他的形式堆叠。裸芯可以都在相同的方向上呈阶梯式。可替代地，可以有多于两个裸芯堆叠体，其每一个安装在前者的顶部之上，并且在相反的方向上呈阶梯式。每个这样的堆叠体可以例如包含两个、四个或八个半导体裸芯。如下文所解释的，与裸芯堆叠体的数量无关，可以将插入器层134固定到最顶部的裸芯堆叠体中的最顶部的裸芯，以将第一封装体100与第二封装体150连接。
在裸芯堆叠体120、122和插入器层134的安装和电连接之后，可以在步骤234中将裸芯堆叠体、引线键合体、插入器层和基板的至少一部分包封在模塑料142中，如图12所示。模塑料142可以例如包含固体环氧树脂、酚醛树脂、石英玻璃、结晶二氧化硅、炭黑和/或金属氢氧化物。这样的模塑料可以例如购自住友股份有限公司(Sumitomo Corp)和日东电气有限公司(Nitto-Denko Corp)，两者的总部都在日本。可以设想来自其他制造商的模塑料。可以根据各种已知的工艺来施加模塑料，包括通过传递模制或注射模制技术。如图12所示，可以施加模塑料，使得插入器层134上的焊料球140的至少一部分暴露在模塑料142的表面之上。
在形成包封的半导体封装体100之前、期间或之后，可以在步骤238中形成第二半导体封装体150。在实施例中，封装体150可以是通过与封装体100相同的步骤而形成的闪速存储器封装体，例如上文所述的图3的步骤200-234。然而，在其他实施例中，封装体100中的插入器层134、连接到插入器层134的引线键合体可以从封装体150省略，如图13所示。应当理解的是，在其他实施例中，封装体150可以具有相对于封装体100的其他区别，例如包含裸芯的数量、裸芯堆叠体的数量和裸芯堆叠体的取向。
在步骤240中，可以将第二半导体封装体150安装到第一半导体封装体100。特别地，第二半导体封装体150可以形成为具有基板102的底部表面上的接触垫108，所述接触垫108与在封装体100的包封的表面之上延伸的焊料球140的图案匹配。封装体150可以对准到封装体100之上(图13)，并且然后降低到封装体100的顶部之上(图14)。在此之后，可以将封装体100中的焊料球140回流焊到封装体150的下表面上的接触垫108上，以将封装体100和150物理地和电气地联接到一起，以形成完成的半导体装置180。
在步骤242中，可以将焊料球184固定到封装体100的基板102的下表面上的接触垫108，以将半导体装置180固定到例如印刷电路板的主机装置(未示出)。可以在封装体100和封装体150固定到彼此的之前或之后，将焊料球184固定到封装体100。在实施例中，可以在将封装体100固定到主机装置的相同的回流焊工艺期间将封装体150固定到封装体100。
在实施例中，一旦彼此固定，可以在进一步的包封工艺中将装置180的封装体100和150两者包封到一起。可替代地，可以用环氧树脂回填充(back-fill)封装体100和150之间的任何空间。在另一实施例中，不执行进一步的包封或回填充步骤，而封装体100和150仅通过焊料球140保持在一起。
如上所述，在实施例中，封装体150可以与封装体100相同，包含具有通过封装体150的上表面延伸的焊料球的插入器层134。在这样的实施例中，可以将第三半导体封装体(未示出)安装到封装体150顶部至上，以提供装置180中的三个半导体封装体。应当理解的是，在其他实施例中，可以将多于三个的这样的封装体以此方式堆叠。
可以在半导体装置180内进一步提供控制器裸芯(未示出)，安装到封装体100内、安装在封装体150中，或安装在封装体100、150两者中。在一个实施例中，控制器可以安装到形成在封装体100中的裸芯堆叠体120的下面的腔内。例如，控制器裸芯可以安装在设置在基板102与底部裸芯堆叠体120之间的间隔内。这样的实施例的示例在申请号为PCT/CN2013/070264、题为“包含用于嵌入和/或分隔半导体裸芯的独立薄膜层的半导体装置(Semiconductor Device Including an Independent Film Layer For Embedding and/or Spacing Semiconductor Die)”、国际申请日为2013年1月9日的专利合作条约专利中公开。作为另一示例，控制器裸芯可以安装到基板102中的腔内。这样的实施例的示例在申请号为PCT/CN2013/071051、题为“包含嵌入的控制器裸芯的半导体装置及其制造方法(Semiconductor Device Including an Embedded Controller Die and Method ofMaking Same)”、国际申请日为2013年1月28日的专利合作条约专利中公开。
在顶部半导体封装体150中使能的往复于半导体裸芯的读写操作可以经由封装体100在封装体150与主机装置之间流通。例如，可以通过使信号经由基板102、引线键合体131以及插入器层134，行进通过封装体100到达焊料球140，来使得信号在主机装置和在封装体150(图14)中使能的半导体裸芯124a之间通信。从那里，信号可以经由引线键合体130行进通过封装体150中的基板102并且到达裸芯124a。可以通过使信号经由基板102、引线键合体131以及插入器层134，行进通过封装体100到达焊料球140，来使得信号在主机装置和在封装体150中的使能的半导体裸芯124b之间通信。从那里，信号可以经由引线键合体131行进通过封装体150中的基板102并且到达裸芯124b。
除了读取/写入信号之外的电压，例如电源/接地、时钟信号和芯片使能信号，也可以经由封装体100行进往复于顶部半导体封装体150中的半导体裸芯。例如，可以通过使电压经由基板102、引线键合体133以及插入器层134，行进通过封装体100到达焊料球140，来使得电压在主机装置和封装体150中的半导体裸芯124之间通信。从那里，信号可以经由引线键合体130或131，行进通过封装体150中的基板102，并且到达半导体裸芯124。
如上文所述，延伸穿过下面的封装体100中的模塑料的表面的焊料球140的图案可以与上面的封装体150的底部表面上的接触垫108的图案匹配。在实施例中，封装体150的底部表面上的接触垫108的该图案还可以与封装体100的底部表面上的接触垫108的图案相同(如图13和14所示)，使得可以使用相同的材料和工艺来制造封装体100和150。然而，在其他实施例中，封装体150的底部表面上的接触垫108的图案可以与封装体100的底部表面上的接触垫108的图案不同。这样的实施例如图15和图16所示。在此实施例中，封装体100的顶部表面处的焊料球140的图案与封装体150的底部表面中的接触垫108的图案被设置为彼此匹配。
在上述实施例中，插入器层134包含接触垫138上的焊料球140，所述焊料球140延伸到封装体100之外，以与封装体150的下表面上的接触垫108键合。在其他实施例中，取而代之地，焊料球可以初始地安装到封装体150的接触垫108上。这样的实施例如图17和图18所示。在此实施例中，封装体100的插入器层134如上文所描述的形成，但不具有焊料球140(图17)。然后包封封装体100，但在上表面处的模塑料中具有开口，以暴露插入器层134的接触垫138。
在这样的实施例中，上面的封装体150与基板102的下表面中的接触垫108一同形成，并且施加焊料球140到这些接触垫108。封装体150中的接触垫108和焊料球140的图案与封装体100的插入器层134中的接触垫138相匹配。可以通过将封装体150在封装体100之上对准，并且将封装体150的焊料球140与封装体100中的暴露的接触垫138配合，来将封装体100和150彼此固定。
如上文所述，半导体封装体100可以形成在基板的面板上，而半导体封装体150可以类似地形成在基板的面板上。在形成封装体100和150之后(且在彼此固定之前)，封装体100和150可以在它们被包封后，从它们相应的基板面板单一化。每一个半导体封装体100、150可以通过各种切割方法(包含锯割、水射流切割、激光切割、水导引激光切割、干介质切割，以及金刚石图层线切割)中的任一种单一化。尽管直线切割将限定大致矩形或正方形的半导体封装体100、150，但应当理解的是，在本发明的其他实施例中，半导体封装体100和/或150可以具有除矩形和正方形之外的其他形状。
在其他实施例中，当封装体100仍是基板面板的一部分时，可以将单一化的封装体150固定到封装体100。在此之后，完整的半导体装置180可以被单一化。在另一些实施例中，可以将封装体150的面板对准并且安装到封装体100的面板之上。在此之后，可以使固定的封装体100和150的面板一起单一化。
在完成相应的封装体100和150的期间和之后(但在彼此固定之前)，可以测试封装体100和150中的每一个的运行和质量。本技术的特征是提供半导体装置的高良率。特别地，例如包含32个半导体裸芯的单个半导体封装体具有比包含16个裸芯的单个半导体封装体更高的缺陷率。根据本技术的示例，可以测试两个16裸芯的封装体，并且如果发现正常工作，则彼此固定。从而，本技术的半导体装置180提供了与具有相同数量裸芯的单个封装体相同的存储器容量，但可以更高的良率来制造。
此外，制造的半导体封装体中的缺陷通常并不致命，但造成完成的半导体封装体的质量变化。可以在“分箱(binning)”工艺中测试完成的半导体封装体，并且基于它们的性能来分类。本技术的另一特征是分箱允许质量类似的半导体封装体彼此固定。这允许了生产的半导体装置180的总体质量比包含具有相同数量的半导体裸芯的单个封装体的装置更高。
与包含相同数量的半导体裸芯的单个封装体相比，本技术的另一特征在于插入器层134实际上充当再分配层(RDL)，使半导体装置180中的半导体裸芯与主机装置之间的信号/电源/接地通信具有更高的灵活性和更好的管理。
完成的半导体装置180可以是例如存储器卡，例如MMC卡、SD卡、多功能卡、微SD卡、存储器棒、压缩SD卡、ID卡、PCMCIA卡、SSD卡、芯片卡、智能卡、USB卡、MCP型嵌入存储卡，或诸如此类。
为了说明和描述的目的，呈现了本发明的上述具体描述。其无意穷举或将本发明局限为所公开的特定形式。鉴于以上教导，可以进行许多改造和变化。选择所描述的实施例，是为了最好地解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够在各种实施例中最好地利用本发明，并做出各种修改以适合于所设想的特定用途。本发明的范围旨在通过所附的权利要求来限定。

Claims (10)

1.一种半导体装置，包含：
第一半导体封装体，包含：
第一基板，
第一多个半导体裸芯，
插入器层，具有固定到所述插入器层的表面的多个焊料球，
第一组引线键合体，从所述基板延伸到所述第一多个半导体裸芯中的每一个，且从所述第一多个半导体裸芯中的一个半导体裸芯延伸到所述插入器层，
第二组引线键合体，在所述插入器层和所述基板之间直接延伸，以及
第一模塑料，包封所述第一半导体封装体的至少一部分，所述焊料球的至少一部分延伸穿过所述第一模塑料的表面；以及
第二半导体封装体，包含：
第二基板，包含在所述第二基板的表面上的接触垫，
第二多个半导体裸芯，以及
第二模塑料，包封所述第二半导体封装体的至少一部分；
延伸穿过所述第一模塑料的表面的所述焊料球的图案与所述第二基板的表面上的接触垫的图案相匹配，所述焊料球固定到所述接触垫，以将所述第一半导体封装体联接到所述第二半导体封装体。
2.如权利要求1所述的半导体装置，其中所述第二半导体封装体和主机装置之间的信号通信通过所述第一半导体封装体发生。
3.如权利要求1所述的半导体装置，其中部分地使用连接到所述第一封装体中的第一多个裸芯的第一组引线键合体，以执行从所述第二封装体中的第二多个半导体裸芯读取数据，和/或将数据写入到所述第二封装体中的第二多个半导体裸芯。
4.如权利要求3所述的半导体装置，其中部分地使用未连接到所述第一封装体中的第一多个半导体裸芯的所述第一封装体中的第二组引线键合体，以执行除了从所述第二封装体中的第二多个半导体裸芯读取数据或将数据写入到所述第二封装体中的第二多个半导体裸芯之外的电压的输送。
5.如权利要求4所述的半导体装置，其中所述第二组引线键合体在所述插入器层和所述第一基板之间延伸。
6.如权利要求1所述的半导体装置，其中所述第一多个半导体裸芯与所述第二多个半导体裸芯在相同的分箱分类中。
7.如权利要求1所述的半导体装置，其中所述第一半导体封装体与所述第二半导体封装体具有相同的配置。
8.如权利要求1所述的半导体装置，其中所述第一半导体封装体与所述第二半导体封装体具有不同的配置。
9.如权利要求1所述的半导体装置，其中所述第二基板的表面上的接触垫是第一组接触垫，所述装置还包括在所述第一基板的表面上的第二组接触垫，所述第一组接触垫的图案与所述第二组接触垫的图案相匹配。
10.如权利要求1所述的半导体装置，其中所述第二基板的表面上的接触垫是第一组接触垫，所述装置还包括在所述第一基板的表面上的第二组接触垫，所述第一组接触垫的图案与所述第二组接触垫的图案不同。
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