CN109585431A - 一种Flash芯片堆叠的扇出封装结构及其制造方法 - Google Patents

一种Flash芯片堆叠的扇出封装结构及其制造方法 Download PDF

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CN109585431A
CN109585431A CN201811540270.6A CN201811540270A CN109585431A CN 109585431 A CN109585431 A CN 109585431A CN 201811540270 A CN201811540270 A CN 201811540270A CN 109585431 A CN109585431 A CN 109585431A
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flash chip
layer
chip
flash
fan
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倪寿杰
孙鹏
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN201811540270.6A priority Critical patent/CN109585431A/zh
Publication of CN109585431A publication Critical patent/CN109585431A/zh
Priority to PCT/CN2019/104927 priority patent/WO2020125073A1/zh
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Abstract

本发明公开了一种Flash芯片堆叠的Fan‑Out封装结构，包括：多个第一Flash芯片，所述多个第一Flash芯片通过错位正装层贴设置在封装结构的底部；第二Flash芯片，所述第二Flash芯片通过错位正装层贴设置在最上层第一Flash芯片之上；导电引线，所述导电引线电互连所述多个第一Flash芯片和第二Flash芯片；塑封层，所述塑封层包覆所述多个第一Flash芯片和第二Flash芯片；重新布局布线层，所述重新布局布线层与所述第二Flash芯片电连接，并实现对封装结构的扇出功能。

Description

一种Flash芯片堆叠的扇出封装结构及其制造方法
技术领域
本发明涉及半导体封装技术领域，尤其涉及一种Flash芯片堆叠的扇出封装结构及其制造方法。
背景技术
随着电子产品轻、小型化的要求，IC芯片封装趋于薄型、小型化。芯片封装的小型化、薄型化就显得尤其重要。在目前电子产品中，存储芯片占据非常重要的地位，而Flash(闪存)芯片又是其中一类核心产品。
传统的Flash存储芯片的封装结构通过堆叠封装实现器件密度的进一步提升。图1示出现有的Flash存储芯片的堆叠封装结构100。现有的封装结构通过再封装衬底/基板101上采用DAF(Die Attach Film，芯片粘接膜)错位层贴多个Flash存储芯片102，然后采用引线键合实现芯片间的互连最后进行整体塑封保护。这种Flash存储芯片的封装结构由于采用了封装基板工艺，极大的增加了堆叠封装结构的厚度。
针对现有Flash存储芯片的堆叠封装结构需要采用封装基板，存在的封装结构厚度较大等问题，本发明提出了一种新型的Flash芯片堆叠的Fan-Out(扇出)封装结构及其制造方法，省略了封装基板，实现了更小尺寸和更低厚度的堆叠封装结构。
发明内容
针对现有Flash存储芯片的堆叠封装结构需要采用封装基板，存在的封装结构厚度较大等问题，根据本发明的一个方面，提供一种Flash芯片堆叠的Fan-Out封装结构，包括：
多个第一Flash芯片，所述多个第一Flash芯片通过错位正装层贴设置在封装结构的底部；
第二Flash芯片，所述第二Flash芯片通过错位正装层贴设置在最上层第一Flash芯片之上，其中每个第一Flash芯片和第二Flash芯片的焊盘不会被相邻芯片覆盖；
导电引线，所述导电引线电互连所述多个第一Flash芯片和第二Flash芯片；
塑封层，所述塑封层包覆所述多个第一Flash芯片和第二Flash芯片；
重新布局布线层，所述重新布局布线层与所述第二Flash芯片电连接，并实现对封装结构的扇出功能。
在本发明的一个实施例中，Flash芯片堆叠的Fan-Out封装结构还包括设置在所述多个第一Flash芯片和所述第二Flash芯片的相邻两者之间的DAF薄膜，所述DAF薄膜用于实现所述错位正装层贴。
在本发明的一个实施例中，所述第二Flash芯片还包括：
RDL层，所述RDL层设置在所述第二Flash芯片表面，且与所述第二Flash芯片的IO互连；
互连焊盘，所述互连焊盘电连接至所述RDL层，用于实现所述第二Flash芯片和所述第一Flash芯片的互连；以及
导电铜柱。
在本发明的一个实施例中，所述互连焊盘为镍钯金焊盘。
在本发明的一个实施例中，所述重新布局布线层通过所述导电铜柱、所述RDL层实现和所述第二Flash芯片电连接。
在本发明的一个实施例中，所述塑封层漏出最下层第一Flash芯片的背面。
在本发明的一个实施例中，所述重新布局布线层具有N层重布线金属层，其中N≥2。
根据本发明的另一个实施例中，提供一种Flash芯片堆叠的Fan-Out封装结构的制造方法，包括：
提供第一Flash芯片和第二Flash芯片，其中第二Flash芯片具有RDL层、引线焊盘和导电铜柱；
采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上，并漏出各芯片的引线焊盘；
通过引线键合工艺电连接已完成错位层贴的第一Flash芯片和第二Flash芯片；
对完成引线键合的第一Flash芯片和第二Flash芯片进行整体塑封；
减薄塑封层并去除载板；
在裸露出第二Flash芯片的导电铜柱的塑封层上面形成重新布局布线层。
在本发明的另一个实施例中，所述采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上进一步包括：
将一个第一Flash芯片通过键合材料键合到载板上，形成最下层第一Flash芯片；
利用DAF薄膜将多个第一Flash芯片依次错位层贴至最下层第一Flash芯片上；以及
将一个第二Flash芯片错位层贴至最上层第一Flash芯片上。
在本发明的另一个实施例中，所述载板为透光材料；所述键合材料为激光可拆键合材料。
本发明提供一种Flash芯片堆叠的Fan-Out封装结构及其制造方法，基于扇出结构设计的封装，封装体中各层芯片通过引线键合互连，顶层芯片预设有重新布局布线层(RDL，Re-Distribution Layer)建立互连的镍钯金焊盘和导电铜柱，镍钯金焊盘与相邻层芯片通过引线键合互连，导电铜柱通过塑封减薄露头，然后再采用RDL和Bumping工艺互连实现最终堆叠封装结构。基于本发明的该种Flash芯片堆叠的Fan-Out封装结构具有相比现有flash产品更低的厚度，从而满足更多便携式、微型电子设备的要求。
附图说明
为了进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出现有技术的Flash存储芯片的堆叠封装结构100的剖面示意图。
图2示出根据本发明的一个实施例形成的一种Flash芯片堆叠的Fan-Out封装结构200的剖面示意图。
图3A至图3H示出根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的过程剖面示意图。
图4示出的是根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的流程图400。
具体实施方式
在以下的描述中，参考各实施例对本发明进行描述。然而，本领域的技术人员将认识到可在没有一个或多个特定细节的情况下或者与其它替换和/或附加方法、材料或组件一起实施各实施例。在其它情形中，未示出或未详细描述公知的结构、材料或操作以免使本发明的各实施例的诸方面晦涩。类似地，为了解释的目的，阐述了特定数量、材料和配置，以便提供对本发明的实施例的全面理解。然而，本发明可在没有特定细节的情况下实施。此外，应理解附图中示出的各实施例是说明性表示且不一定按比例绘制。
在本说明书中，对“一个实施例”或“该实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。在本说明书各处中出现的短语“在一个实施例中”并不一定全部指代同一实施例。
需要说明的是，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了方便区分各步骤，而并不是限定各步骤的先后顺序，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。
本发明提供一种Flash芯片堆叠的Fan-Out封装结构及其制造方法，基于扇出结构设计的封装，封装体中各层芯片通过引线键合互连，顶层芯片预设有重新布局布线层(RDL，Re-Distribution Layer)建立互连的镍钯金焊盘和导电铜柱，镍钯金焊盘与相邻层芯片通过引线键合互连，导电铜柱通过塑封减薄露头，然后再采用RDL和Bumping工艺互连实现最终堆叠封装结构。基于本发明的该种Flash芯片堆叠的Fan-Out封装结构具有相比现有flash产品更低的厚度，从而满足更多便携式、微型电子设备的要求。
下面结合图2来详细介绍根据本发明的一个实施例的一种Flash芯片堆叠的Fan-Out封装结构。图2示出根据本发明的一个实施例形成的一种Flash芯片堆叠的Fan-Out封装结构200的剖面示意图。如图2所示，该Flash芯片堆叠的Fan-Out封装结构200进一步包括第一Flash芯片210、第二Flash芯片220、芯片粘接膜230、导电引线240、塑封层250、重新布局布线层260以及外接焊球270。
第一Flash芯片210设置在封装结构的上部，为常规Flash芯片，由芯片主体和引线焊盘构成，其中引线焊盘用于和其他芯片和/或外部电路形成电互连。在本发明的一个实施例中，第一Flash芯片210包括3个相同或类似结构的类似芯片构成，从上到下依次为210-1、210-2、210-3，对应的具有3组引线焊盘211-1、211-2、211-3。
第二Flash芯片220通过在常规Flash芯片的表面通过重新布局布线层221形成外接导电铜柱223和互连焊盘222形成，设置在第一Flash芯片210的下面。在本发明的一个实施例中，互连焊盘为镍钯金焊盘。
芯片粘接膜230用于芯片堆叠时的贴片，通过标准的DAF工艺将多个第一Flash芯片210和一个第二Flash芯片220错位正贴，其中第二Flash芯片220位于最下层。如图所示，每个Flash芯片的焊盘区域不会被相邻层叠的Flash芯片覆盖。
导电引线240互连相邻的第一Flash芯片210和/或第二Flash芯片220。导电引线240通过引线键合工艺形成，可以为金线、铜线或者其他金属线或合金线。
塑封层250包覆第一Flash芯片210、第二Flash芯片220以及导电引线240，起到绝缘保护和结构支撑作用。在本发明的一个实施例中，最外侧的第一Flash芯片210的背面从塑封层250中裸露出来，以获得良好的散热效果。
重新布局布线层260设置在与第二Flash芯片220的导电铜柱223电互连，并实现对堆叠Flash芯片引脚的扇出功能。在本发明的一个实施例中，重新布局布线层260可以包括一层或多层重新布线层构成。
外接焊球270设置在重新布局布线层260的外接焊盘上，实现与外部电路的电和/或信号互连。
下面结合图3A至图3H以及图4来详细描述形成该种芯片Flash芯片堆叠的Fan-Out封装结构200的过程。图3A至图3H示出根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的过程剖面示意图；图4示出的是根据本发明的一个实施例形成该种Flash芯片堆叠的Fan-Out封装结构200的流程图400。
首先，在步骤410，如图3A、图3B所示，提供第一芯片310和第二芯片320。其中第一芯片为常规Flash芯片，由芯片主体311和引线焊盘312构成，其中引线焊盘用于和其他芯片和/或外部电路形成电互连；第二芯片320在常规Flash芯片的表面通过重新布局布线层321形成外接导电铜柱323和互连焊盘322形成。在本发明的一个实施例中，需要提供多组第一芯片310和一组第二芯片320，第二芯片320的互连焊盘322为镍钯金焊盘。
接下来，在步骤420，如图3C所示，采用DAF工艺将多个第一芯片310及一个第二芯片320错位层贴并键合到载板340上，错位层贴漏出各芯片的引线焊盘。在本发明的一个实施中，第一步将一个第一芯片310-1通过键合材料330键合到载板340上，第二步采用DAF薄膜350将多个第一芯片310-2、310-3及一个第二芯片320错位层贴至第一芯片310-1上。在本发明的又一实施例中，键合材料330为激光可拆键合材料，载板340为透光材料，以获得更安全、经济和高效的工艺效果。
然后，在步骤430，如图3D所示，通过导电引线360引线键合电连接已完成错位层贴的第一芯片310和第二芯片320。导电引线360可以为金线、铜线或其他金属线以及合金线。
接下来，在步骤440，如图3E所示，对完成引线键合的第一芯片310和第二芯片320进行整体塑封，塑封后的塑封层370完全包覆第一芯片310和第二芯片320。
然后，在步骤450，如图3F所示，减薄塑封层370，并去除载板340。其中减薄塑封层370可通过研磨、抛光等工艺实现，逐渐减薄塑封层370，直到漏出第二芯片320的导电铜柱323，在导电铜柱323上方形成晶圆重构面。其中，去除载板340工艺可通过加热、光照等方式完成，具体去除方式需要依据键合材料330的特性进行。
接下来，在步骤460，如图3G所示，在裸露出第二芯片320的导电铜柱323的塑封层上面形成重新布局布线层380。重新布局布线层380与导电铜柱323电互连。在本发明的一个实施例中，重新布局布线层380可以具有一层或多层，同时在相邻两层间或同层的导线间还设置有介质层以起到绝缘和保护作用。
最后，在步骤470，如图3H所示，形成外接焊球390。外接焊球390设置在重新布局布线层380的最外层布线的外接焊盘位置。
基于本发明提供的该种Flash芯片堆叠的Fan-Out封装结构及其制造方法，基于扇出结构设计的封装，封装体中各层芯片通过引线键合互连，顶层芯片预设有重新布局布线层(RDL，Re-Distribution Layer)建立互连的镍钯金焊盘和导电铜柱，镍钯金焊盘与相邻层芯片通过引线键合互连，导电铜柱通过塑封减薄露头，然后再采用RDL和Bumping工艺互连实现最终堆叠封装结构。基于本发明的该种Flash芯片堆叠的Fan-Out封装结构具有相比现有flash产品更低的厚度，从而满足更多便携式、微型电子设备的要求。
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。

Claims (10)

1.一种Flash芯片堆叠的Fan-Out封装结构，包括：
多个第一Flash芯片，所述多个第一Flash芯片通过错位正装层贴设置在封装结构的底部；
第二Flash芯片，所述第二Flash芯片通过错位正装层贴设置在最上层第一Flash芯片之上，其中每个第一Flash芯片和第二Flash芯片的焊盘不会被相邻芯片覆盖；
导电引线，所述导电引线电互连所述多个第一Flash芯片和第二Flash芯片；
塑封层，所述塑封层包覆所述多个第一Flash芯片和第二Flash芯片；
重新布局布线层，所述重新布局布线层与所述第二Flash芯片电连接，并实现对封装结构的扇出功能。
2.如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，还包括设置在所述多个第一Flash芯片和所述第二Flash芯片的相邻两者之间的DAF薄膜，所述DAF薄膜用于实现所述错位正装层贴。
3.如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述第二Flash芯片还包括：
RDL层，所述RDL层设置在所述第二Flash芯片表面，且与所述第二Flash芯片的IO互连；
互连焊盘，所述互连焊盘电连接至所述RDL层，用于实现所述第二Flash芯片和所述第一Flash芯片的互连；以及
导电铜柱。
4.如权利要求3所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述互连焊盘为镍钯金焊盘。
5.如权利要求1或3所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述重新布局布线层通过所述导电铜柱、所述RDL层实现和所述第二Flash芯片电连接。
6.如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述塑封层漏出最下层第一Flash芯片的背面。
7.如权利要求1所述的Flash芯片堆叠的Fan-Out封装结构，其特征在于，所述重新布局布线层具有N层重布线金属层，其中N≥2。
8.一种Flash芯片堆叠的Fan-Out封装结构的制造方法，包括：
提供第一Flash芯片和第二Flash芯片，其中第二Flash芯片具有RDL层、引线焊盘和导电铜柱；
采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上，并漏出各芯片的引线焊盘；
通过引线键合工艺电连接已完成错位层贴的第一Flash芯片和第二Flash芯片；
对完成引线键合的第一Flash芯片和第二Flash芯片进行整体塑封；
减薄塑封层并去除载板；
在裸露出第二Flash芯片的导电铜柱的塑封层上面形成重新布局布线层。
9.如权利要求8所述的方法，其特征在于，所述采用DAF工艺将多个第一Flash芯片及一个第二Flash芯片错位层贴并键合到载板上进一步包括：
将一个第一Flash芯片通过键合材料键合到载板上，形成最下层第一Flash芯片；
利用DAF薄膜将多个第一Flash芯片依次错位层贴至最下层第一Flash芯片上；以及
将一个第二Flash芯片错位层贴至最上层第一Flash芯片上。
10.如权利要求9所述的方法，其特征在于，所述载板为透光材料；所述键合材料为激光可拆键合材料。
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