CN107808878A - 堆叠型芯片封装结构 - Google Patents

堆叠型芯片封装结构 Download PDF

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Publication number
CN107808878A
CN107808878A CN201710622262.5A CN201710622262A CN107808878A CN 107808878 A CN107808878 A CN 107808878A CN 201710622262 A CN201710622262 A CN 201710622262A CN 107808878 A CN107808878 A CN 107808878A
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Prior art keywords
chip
terminal
seal
floor
road floor
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CN201710622262.5A
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Inventor
徐宏欣
林南君
张简上煜
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN107808878A publication Critical patent/CN107808878A/zh
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Abstract

本发明提供一种堆叠型芯片封装结构，其包括第一芯片、第一端子、第一重布线路层、第一密封体、第二芯片、第二端子、第二重布线路层以及贯通柱。第一芯片包括第一主动面以及位于第一主动面上的第一接垫。第一端子位于第一接垫上。第一重布线路层电性连接至第一芯片。第一密封体密封第一芯片，并暴露出第一端子的顶面。第二芯片配置于第一重布线路层上。第二芯片包括第二主动面以及位于第二主动面上的第二接垫。第二端子位于第二接垫上。第二重布线路层电性连接至第二芯片。贯通柱电性连接至第一重布线路层以及第二重布线路层。

Description

堆叠型芯片封装结构
技术领域
本发明涉及一种芯片封装结构及其制造方法，尤其涉及一种堆叠型(stackedtype)芯片封装结构及其制造方法。
背景技术
近年来，符合市场需求的电子设备以及制造技术的提升正在蓬勃地发展。考量到电脑(computer)，通信(communication)以及消费(consumer)等3C电子产品的便携性以及其不断成长的需求，传统的单芯片封装结构已逐渐不符合市场的需求。也就是说，在产品设计之时，必须考虑到轻、薄、短、小、紧密度、高密度以及低成本的趋势。因此，有鉴于对轻、薄、短、小以及紧密度的需求，以不同的方式堆叠具有各种功能的积体电路(integratedcircuits；IC)，以减少封装产品的尺寸以及厚度，已成为封装市场的主流策略。目前，具有封装层叠(package on package；POP)结构或封装内置封装(package in package；PIP)结构的封装产品乃是为了此趋势而研究开发。
一般而言，封装中的通孔(via hole)通常通过激光光束形成。在这种情况下，激光光束通过绝缘层，并且由铝或类似物所制成的芯片接垫可以于激光的照射下而被分开。如此一来，会对具有半导体芯片的元件造成破坏性的损坏。此外，随着电子设备的功能日益复杂及提升，封装层叠(PoP)结构以及封装内置封装(PiP)结构中所需堆叠的芯片数量也日益增加。因此，当务之急，必须控制封装件以及电接点的厚度，以便于封装制程中减小芯片封装结构的厚度。
发明内容
本发明提供一种堆叠型芯片封装结构，其具有良好的可靠性、较低的生产成本以及较薄的整体厚度。
本发明提供一种制造堆叠型芯片封装结构的制造方法，用于制造上述堆叠型芯片封装结构。
本发明提供一种堆叠型芯片封装结构的制造方法，所述方法包括以下步骤。配置至少一个第一芯片于载板上，其中第一芯片包括第一主动面以及位于第一主动面上的多个第一接垫，且第一端子位于第一接垫上。形成第一重布线路层以电性连接至第一芯片。形成第一密封体以密封第一芯片，并暴露出各个第一端子的顶面。配置至少一个第二芯片于第一密封体上，其中第二芯片包括第二主动面以及位于第二主动面上的多个第二接垫，且第二端子位于第二接垫上。形成第二重布线路层以电性连接至第二芯片。形成多个贯通柱，其中贯通柱电性连接至第一重布线路层以及第二重布线路层。
在本发明的一实施例中，配置至少一第一芯片于载板上的步骤以及形成第一密封体以密封第一芯片的步骤先于形成第一重布线路层的步骤，且形成第一重布线路层的步骤先于形成多个贯通柱的步骤。
在本发明的一实施例中，形成第一重布线路层的步骤先于配置至少一第一芯片于载板上的步骤以及形成多个贯通柱的步骤，且配置至少一第一芯片于载板上的步骤以及形成多个贯通柱的步骤先于形成第一密封体以密封第一芯片的步骤。
在本发明的一实施例中，配置至少一第一芯片以使第一主动面面向载板，且位于至少一第一芯片的第一主动面上的多个第一接垫通过多个第一端子电性连接至第一重布线路层。
在本发明的一实施例中，配置至少一第二芯片以使位于至少一第二芯片的第二主动面上的多个第二接垫通过多个第二端子电性连接至第二重布线路层。
在本发明的一实施例中，配置至少一第二芯片以使位于至少一第二芯片的第二主动面上的多个第二接垫通过多个第二端子电性连接至第一重布线路层。
在本发明的一实施例中，配置至少一第一芯片以使第一主动面面离载板，且位于至少一第一芯片的第一主动面上的多个第一接垫通过多个第一端子电性连接至第二重布线路层。
本发明更提供一种堆叠型芯片封装结构，其包括第一芯片、多个第一端子、第一重布线路层、第一密封体、第二芯片、多个第二端子、第二重布线路层以及多个贯通柱。各个第一芯片包括第一主动面以及位于第一主动面上的多个第一接垫。第一端子位于第一接垫上。第一重布线路层电性连接至第一芯片。第一密封体密封第一芯片，并暴露出第一端子的顶面。第二芯片配置于第一密封体上，其中第二芯片包括第二主动面以及位于第二主动面上的多个第二接垫。第二端子位于第二接垫上。第二重布线路层电性连接至第二芯片。贯通柱电性连接至第一重布线路层以及第二重布线路层。
在本发明的一实施例中，堆叠型芯片封装结构还包括第一底胶，位于第一芯片以及第一重布线路层之间，其中第一密封体密封第一芯片以及第一底胶。
在本发明的一实施例中，堆叠型芯片封装结构还包括第二底胶，位于第二芯片以及第二重布线路层之间，其中第二密封体密封第二芯片以及第二底胶。
基于上述，在本发明中，第一端子形成于第一芯片上，然后第一芯片配置于载板上。然后形成第一密封体以密封第一芯片，且第一重布线路层形成于第一密封体上以电性连接第一芯片。然后，其上形成有第二端子的第二芯片可以依续堆叠于第一密封体上，且形成第二重布线路层以电性连接至第二芯片，且形成贯通柱以电性连接至第一重布线路层以及第二重布线路层。通过这样的结构，可以进一步减小堆叠型芯片封装结构的厚度。此外，可以省略通过激光钻孔(laser drilling)以形成用于芯片的导通孔(conductive vias)的制程，因而降低堆叠型芯片封装结构的生产成本，以及因激光钻孔而对芯片接垫所引起的损坏。因此，由本发明的方法所制造的堆叠型芯片封装结构具有良好的可靠性、较低的生产成本以及较薄的整体厚度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1至图9是依据本发明一实施例的堆叠型芯片封装结构的制造方法的剖面示意图。
图10至图14是依据本发明一实施例的堆叠型芯片封装结构的部分制造方法的剖面示意图。
图15至图19是依据本发明一实施例的堆叠型芯片封装结构的部分制造方法的剖面示意图。
图20至图24是依据本发明一实施例的堆叠型芯片封装结构的部分制造方法的剖面示意图。
图25是依据本发明一实施例的堆叠型芯片封装结构的剖面示意图。
附图标记说明
100、100a、100b、100c：堆叠型芯片封装结构
10：载板
11：第一晶圆
11a：第一基本芯片
12：第二晶圆
12a：第二基本芯片
13、111、121：晶粒黏着膜
20：辅助载板
25：离型层
40：散热件
110：第一芯片
112：第一主动面
114：第一接垫
116：第一端子
120：第二芯片
122：第二主动面
124：第二接垫
126：第二端子
130：第一重布线路层
140：第一密封体
150：第二重布线路层
160：贯通柱
170：第二密封体
180：焊球
190：第一底胶
190a：第二底胶
具体实施方式
图1至图9是依据本发明一实施例的堆叠型芯片封装结构的制造方法的剖面示意图。本实施例中，堆叠型芯片封装结构的制造方法可以包括以下步骤。首先，请参照图1，提供第一晶圆11以及第二晶圆12。第一晶圆11包括多个第一基本芯片(primary chip)11a，第二晶圆12包括多个第二基本芯片12a。在各个第一基本芯片11a上形成多个第一端子116，且在各个第二基本芯片12a上形成多个第二端子126。在本实施例中，第一端子116以及第二端子126可以为如图1所示的一体形成(integrally formed)的导电柱，且第一端子116以及第二端子126的材质可以包括铜。第一端子116以及第二端子126可以为铜柱。在本实施例中，如图1所示，在第二晶圆12的背面可以贴附有晶粒黏着膜(die attach film；DAF)13，但本发明不限于此。
请参照图2以及图3，切割第一晶圆11以分离第一基本芯片11a，且也可以切割第二晶圆12以分离第二基本芯片12a。然后，如图3所示，自第一基本芯片11a中选取至少一个第一芯片110，并配置于载板10上。请回头参照图2，第一芯片110包括第一主动面112以及位于第一主动面112上的多个第一接垫114，且如图3所示，第一端子116位于第一接垫114上。在本实施例中，第一芯片110是以第一主动面112远离载板10的方式配置于载板10上，但本发明不限于此。
接着，请参照图4，形成第一密封体140以密封第一芯片110，并暴露出第一端子116的顶面。在本实施例中，第一密封体140可以先完全覆盖第一芯片110以及第一端子116。接着，可以对第一密封体140进行研磨制程(grinding process)，直到露出第一端子116的顶面。如此一来，第一密封体140的顶面与第一端子116的顶面共面(coplanar)。此外，可以进行某些处理(例如：蚀刻)，以进一步移除第一端子116的顶部。因此，如图3所示，第一端子116的顶面可以低于第一密封体140的顶面。如此一来，可以增加第一端子116以及第一密封体140与后续所形成的重布线路层(例如，第一重布线路层130)所接触的接触面积，以提升第一端子116，第一密封体140以及第一重布线路层130之间的接合强度。在一些实施例中，第一端子116的顶面与第一密封体140的顶面之间的高度差范围为1微米(micrometer；μm)至3微米。为求简洁，于其余图示中，第一端子116的顶面被示出为与第一密封体140的顶面基本上共面，但本发明不限于此。通过这样的结构，可以进一步减小堆叠型芯片封装结构100的厚度，且可以省略通过激光钻孔形成用于第一芯片110的导通孔的制程，从而降低堆叠型芯片封装结构100的制造成本。此外，由于于此省略了激光钻孔制程，从而可以避免因激光引起的对第一接垫114的损坏。除此之外，一体形成的第一端子116可以是实心柱，而通过激光制程所形成的通孔为内部具有空隙的锥形。因此，第一端子116可以具有较好的电性，并且可以减小任何两相邻的第一端子116之间的间隙。
接着，请参照图4，形成第一重布线路层130以电性连接至第一芯片110。在本实施例中，第一重布线路层130形成于第一密封体140上，但本发明不限于此。然后，例如通过电镀制程(electroplating process)以形成多个贯通柱160。
接着，请参照图5，自第二基本芯片12a中选取至少一个第二芯片120，并配置于第一重布线路层130上。在本实施例中，第二芯片120通过晶粒黏着膜121配置于第一重布线路层130上。于此，第二芯片120包括第二主动面122以及位于第二主动面122上的多个第二接垫124。如图5所示，第二端子126位于第二接垫124上。在本实施例中，第二芯片120是以第二主动面122远离第一重布线路层130的方式配置于第一重布线路层130上，但本发明不限于此。贯通柱160围绕第二芯片120并且电性连接至第一重布线路层130。
接着，请参照图6，形成第二重布线路层150以电性连接至第二芯片120。在本实施例中，可以形成第二密封体170以密封第二芯片120以及贯通柱160。第二密封体170暴露出第二端子126的顶面以及贯通柱160的顶面，且形成第二重布线路层150于第二密封体170上以电性连接至第二端子126以及贯通柱160。第二重布线路层150形成于相对于第一重布线路层130处。也就是说，第一重布线路层130以及第二重布线路层150分别位于第一密封体140或第二密封体170的两相对侧上。在本实施例中，第一重布线路层130以及第二重布线路层150分别位于第二密封体170的两相对侧上。因此，贯通柱160电性连接至第一重布线路层130以及第二重布线路层150，且第一重布线路层130位于第一密封体140以及第二密封体170之间。在后续的一些实施例中，第一重布线路层130以及第二重布线路层150分别位于第一密封体140的两相对侧上。
请参照图7以及图8，如图7所示，移除载板10。然后，可以翻转堆叠型芯片封装结构并配置于辅助载板20上，以在第一芯片110以及第一密封体140的背面上进行研磨制程(grinding process)。因此，堆叠型芯片封装结构100的厚度可以进一步地减小。如图7所示的结构例如可以通过离型层25而配置于辅助载板20上。接着，请参照图9，移除辅助载板20，并且在第二重布线路层150上形成多个焊球180。此时，基本上完成了堆叠型芯片封装结构100的制造过程。
图10至图14是依据本发明一实施例的堆叠型芯片封装结构的部分制造方法的剖面示意图。请参照图10至图14，在本实施例中，堆叠型芯片封装结构100a的制造过程与图1至图9所示出的堆叠型芯片封装结构100的制造过程类似。其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。堆叠型芯片封装结构100a以及堆叠型芯片封装结构100之间的制造过程的主要差异如下。
请参照图10以及图11，如图10所示，第一重布线路层130形成于载板10上。然后，例如通过电镀等制程将贯通柱160形成于第一重布线路层130上。然后，将自第一基本芯片(例如：如图2所示的第一基本芯片11a)中的至少一个第一芯片110配置于载板10上。在本实施例中，第一芯片110以覆晶(flip-chip)接合技术通过第一端子116配置于第一重布线路层130上，因此第一重布线路层130位于第一芯片110以及载板10之间。接着，形成第一底胶190于第一芯片110以及第一重布线路层130之间。
在本实施例中，第一端子116可以是包括铜、镍和锡银合金的导电凸块。第一端子116可以包括铜柱、位于铜柱上的锡银合金凸块，以及位于铜柱以及锡银合金凸块之间的镍层，但本发明不限于此。在本实施例中，在切割第一晶圆11以分离第一基本芯片11a之前，可以先在第一晶圆11的各个第一基本芯片11a上形成上述的第一端子116。
请参照图12，形成第一密封体140以密封第一芯片110、第一底胶190以及贯通柱160。在本实施例中，第一密封体140可以先完全覆盖第一芯片110以及贯通柱160。接着，可以对第一密封体140进行研磨制程，直到露出贯通柱160的顶面以及第一芯片110的背面。因此，堆叠型芯片封装结构100a的厚度可以进一步地减小。接着，形成第二重布线路层150于第一密封体140上，以与贯通柱160电性连接。第二重布线路层150形成于相对于第一重布线路层130处。在本实施例中，第一重布线路层130以及第二重布线路层150分别位于第一密封体140的两相对侧上。
请参照图13，以覆晶接合技术，通过第二端子126将自第二基本芯片(例如：如图2所示的第二基本芯片12a)中的至少一个第二芯片120配置于第二重布线路层150上。接着，形成第二底胶190a于第二芯片120以及第二重布线路层150之间。在本实施例中，第二端子126可以是包括铜、镍和锡银合金的导电凸块。举例而言，第二端子126可以包括铜柱、位于铜柱上的锡银合金凸块，以及位于铜柱以及锡银合金凸块之间的镍层，但本发明不限于此。在本实施例中，在切割第二晶圆12以分离第二基本芯片12a之前，可以先在第二晶圆12的各个第二基本芯片12a上形成上述的第二端子126。在本实施方式中，不需要在第二晶圆12的背面贴附晶粒黏着膜。然后，形成第二密封体170以密封第二芯片120以及第二底胶190a。
接着，请参照图14，自第一重布线路层130移除载板10，且焊球180可以形成于从载板10所暴露出的第一重布线路层130上。此时，基本上完成了堆叠型芯片封装结构100a的制造过程。
图15至图19是依据本发明一实施例的堆叠型芯片封装结构的部分制造方法的剖面示意图。请参照图15至图19，在本实施例中，堆叠型芯片封装结构100b的制造过程与图1至图9所示出的堆叠型芯片封装结构100的制造过程类似。其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。堆叠型芯片封装结构100b以及堆叠型芯片封装结构100之间的制造过程的主要差异如下。
请参照图15，在本实施例中，首先在载板10上形成第一重布线路层130，然后通过晶粒黏着膜111将来自于第一基本芯片11a的至少一个第一芯片110贴附于第一重布线路层130上。在本实施例中，第一端子116是可以一体形成的导电柱，且第一端子116所位于的第一主动面112面向远离于第一重布线路层130。在本实施例中，贯通柱160形成于第一重布线路层130上且围绕第一芯片110，第一密封体140密封贯通柱160并暴露出第一端子116的顶面以及贯通柱160的顶面。
请参照图16，形成第二重布线路层150于第一密封体140上，以与暴露出的第一端子116以及贯通柱160电性连接。因此，贯通柱160电性连接于第一重布线路层130以及第二重布线路层150之间。
请参照图17，例如通过离型层25以将辅助载板20配置于第二重布线路层150上，且将载板10自第一重布线路层130移除。此外，在载板10以及第一重布线路层130之间也可以具有离型层，因此可以通过离型层容易地移除载板10。接着，请参照图18，翻转图17的结构，且来自第二基本芯片12a中的至少一个第二芯片120配置于暴露出的第一重布线路层130上。
在本实施例中，第二芯片120通过覆晶接合技术配置于第一重布线路层130上。接着，形成第二底胶190a于第二芯片120以及第一重布线路层130之间。在本实施例中，第二端子126可以是包括铜、镍和锡银合金的导电凸块。举例而言，第二端子126可以包括铜柱、位于铜柱上的锡银合金凸块，以及位于铜柱以及锡银合金凸块之间的镍层，但本发明不限于此。在本实施例中，在切割第二晶圆12以分离第二基本芯片12a之前，可以先在第二晶圆12的各个第二基本芯片12a上形成上述的第二端子126。在本实施方式中，不需要在第二晶圆12的背面贴附晶粒黏着膜。然后，形成第二密封体170以密封第二芯片120以及第二底胶190a。
接着，如图19所示，移除辅助载板20以暴露出第二重布线路层150。接下来，将焊球180设置于第二重布线路层150上。此时，基本上完成了堆叠型芯片封装结构100b的制造过程。
图20至图24是依据本发明一实施例的堆叠型芯片封装结构的部分制造方法的剖面示意图。请参照图20至图24，在本实施例中，堆叠型芯片封装结构100c的制造过程与图15至图19所示出的堆叠型芯片封装结构100b的制造过程类似。其相同或类似的构件以相同或类似的标号表示，且具有相同或类似的功能，并省略描述。堆叠型芯片封装结构100c以及堆叠型芯片封装结构100b之间的制造过程的主要差异如下。
请参照图20，在本实施例中，形成第一重布线路层130于载板10上。接着，形成贯通柱160于第一重布线路层130上。接着，将来自于第一基本芯片11a中的多于一个第一芯片110配置于第一重布线路层130上。在此示出了两个第一芯片110，但本发明不限于此。值得注意的是，配置于第一重布线路层130上的第一芯片110可以相同或可以彼此不同。也就是说，配置于第一重布线路层130上的第一芯片110可以是彼此同性质/种类/类型(homogeneous)或彼此不同性质/不同种类/不同类型(heterogeneous)，本发明对于配置于第一重布线路层130上的第一芯片110的性质/种类/类型并不加以限定。在本实施例中，第一芯片110以覆晶(flip-chip)接合技术通过第一端子116配置于第一重布线路层130上，且贯通柱160围绕第一芯片110。第一芯片110的第一主动面112面向第一重布线路层130，且第一端子116可以是包括铜、镍和锡银合金的导电凸块。举例而言，第一端子116可以包括铜柱、位于铜柱上的锡银合金凸块，以及位于铜柱以及锡银合金凸块之间的镍层，但本发明不限于此。在本实施例中，在切割第一晶圆11以分离第一基本芯片11a之前，可以先在第一晶圆11的各个第一基本芯片11a上形成上述的第一端子116。
接着，形成第一密封体140以密封第一芯片110以及贯通柱160。在本实施例中，第一密封体140可以先完全覆盖第一芯片110以及贯通柱160。接着，可以对第一密封体140进行研磨制程，直到露出第一芯片110的背面以及贯通柱160的顶面，因而可以进一步减小堆叠型芯片封装结构100c的厚度。
接着，请参照图21，形成第二重布线路层150于第一密封体140上，以与贯通柱160电性连接。因此，贯通柱160电性连接第一重布线路层130以及第二重布线路层150。然后，对图21所示的结构所进行的后续制造过程(示出于图22至图24)基本上相同于图13以及图14所示出的制造过程，故相同或类似的特征于此不加以赘述。
在本实施例中，可以省略形成第一底胶190的制程。此外，可以形成第二密封体170以密封第二芯片120，或是也可以不形成第二密封体170。于此仅示出了两个第二芯片120，但发明对于第二芯片120的数量并不加以限制。类似地，如图14以及图19所示出的堆叠型封装结构100a、100b中，也可以不形成第二密封体170而不密封第二芯片120。在具有第二密封体170的堆叠型芯片封装结构100c的实施例中，第二密封体170可以暴露出或不暴露出第二芯片120的背面。类似地，如图14以及图19所示出的堆叠型芯片封装结构100a、100b中，第二密封体170也可以不暴露出第二芯片120的背面。除此之外，如图25所示，在第二密封体170暴露出第二芯片120背面的实施例中，可以配置散热件40于第二密封体170上并与第二芯片120的背面接触。类似地，于如图14以及图19所示的堆叠型芯片封装结构100a、100b中，散热件40也可以配置于第二密封体170上，且与第二芯片120的背面接触。
综上所述，在本发明中，第一端子形成于第一芯片上，然后第一芯片配置于载板上。然后，形成第一密封体以密封第一芯片，且第一重布线路层形成于第一密封体上以电性连接第一芯片。然后，其上形成有第二端子的第二芯片可以依续堆叠于第一重布线路层上，且形成第二重布线路层以电性连接至第二芯片，且形成贯通柱以电性连接至第一重布线路层以及第二重布线路层。
通过这样的结构，可以进一步减小堆叠型芯片封装结构的厚度，且可以省略通过激光钻孔形成用于芯片的导通孔的制程，从而降低堆叠型芯片封装结构的制造成本。并且，由于于此省略了激光钻孔制程，从而可以避免因激光引起的对芯片的接垫的损坏。此外，本发明的端子是预先形成于芯片上的实心柱，而通过激光工艺形成的通孔是具有内部空隙的锥形形状。因此，本发明的端子可以具有较好的电性，并且可以减小任何两相邻的端子之间的间隙。因此，由本发明的方法所制造的堆叠型芯片封装结构具有良好的可靠性、较低的生产成本以及较薄的整体厚度。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (10)

1.一种堆叠型芯片封装结构，其特征在于，包括：
第一芯片，其中所述第一芯片包括第一主动面以及位于所述第一主动面上的多个第一接垫；
多个第一端子，位于所述多个第一接垫上；
第一重布线路层，电性连接至所述第一芯片；
第一密封体，密封所述第一芯片且暴露出各个所述多个第一端子的顶面；
第二芯片，配置于所述第一密封体上，其中所述第二芯片包括第二主动面以及位于所述第二主动面上的多个第二接垫；
多个第二端子，位于所述多个第二接垫上；
第二重布线路层，电性连接至所述第二芯片；以及
多个贯通柱，电性连接至所述第一重布线路层以及所述第二重布线路层。
2.根据权利要求1所述的堆叠型芯片封装结构，其特征在于，所述多个第一端子为一体形成的导电柱，所述第一重布线路层位于所述第一密封体上，所述第二芯片配置于所述第一重布线路层上，所述第二主动面面离所述第一重布线路层，所述多个贯通柱位于所述第一重布线路层上且围绕所述第二芯片。
3.根据权利要求2所述的堆叠型芯片封装结构，其特征在于，还包括：
第二密封体，密封所述第二芯片以及所述多个贯通柱，其中所述第二密封体暴露出各个所述多个第二端子的顶面以及各个所述多个贯通柱的顶面，且所述第二重布线路层位于所述第二密封体上；以及
多个焊球，位于所述第二重布线路层上。
4.根据权利要求1所述的堆叠型芯片封装结构，其特征在于，所述第一芯片通过所述多个第一端子以配置于所述第一重布线路层上，且所述多个第一端子为包括铜、镍或锡银合金的导电凸块，所述多个贯通柱位于所述第一重布线路层上，所述第一密封体密封所述多个贯通柱并暴露出各个所述多个贯通柱的顶面，且所述第一重布线路层位于所述第一密封体上。
5.根据权利要求4所述的堆叠型芯片封装结构，其特征在于，所述第二芯片通过所述多个第二端子以配置于所述第二重布线路层上，且所述多个第二端子为包括铜、镍或锡银合金的导电凸块。
6.根据权利要求1所述的堆叠型芯片封装结构，其特征在于，所述第一芯片配置于所述第一重布线路层上。
7.根据权利要求6所述的堆叠型芯片封装结构，其特征在于，所述多个第一端子为一体形成的导电柱，且所述第一主动面面离所述第一重布线路层。
8.根据权利要求6所述的堆叠型芯片封装结构，其特征在于，所述第一芯片通过所述多个第一端子以配置于所述第一重布线路层上，且所述多个第一端子为包括铜、镍或锡银合金的导电凸块。
9.根据权利要求6所述的堆叠型芯片封装结构，其特征在于，所述多个贯通柱位于所述第一重布线路层上且围绕所述第一芯片，且所述第一密封体密封所述多个贯通柱并暴露出所述多个贯通柱的顶面。
10.根据权利要求8所述的堆叠型芯片封装结构，其特征在于，所述第二重布线路层位于所述第一密封体上，所述第二芯片通过所述多个第二端子以配置于所述第一重布线路层上，且所述多个第二端子为包括铜、镍或锡银合金的导电凸块。
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CN111599795A (zh) * 2019-02-21 2020-08-28 力成科技股份有限公司 半导体封装及其制造方法
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CN111599795B (zh) * 2019-02-21 2022-07-05 力成科技股份有限公司 半导体封装及其制造方法
WO2020232610A1 (zh) * 2019-05-20 2020-11-26 华为技术有限公司 芯片封装结构及芯片封装方法
CN110828431A (zh) * 2019-12-06 2020-02-21 上海先方半导体有限公司 一种用于三维扇出型封装的塑封结构
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