WO2021109527A1 - 一种用于三维扇出型封装的塑封结构 - Google Patents

一种用于三维扇出型封装的塑封结构 Download PDF

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WO2021109527A1
WO2021109527A1 PCT/CN2020/095306 CN2020095306W WO2021109527A1 WO 2021109527 A1 WO2021109527 A1 WO 2021109527A1 CN 2020095306 W CN2020095306 W CN 2020095306W WO 2021109527 A1 WO2021109527 A1 WO 2021109527A1
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layer
layout
plastic
encapsulation layer
chip
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PCT/CN2020/095306
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English (en)
French (fr)
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曹立强
戴风伟
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上海先方半导体有限公司
华进半导体封装先导技术研发中心有限公司
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Publication of WO2021109527A1 publication Critical patent/WO2021109527A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]

Definitions

  • the present invention relates to the technical field of semiconductor packaging, in particular to a plastic packaging structure for three-dimensional fan-out packaging.
  • the present invention proposes a three-dimensional fan-out package structure.
  • the plastic packaging structure of the package at least partially overcomes the above-mentioned problems in the prior art.
  • Plastic packaging structure for 3D fan-out packaging including:
  • a first plastic encapsulation layer where the first plastic encapsulation layer covers the first chip
  • a first layout and wiring layer where the first layout and wiring layer is arranged above the first plastic encapsulation layer and is electrically connected to the conductive vias of the first plastic encapsulation layer;
  • a second chip, the second chip is arranged above the first layout and wiring layer and is electrically connected to the first layout and wiring layer;
  • a second plastic encapsulation layer wherein the second plastic encapsulation layer covers the second chip and the top and side surfaces of the first encapsulation layer, and the bottom surface is substantially flush with the bottom surface of the second encapsulation layer;
  • a second layout and wiring layer, the second layout and wiring layer is disposed under the second plastic encapsulation layer and is electrically connected to the conductive vias of the first plastic encapsulation layer;
  • An external solder ball is electrically connected to the second layout and wiring layer.
  • the plastic packaging structure for three-dimensional fan-out packaging is characterized in that it further includes:
  • An insulating protective layer covering the lower surface of the second plastic encapsulation layer and the first plastic encapsulation layer except for the solder balls.
  • the front side of the first chip faces down, and the chip pad of the first chip is electrically connected to the second layout and wiring layer.
  • the front side of the first chip faces upward, and the chip pad of the first chip is electrically connected to the first layout and wiring layer.
  • the number of wiring layers of the first layout wiring layer is M layers, where M ⁇ 2.
  • the number of wiring layers of the second layout wiring layer is N layers, where N ⁇ 2.
  • a plastic packaging structure for three-dimensional fan-out packaging including:
  • a first plastic encapsulation layer where the first plastic encapsulation layer covers the first chip
  • a first layout and wiring layer where the first layout and wiring layer is disposed above the first plastic encapsulation layer and is electrically connected to the first chip;
  • a second chip, the second chip is arranged above the first layout and wiring layer and is electrically connected to the first layout and wiring layer;
  • a second plastic encapsulation layer wherein the second plastic encapsulation layer covers the second chip and the top and side surfaces of the first encapsulation layer, and the bottom surface is substantially flush with the bottom surface of the second encapsulation layer;
  • a second layout and wiring layer, the second layout and wiring layer is disposed on the second plastic encapsulation layer and is electrically connected to the conductive vias of the second plastic encapsulation layer;
  • An external solder ball is electrically connected to the second layout and wiring layer.
  • the plastic packaging structure used for three-dimensional fan-out packaging further includes:
  • An insulating protection layer is arranged to cover the upper surface of the second plastic encapsulation layer except for the solder balls.
  • the number of wiring layers of the first layout wiring layer is M layers, where M ⁇ 2.
  • the number of wiring layers of the second layout wiring layer is N layers, where N ⁇ 2.
  • the present invention provides a plastic packaging structure for three-dimensional fan-out packaging.
  • a first chip is plastic-encapsulated and interconnected fan-out by a conventional fan-out process to form a first chip fan-out packaging structure, and then the first chip is fan-out packaged.
  • a second chip is mounted on the structure to form a three-dimensional fan-out packaging structure, and finally the three-dimensional fan-out packaging structure is plastic-encapsulated a second time, and the second plastic packaging layer realizes five-fold sealing on the top and side surfaces of the three-dimensional fan-out packaging structure.
  • the plastic packaging structure for three-dimensional fan-out packaging based on the present invention solves the problems of stress delamination caused by thermal mismatch of the multi-layer interface, or delamination of the multi-layer interface caused by mechanical impact during cutting, and improves The reliability and yield of the three-dimensional fan-out package structure are improved.
  • FIG. 1 shows a schematic cross-sectional view of a plastic packaging structure 100 for three-dimensional fan-out packaging according to a first embodiment of the present invention.
  • FIG. 2 shows a schematic cross-sectional view of a plastic packaging structure 200 for three-dimensional fan-out packaging according to a second embodiment of the present invention.
  • FIG. 3 shows a schematic cross-sectional view of a plastic packaging structure 300 for three-dimensional fan-out packaging according to a third embodiment of the present invention.
  • FIG. 4 shows a schematic cross-sectional view of a plastic packaging structure 400 for three-dimensional fan-out packaging according to a fourth embodiment of the present invention.
  • FIG. 5 shows a schematic cross-sectional view of a plastic packaging structure 300 for three-dimensional fan-out packaging according to a fifth embodiment of the present invention.
  • the present invention provides a plastic packaging structure for three-dimensional fan-out packaging.
  • a first chip is plastic-encapsulated and interconnected fan-out by a conventional fan-out process to form a first chip fan-out packaging structure, and then the first chip is fan-out packaged.
  • a second chip is mounted on the structure to form a three-dimensional fan-out packaging structure, and finally the three-dimensional fan-out packaging structure is plastic-encapsulated a second time, and the second plastic packaging layer realizes five-fold sealing on the top and side surfaces of the three-dimensional fan-out packaging structure.
  • the plastic packaging structure for three-dimensional fan-out packaging based on the present invention solves the problems of stress delamination caused by thermal mismatch of the multi-layer interface, or delamination of the multi-layer interface caused by mechanical impact during cutting, and improves The reliability and yield of the three-dimensional fan-out package structure are improved.
  • FIG. 1 shows a schematic cross-sectional view of a plastic packaging structure 100 for three-dimensional fan-out packaging according to a first embodiment of the present invention.
  • the plastic packaging structure 100 for three-dimensional fan-out packaging further includes a first chip 110, a first plastic packaging layer 120, a first plastic packaging layer conductive via 130, a first layout layer 140, and a dielectric layer 150.
  • the first chip 110 may be a logic processing chip such as a processor, an FPGA, an MCU, or a storage chip such as a Flash, an EPROM, or a sensor or other radio frequency chips.
  • the first chip 110 may be a single chip or multiple chips, and when there are multiple chips, they may be chips of the same type or different types.
  • the first plastic encapsulation layer 120 covers the first chip 110.
  • the first plastic encapsulation layer 120 covers the five sides of the first chip 110 from the back and side surfaces, and the front side of the first chip 110 (the chip and the pad surface, opposite to the substrate) leaks out the first chip 110. Molding layer 120.
  • the conductive through hole 130 of the first plastic encapsulation layer is disposed to penetrate the first plastic encapsulation layer 120 and is separated from the first chip 110.
  • the conductive via 130 of the first plastic encapsulation layer is formed by filling the conductive material through the first plastic encapsulation layer 120.
  • the through holes of the conductive through holes 130 of the first plastic encapsulation layer are formed by laser or mechanical through holes in specific areas of the first plastic encapsulation layer 120; the conductive material is filled by electroplating of copper or other metals. Formed; it can also be formed by filling conductive silver paste or conductive glue.
  • the first layout and wiring layer 140 is disposed on the first plastic encapsulation layer 120 and forms an electrical connection with the conductive via 130 of the first plastic encapsulation layer.
  • the first layout and wiring layer 140 may be formed by an additive method or a subtractive method.
  • the first layout and wiring layer 140 may be a single-layer or multi-layer wiring layer.
  • the dielectric layer 150 is disposed between the same layer wiring of the first layout layer 140 and between adjacent layers.
  • the dielectric layer can be an inorganic insulating material such as silicon dioxide and silicon nitride, or an organic insulating material such as PI and resin, which plays a role of insulation and mechanical protection.
  • the second chip 160 is arranged on the first layout and wiring layer 140, and the pads 161 of the first layout and wiring layer 140 are electrically connected to the first layout and wiring layer 140 to realize the transmission of electrical and/or signals.
  • the second chip 160 is connected to the first layout and wiring layer 140.
  • the chip 110 may be a similar chip or a different chip. Similar to the first chip 110, the second chip 160 may also be a logic processing chip such as a processor, FPGA, or MCU, or a storage chip such as Flash, EPROM, or a sensor or other radio frequency chip. In an embodiment of the present invention, the second chip 160 may also be a single chip or multiple chips. When there are multiple chips, they may be of the same or different types.
  • the second plastic encapsulation layer 170 covers the side surfaces of the second chip 160, the first layout layer 140, the dielectric layer 150, and the first plastic encapsulation layer 120 to form a five-sided encapsulation on the upper and side surfaces of the encapsulation structure; the first plastic encapsulation layer is conductive
  • the through hole 130 and the front surface of the first chip 110 leak from the bottom surface of the second plastic encapsulation layer 170.
  • the second layout layer 180 is arranged under the second plastic package 170 and is electrically connected to the conductive vias 130 of the first plastic package layer and the front surface pads of the first chip 110; wherein the second layout layer 180 is also provided on the outermost layer There are external pads.
  • the second layout layer 180 may be a single layer or multiple layers.
  • the insulating protection layer 185 is disposed between the same layer wiring of the second layout layer 180 and between adjacent layers.
  • the external solder balls 190 are arranged on the external pads of the second layout layer 180 of the outermost layer, and serve as electrical and/or signal connections between the package structure and the external circuits and/or systems.
  • FIG. 2 shows a schematic cross-sectional view of a plastic packaging structure 200 for three-dimensional fan-out packaging according to a second embodiment of the present invention.
  • the plastic packaging structure 200 for three-dimensional fan-out packaging further includes a first chip 210, a first plastic packaging layer 220, a first plastic packaging layer conductive via 230, a first layout layer 240, and a dielectric layer 250.
  • the second chip 260, the second plastic encapsulation layer 270, the external pad 280, the insulating protection layer 285 and the external solder ball 290 is a plastic packaging structure 200 for three-dimensional fan-out packaging.
  • the difference between the plastic packaging structure 200 for three-dimensional fan-out packaging and the aforementioned plastic packaging structure 100 for three-dimensional fan-out packaging is only that the first chip 210 is disposed inside the first plastic encapsulation layer 220 with the first chip 210 facing upward.
  • the first chip pad 211 is electrically connected to the first layout layer 240; in addition, the external solder ball 290 is only electrically connected to the conductive via 230 of the first plastic encapsulation layer through the external pad 280.
  • FIG. 3 shows a schematic cross-sectional view of a plastic packaging structure 300 for three-dimensional fan-out packaging according to a third embodiment of the present invention.
  • the plastic package structure 300 for three-dimensional fan-out packaging further includes a first chip 310, a first plastic package layer 320, a first plastic package layer conductive via 330, a first layout layer 340, and a dielectric layer 350 , The second chip 360, the second plastic encapsulation layer 370, the second layout layer 380, the insulating protection layer 385, and the external solder balls 390.
  • the difference between the plastic packaging structure 300 for three-dimensional fan-out packaging and the aforementioned plastic packaging structure 200 for three-dimensional fan-out packaging is only the second layout and wiring layer 380, which can be a single layer or multiple layers. It is electrically connected to the conductive via 330 of the first plastic encapsulation layer, and realizes a uniform layout of the external pads.
  • FIG. 4 shows a schematic cross-sectional view of a plastic packaging structure 400 for three-dimensional fan-out packaging according to a fourth embodiment of the present invention.
  • the plastic packaging structure 400 for three-dimensional fan-out packaging further includes a first chip 410, a first plastic packaging layer 420, a first layout layer 430, a dielectric layer 440, a second chip 450, and a second plastic packaging layer.
  • the difference between the plastic packaging structure 400 for three-dimensional fan-out packaging and the aforementioned plastic packaging structure 200 for three-dimensional fan-out packaging is that the first chip 410 and the second chip 450 are electrically connected to the first chip through the chip pads 411 and 451, respectively.
  • the layout layer 430 is electrically connected to the second plastic encapsulation layer conductive via 470 penetrating the second encapsulation layer 460, and the external solder balls 490 are arranged above the second plastic encapsulation layer 460.
  • FIG. 5 shows a schematic cross-sectional view of a plastic packaging structure 500 for three-dimensional fan-out packaging according to a fifth embodiment of the present invention.
  • the plastic packaging structure 500 for three-dimensional fan-out packaging further includes a first chip 510, a first plastic packaging layer 520, a first layout layer 530, a dielectric layer 540, a second chip 550, and a second plastic packaging layer.
  • the difference between the plastic packaging structure 500 for three-dimensional fan-out packaging and the aforementioned plastic packaging structure 400 for three-dimensional fan-out packaging is only the second layout and wiring layer 580.
  • the second layout and wiring layer 580 can be a single layer or multiple layers. It is electrically connected to the conductive via 570 of the second plastic encapsulation layer, and realizes a uniform layout of the external pads.
  • the first chip is plastic-encapsulated and interconnected fan-out by a conventional fan-out process to form the first chip fan-out package structure, and then the first chip fan-out package structure is formed.
  • the second chip is mounted on the top of the package structure to form a three-dimensional fan-out package structure, and finally the three-dimensional fan-out package structure is plasticized a second time, and the second plastic encapsulation layer realizes the top and side surfaces of the three-dimensional fan-out package structure. seal.
  • the plastic packaging structure for three-dimensional fan-out packaging based on the present invention solves the problems of stress delamination caused by thermal mismatch of the multi-layer interface, or delamination of the multi-layer interface caused by mechanical impact during cutting, and improves The reliability and yield of the three-dimensional fan-out package structure are improved.

Abstract

一种用于三维扇出型封装的塑封结构（100），包括：第一芯片（110）；第一塑封层（120），所述第一塑封层（120）包覆所述第一芯片（110）；第一塑封层导电通孔（130），所述第一塑封层导电通孔（130）贯穿所述第一塑封层（120）；第一布局布线层（140），所述第一布局布线层（140）设置在所述第一塑封层（120）的上方，且与所述第一塑封层导电通孔（130）电连接；第二芯片（160），所述第二芯片（160）设置在所述第一布局布线层（140）的上方，且与第一布局布线层（140）电连接；第二塑封层（170），所述第二塑封层（170）包覆所述第二芯片（160）和所述第一塑封层（120）顶面和侧面，所述第一塑封层（120）的底面与所述第二塑封层（170）的底面基本齐平；第二布局布线层（180），所述第二布局布线层（180）设置在所述第二塑封层（170）的下面，与所述第一塑封层导电通孔（130）电连接；外接焊球（190），所述外接焊球（190）与所述第二布局布线层（180）电连接。

Description

一种用于三维扇出型封装的塑封结构 技术领域
本发明涉及半导体封装技术领域，尤其涉及一种用于三维扇出型封装的塑封结构。
背景技术
随着微电子技术的不断发展，用户对系统的小型化、多功能、低功耗、高可靠性的要求越来越高，尤其是近年来便携式手持终端市场需求的井喷，如手提电脑、智能手机和平板电脑等，要求更高的集成度和互连能力。而三维堆叠封装是满足上述要求的一种非常有效的技术途径。
在现有的三维堆叠封装结构，尤其是涉及三维扇出型封装结构中，经常需要采用两次或者更多次的塑封工艺，从而实现晶圆重构以及塑封保护。然后在两次塑封工艺中，不同层界面热失配引起的应力分层或由于切割的机械冲击导致的多层界面的分层等问题，如第一塑封层、介质层、金属互连层、第二塑封层等之间的界面分层。这些界面分层可能会导致封装结构的缺陷、可靠性乃至最终产品的良率。
针对现有的三维扇出型封装结构由于不同层界面热失配引起的应力分层或由于切割的机械冲击导致的多层界面的分层等问题，本发明提出一种用于三维扇出型封装的塑封结构，至少部分的克服了上述现有技术存在的问题。
发明内容
针对现有的三维扇出型封装结构由于不同层界面热失配引起的应力分层或由于切割的机械冲击导致的多层界面的分层等问题，根据本发明的一个实施例，提供一种用于三维扇出型封装的塑封结构，包括：
第一芯片；
第一塑封层，所述第一塑封层包覆所述第一芯片；
第一塑封层导电通孔，所述第一塑封层导电通孔贯穿所述第一塑封层；
第一布局布线层，所述第一布局布线层设置在所述第一塑封层的上方，且与所述第一塑封层导电通孔电连接；
第二芯片，所述第二芯片设置在所述第一布局布线层的上方，且与第一布局布线层电连接；
第二塑封层，所述第二塑封层包覆所述第二芯片和所述第一塑封层顶面和侧面，底面与所述第二塑封层的底面基本齐平；
第二布局布线层，所述第二布局布线层设置在所述第二塑封层的下面，与所述第一塑封层导电通孔电连接；以及
外接焊球，所述外接焊球与所述第二布局布线层电连接。
在本发明的一个实施例中，该用于三维扇出型封装的塑封结构，其特征在于，还包括：
设置在所述第一塑封层上表面与所述第二塑封层之间的介质层，所述介质层起到对所述第一布局布线层的同层布线间以及相邻层间的电绝缘和机械支撑作用；以及
设置在覆盖除外接焊球之外的所述第二塑封层和所述第一塑封层下表面的绝缘保护层。
在本发明的一个实施例中，所述第一芯片正面朝下，所述第一芯片的芯片焊盘与所述第二布局布线层电连接。
在本发明的一个实施例中，所述第一芯片正面朝上，所述第一芯片的芯片焊盘与所述第一布局布线层电连接。
在本发明的一个实施例中，所述第一布局布线层的布线层数为M层，其中M≥2。
在本发明的一个实施例中，所述第二布局布线层的布线层数为N层，其中N≥2。
根据本发明的另一个实施例，提供一种用于三维扇出型封装的塑封结构，包括：
第一芯片；
第一塑封层，所述第一塑封层包覆所述第一芯片；
第一布局布线层，所述第一布局布线层设置在所述第一塑封层的上方，且 与所述第一芯片电连接；
第二芯片，所述第二芯片设置在所述第一布局布线层的上方，且与第一布局布线层电连接；
第二塑封层，所述第二塑封层包覆所述第二芯片和所述第一塑封层顶面和侧面，底面与所述第二塑封层的底面基本齐平；
第二塑封层导电通孔，所述第二塑封层导电通孔贯穿所述第二塑封层；
第二布局布线层，所述第二布局布线层设置在所述第二塑封层的上面，与所述第二塑封层导电通孔电连接；以及
外接焊球，所述外接焊球与所述第二布局布线层电连接。
在本发明的另一个实施例中，用于三维扇出型封装的塑封结构还包括：
设置在所述第一塑封层上表面与所述第二塑封层之间的介质层，所述介质层起到对所述第一布局布线层的同层布线间以及相邻层间的电绝缘和机械支撑作用；以及
设置在覆盖除外接焊球之外的所述第二塑封层上表面的绝缘保护层。
在本发明的另一个实施例中，所述第一布局布线层的布线层数为M层，其中M≥2。
在本发明的另一个实施例中，所述第二布局布线层的布线层数为N层，其中N≥2。
本发明提供一种用于三维扇出型封装的塑封结构，首先通过常规扇出工艺对第一芯片进行塑封和互连扇出形成第一芯片扇出封装结构，然后在第一芯片扇出封装结构上方贴装第二芯片形成三维扇出型封装结构，最后对三维扇出型封装结构进行第二次塑封，第二塑封层实现对三维扇出型封装结构顶面和侧面的五面包封。基于本发明的该种用于三维扇出型封装的塑封结构解决了由于多层界面热失配引起的应力分层，或由于切割时的机械冲击导致的多层界面的分层等问题，提升了三维扇出型封装结构的可靠性和良率。
附图说明
为了进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明 的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出根据本发明的第一实施例的一种用于三维扇出型封装的塑封结构100的剖面示意图。
图2示出根据本发明的第二实施例的一种用于三维扇出型封装的塑封结构200的剖面示意图。
图3示出根据本发明的第三实施例的一种用于三维扇出型封装的塑封结构300的剖面示意图。
图4示出根据本发明的第四实施例的一种用于三维扇出型封装的塑封结构400的剖面示意图。
图5示出根据本发明的第五实施例的一种用于三维扇出型封装的塑封结构300的剖面示意图。
具体实施方式
在以下的描述中，参考各实施例对本发明进行描述。然而，本领域的技术人员将认识到可在没有一个或多个特定细节的情况下或者与其它替换和/或附加方法、材料或组件一起实施各实施例。在其它情形中，未示出或未详细描述公知的结构、材料或操作以免使本发明的各实施例的诸方面晦涩。类似地，为了解释的目的，阐述了特定数量、材料和配置，以便提供对本发明的实施例的全面理解。然而，本发明可在没有特定细节的情况下实施。此外，应理解附图中示出的各实施例是说明性表示且不一定按比例绘制。
在本说明书中，对“一个实施例”或“该实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。在本说明书各处中出现的短语“在一个实施例中”并不一定全部指代同一实施例。
需要说明的是，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了方便区分各步骤，而并不是限定各步骤的先后顺序，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。
本发明提供一种用于三维扇出型封装的塑封结构，首先通过常规扇出工艺对第一芯片进行塑封和互连扇出形成第一芯片扇出封装结构，然后在第一芯片扇出封装结构上方贴装第二芯片形成三维扇出型封装结构，最后对三维扇出型封装结构进行第二次塑封，第二塑封层实现对三维扇出型封装结构顶面和侧面的五面包封。基于本发明的该种用于三维扇出型封装的塑封结构解决了由于多层界面热失配引起的应力分层，或由于切割时的机械冲击导致的多层界面的分层等问题，提升了三维扇出型封装结构的可靠性和良率。
下面结合图1来详细介绍根据本发明的一个实施例的一种用于三维扇出型封装的塑封结构。图1示出根据本发明的第一实施例的一种用于三维扇出型封装的塑封结构100的剖面示意图。如图1所示，该用于三维扇出型封装的塑封结构100进一步包括第一芯片110、第一塑封层120、第一塑封层导电通孔130、第一布局布线层140、介质层150、第二芯片160、第二塑封层170、第二布局布线层180、绝缘保护层185以及外接焊球190。
第一芯片110可以为处理器、FPGA、MCU等逻辑处理芯片，也可以为Flash、EPROM等存储芯片，还可以为传感器或者射频类其他芯片等。在本发明的一个实施例中，第一芯片110可以为单个或者多个芯片，当为多个芯片时，可以为同类或者不同类芯片。
第一塑封层120包覆第一芯片110。在本发明的一个实施例中，第一塑封层120从背面和侧面实现对第一芯片110的五面包覆，第一芯片110的正面(芯片及焊盘面，与衬底相对)漏出第一塑封层120。
第一塑封层导电通孔130设置成贯穿第一塑封层120，且与第一芯片110分离开。在本发明的一个实施例中，第一塑封层导电通孔130通过对第一塑封层120通孔后进行填充导电材料形成。在本发明的一个具体实施例中，第一塑封层导电通孔130的通孔通过对第一塑封层120的特定区域进行激光通过或者机械通孔形成；导电材料填充通过铜或其他金属的电镀形成；也可以通过填充导电银浆或导电胶形成。
第一布局布线层140设置在第一塑封层120的上面，与第一塑封层导电通孔130形成电连接。第一布局布线层140可以通过加成法或者减成法形成。在本发明的一个实施例中，第一布局布线层140可以为单层或多层布线层。
介质层150设置在第一布局布线层140的同层布线间以及相邻层间。介质层可以为二氧化硅、氮化硅等无机绝缘材料，也可以为PI、树脂等有机绝缘材料，起到绝缘和机械保护作用。
第二芯片160设置在第一布局布线层140的上面，第一布局布线层140的焊盘161与第一布局布线层140电连接，实现电和或信号的传输，第二芯片160与第一芯片110可以为同类芯片或者不同芯片。与第一芯片110类似，第二芯片160也可以为处理器、FPGA、MCU等逻辑处理芯片，也可以为Flash、EPROM等存储芯片，或者为传感器或者射频类其他芯片等。在本发明的一个实施例中，第二芯片160也可以为单个或者多个芯片，当为多个芯片时，可以为同类或者不同类芯片。
第二塑封层170包覆第二芯片160、第一布局布线层140、介质层150以及第一塑封层120的侧面，形成对封装结构的上面和侧面的五面包覆；第一塑封层导电通孔130和第一芯片110的正面从第二塑封层170的底面漏出。
第二布局布线层180设置在第二塑封170的下面，与第一塑封层导电通孔130和第一芯片110的正面焊盘电连接；其中在最外层的第二布局布线层180还设置有外接焊盘。在本发明的一个实施例中，第二布局布线层180可以为单层或多层。
绝缘保护层185设置在第二布局布线层180的同层布线间以及相邻层间。
外接焊球190设置在最外层的第二布局布线层180的外接焊盘上，起到封装结构与外面电路和或系统的电和或信号连接作用。
下面结合图2来介绍根据本发明的第二实施例的一种用于三维扇出型封装的塑封结构。图2示出根据本发明的第二实施例的一种用于三维扇出型封装的塑封结构200的剖面示意图。如图2所示，该用于三维扇出型封装的塑封结构200进一步包括第一芯片210、第一塑封层220、第一塑封层导电通孔230、第一布局布线层240、介质层250、第二芯片260、第二塑封层270、外接焊盘280、绝缘保护层285以及外接焊球290。
该用于三维扇出型封装的塑封结构200与前述用于三维扇出型封装的塑封结构100的区别仅在于在第一芯片210正面朝上设置在第一塑封层220内部，第一芯片210的第一芯片焊盘211与第一布局布线层240电连接；此外，外接 焊球290仅通过外接焊盘280与第一塑封层导电通孔230电连接。
下面结合图3来介绍根据本发明的第三实施例的一种用于三维扇出型封装的塑封结构。图3示出根据本发明的第三实施例的一种用于三维扇出型封装的塑封结构300的剖面示意图。如图3所示，该用于三维扇出型封装的塑封结构300进一步包括第一芯片310、第一塑封层320、第一塑封层导电通孔330、第一布局布线层340、介质层350、第二芯片360、第二塑封层370、第二布局布线层380、绝缘保护层385以及外接焊球390。
该用于三维扇出型封装的塑封结构300与前述用于三维扇出型封装的塑封结构200的区别仅在于第二布局布线层380，第二布局布线层380可以为单层或多层，与第一塑封层导电通孔330电连接，并实现外接焊盘的均匀布局。
下面结合图4来介绍根据本发明的第四实施例的一种用于三维扇出型封装的塑封结构。图4示出根据本发明的第四实施例的一种用于三维扇出型封装的塑封结构400的剖面示意图。如图4所示，该用于三维扇出型封装的塑封结构400进一步包括第一芯片410、第一塑封层420、第一布局布线层430、介质层440、第二芯片450、第二塑封层460、第二塑封层导电通孔470、外接焊盘480、绝缘保护层485以及外接焊球490。
该用于三维扇出型封装的塑封结构400与前述用于三维扇出型封装的塑封结构200的区别在于第一芯片410和第二芯片450分别通过芯片焊盘411和451电连接到第一布局布线层430上，再与贯穿第二塑封层460的第二塑封层导电通孔470电连接，外接焊球490设置在第二塑封层460的上方。
最后，再结合图5来介绍根据本发明的第五实施例的一种用于三维扇出型封装的塑封结构。图5示出根据本发明的第五实施例的一种用于三维扇出型封装的塑封结构500的剖面示意图。如图5所示，该用于三维扇出型封装的塑封结构500进一步包括第一芯片510、第一塑封层520、第一布局布线层530、介质层540、第二芯片550、第二塑封层560、第二塑封层导电通孔570、第二布局布线层580、绝缘保护层585以及外接焊球590。
该用于三维扇出型封装的塑封结构500与前述用于三维扇出型封装的塑封结构400的区别仅在于第二布局布线层580，第二布局布线层580可以为单层或多层，与第二塑封层导电通孔570电连接，并实现外接焊盘的均匀布局。
基于本发明提供的该种用于三维扇出型封装的塑封结构，首先通过常规扇出工艺对第一芯片进行塑封和互连扇出形成第一芯片扇出封装结构，然后在第一芯片扇出封装结构上方贴装第二芯片形成三维扇出型封装结构，最后对三维扇出型封装结构进行第二次塑封，第二塑封层实现对三维扇出型封装结构顶面和侧面的五面包封。基于本发明的该种用于三维扇出型封装的塑封结构解决了由于多层界面热失配引起的应力分层，或由于切割时的机械冲击导致的多层界面的分层等问题，提升了三维扇出型封装结构的可靠性和良率。
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。

Claims (10)

  1. 一种用于三维扇出型封装的塑封结构，包括：
    第一芯片；
    第一塑封层，所述第一塑封层包覆所述第一芯片；
    第一塑封层导电通孔，所述第一塑封层导电通孔贯穿所述第一塑封层；
    第一布局布线层，所述第一布局布线层设置在所述第一塑封层的上方，且与所述第一塑封层导电通孔电连接；
    第二芯片，所述第二芯片设置在所述第一布局布线层的上方，且与第一布局布线层电连接；
    第二塑封层，所述第二塑封层包覆所述第二芯片和所述第一塑封层顶面和侧面，底面与所述第二塑封层的底面基本齐平；
    第二布局布线层，所述第二布局布线层设置在所述第二塑封层的下面，与所述第一塑封层导电通孔电连接；以及
    外接焊球，所述外接焊球与所述第二布局布线层电连接。
  2. 如权利要求1所述的用于三维扇出型封装的塑封结构，其特征在于，还包括：
    设置在所述第一塑封层上表面与所述第二塑封层之间的介质层，所述介质层起到对所述第一布局布线层的同层布线间以及相邻层间的电绝缘和机械支撑作用；以及
    设置在覆盖除外接焊球之外的所述第二塑封层和所述第一塑封层下表面的绝缘保护层。
  3. 如权利要求1所述的用于三维扇出型封装的塑封结构，其特征在于，所述第一芯片正面朝下，所述第一芯片的芯片焊盘与所述第二布局布线层电连接。
  4. 如权利要求1所述的用于三维扇出型封装的塑封结构，其特征在于，所述第一芯片正面朝上，所述第一芯片的芯片焊盘与所述第一布局布线层电连 接。
  5. 如权利要求1所述的用于三维扇出型封装的塑封结构，其特征在于，所述第一布局布线层的布线层数为M层，其中M≥2。
  6. 如权利要求1所述的用于三维扇出型封装的塑封结构，其特征在于，所述第二布局布线层的布线层数为N层，其中N≥2。
  7. 一种用于三维扇出型封装的塑封结构，包括：
    第一芯片；
    第一塑封层，所述第一塑封层包覆所述第一芯片；
    第一布局布线层，所述第一布局布线层设置在所述第一塑封层的上方，且与所述第一芯片电连接；
    第二芯片，所述第二芯片设置在所述第一布局布线层的上方，且与第一布局布线层电连接；
    第二塑封层，所述第二塑封层包覆所述第二芯片和所述第一塑封层顶面和侧面，底面与所述第二塑封层的底面基本齐平；
    第二塑封层导电通孔，所述第二塑封层导电通孔贯穿所述第二塑封层；
    第二布局布线层，所述第二布局布线层设置在所述第二塑封层的上面，与所述第二塑封层导电通孔电连接；以及
    外接焊球，所述外接焊球与所述第二布局布线层电连接。
  8. 如权利要求7所述的用于三维扇出型封装的塑封结构，其特征在于，还包括：
    设置在所述第一塑封层上表面与所述第二塑封层之间的介质层，所述介质层起到对所述第一布局布线层的同层布线间以及相邻层间的电绝缘和机械支撑作用；以及
    设置在覆盖除外接焊球之外的所述第二塑封层上表面的绝缘保护层。
  9. 如权利要求7所述的用于三维扇出型封装的塑封结构，其特征在于， 所述第一布局布线层的布线层数为M层，其中M≥2。
  10. 如权利要求7所述的用于三维扇出型封装的塑封结构，其特征在于，所述第二布局布线层的布线层数为N层，其中N≥2。
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