CN111834315A - 一种存储器结构及其制造方法 - Google Patents
一种存储器结构及其制造方法 Download PDFInfo
- Publication number
- CN111834315A CN111834315A CN202010740492.3A CN202010740492A CN111834315A CN 111834315 A CN111834315 A CN 111834315A CN 202010740492 A CN202010740492 A CN 202010740492A CN 111834315 A CN111834315 A CN 111834315A
- Authority
- CN
- China
- Prior art keywords
- memory
- storage
- connecting piece
- storage module
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 168
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000003860 storage Methods 0.000 claims abstract description 83
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims description 30
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 238000012858 packaging process Methods 0.000 abstract description 4
- 210000004027 cell Anatomy 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明公开了一种存储器结构及其制造方法,该结构包括:多个相同结构的存储单元;存储单元包括:存储模块,存储模块上覆盖有塑封层,存储模块底部设置有连接件,存储模块的侧边设置有金属柱,连接件延伸至存储模块的侧边,与金属柱电连接;其中,多个相同结构的存储单元堆叠设置,位于下方的存储单元通过所述金属柱与位于上方的存储单元的连接件电连接。本发明通过存储模块堆叠的方式扩大存储器的容量,无需外接引线,避免引线之间的干扰,无需通过复杂的封装工艺来实现高容量存储器的制作,也不需要复杂的芯片组装设备,封装工艺简单,成本低廉。
Description
技术领域
本发明涉及存储器技术领域,具体涉及存储器结构及其制造方法。
背景技术
在存储器技术领域,存储器的容量通常是采用存储模块叠加的方式来进行扩容。随着数字化时代的到来,对数据进行存储的需求越大越大,这也就导致了对存储器的容量需求越来越大。现有技术中,对于存储器的扩容方式,以NAND Flash封装为例,一般分为两种:一种是将存储芯片(存储模块)叠加,通过打线互连,从而实现存储器整体容量增加,如图1所示,但是这种存储芯片之间互连较长,引线之间容易干扰;另一种则是对NAND Flash芯片通过硅通孔(Through Silicon Via,TSV),进行直接互连,如图2所示。但是NAND Flash芯片需要特别定制,在流片过程中留出特殊的TSV孔,价格非常昂贵。
发明内容
因此,本发明要解决现有技术中存储芯片通过打线互连,引线之间容易干扰的问题,从而提供一种存储器的结构及其制造方法。
为达到上述目的,本发明提供如下方案:
第一方面,本发明实施例提供一种存储器结构,包括:多个相同结构的存储单元;所述存储单元包括:存储模块,所述存储模块上覆盖有塑封层,所述存储模块底部设置有连接件,所述存储模块的侧边设置有金属柱,所述连接件延伸至所述存储模块的侧边,与所述金属柱电连接;其中,所述多个相同结构的存储单元堆叠设置,位于下方的存储单元通过所述金属柱与位于上方的存储单元的连接件电连接。
在一实施例中,所述塑封层覆盖所述存储模块的上表面以及四周,位于下方的存储单元与位于上方的存储单元之间的缝隙通过填充有绝缘材料层。
在一实施例中,所述绝缘材料层为设置在所述存储单元下方的NCF膜,经过加热和加压后融化填充进位于下方的存储单元与位于上方的存储单元之间的缝隙。
在一实施例中,所述存储模块的侧边的塑封层设置有第一通孔,所述金属柱贯穿所述第一通孔。
在一实施例中,还包括:位于所述多个相同结构的存储单元顶端的盖板;位于所述多个相同结构的存储单元四周的侧壁;位于所述多个相同结构的存储单元底部的基板,其中,所述基板上设置有第二通孔,所述存储器的引出端通过所述第二通孔与位于所述基板上方的连接件连接,或者所述存储器的引出端通过所述基板内的内部线路与所述基板上的连接件连接。
在一实施例中,所述盖板下方设置有凹槽结构。
在一实施例中,所述连接件为多个,分布在所述存储模块的两侧,每个所述连接件对应设置有一个金属柱。
第二方面,本发明实施例提供一种存储器制造方法,包括:在存储模块上生成覆盖所述存储模块的塑封层;在所述存储模块底部装配延伸至所述存储模块的侧边的连接件;在所述存储模块的侧边装配与所述连接件电连接的金属柱,得到存储单元;在所述存储单元底部粘贴绝缘膜,并将所述存储单元放置在另一个具有相同结构的存储单元上;对所述绝缘膜进行加热和加压处理,使得所述绝缘膜融化形成绝缘材料层,填充在上下存储单元之间的缝隙,得到存储单元堆叠设置的存储器结构。
在一实施例中,所述在所述存储模块的侧边装配与所述连接件电连接的金属柱,包括:在所述存储模块的侧边的塑封层打孔,形成贯穿所述塑封层的第一通孔;在所述通孔内插入所述金属柱。
在一实施例中,所述在所述存储模块的侧边装配与所述连接件电连接的金属柱,其他制作方法包括:在所述存储模块内预先埋入金属柱,然后整体塑封,在塑封料表面装配连接件。
在一实施例中,还包括:制作所述存储器的盖板,盖在多个相同结构的存储单元堆叠结构的顶端;制作位于所述多个相同结构的存储单元四周的侧壁;制作位于所述多个相同结构的存储单元底部的基板,其中,所述基板上设置有第二通孔,所述存储器的引出端通过所述第二通孔与位于所述基板上方的连接件连接。
本发明技术方案,具有如下优点:本发明提供了一种存储器结构及其制造方法,首先制备单独的存储模块,然后制作单独的组装模块,最后把存储模块放入组装模块后,形成模块化的存储器。本发明实施例中,通过模块化方式,对存储器单元进行模块化制作,从而实现存储器的大容量化,因此,只要将单独制备的存储单元进行叠加,就可以实现存储器扩容,相对于现有技术中采用NAND Flash封装,通过打线互连的方式而言,芯片之间互连较短,无需外接引线,相对于现有技术对NAND Flash芯片通过TSV直接互连的方式而言,无需定制,成本较低。本发明通过单独制备存储模块,再将存储模块叠加的方式,简化了存储模块的封装工艺,降低了组装成本。
本发明通过在塑封层进行打孔,不需要存储模块在流片过程中流出特殊的TSV孔,从而降低了存储器制造成本。
附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案,下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术通过芯片堆叠打线方式实现高密度存储的结构图;
图2为现有技术通过TSV堆叠实现高密度存储的结构图;
图3为本发明实施例提供的存储单元的俯视图;
图4为本发明实施例提供的存储单元的仰视图;
图5为本发明实施例提供的存储单元的剖面图;
图6为本发明实施例提供的盖板截面图;
图7为本发明实施例提供的存储器截面图;
图8为本发明实施例提供的叠加有存储单元的存储器截面图;
图9为本发明实施例提供的存储器制造方法的流程图;
图10为本发明实施例提供的在存储模块的侧边装配金属柱的方法的流程图;
图11为本发明实施例提供的在存储模块的侧边装配金属柱另一种方法的流程图;
图12为本发明实施例提供的存储器制造方法的流程图。
具体实施方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
在本发明的描述中,需要说明的是,术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”、“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性。
在本发明的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,还可以是两个元件内部的连通,可以是无线连接,也可以是有线连接。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本发明中的具体含义。
此外,下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
本发明实施例提供一种存储器结构,包括:多个相同结构的存储单元。多个相同结构的存储单元堆叠设置,形成一个层叠结构。每个存储单元具有相同的结构,如图3-5所示,具体存储单元10包括:存储模块101,所述存储模块101上部和周围覆盖有塑封层102,所述存储模块101底部设置有连接件103,所述存储模块101的侧边设置有金属柱104,所述连接件103延伸至所述存储模块101的侧边,与所述金属柱104电连接;该连接件103也即是存储模块的RDL线路,用于连接其他存储模块。RDL线路使所述半导体封装的输入/输出(I/O)连接点在另一位置可用,其中,所述RDL导电技术线路延伸至金属柱,与所述金属柱电连接。存储单元的堆叠结构如图8所示,位于下方的存储单元通过所述金属柱104与位于上方的存储单元的连接件103电连接。
本发明实施例提供的存储器结构,通过将多个相同结构的存储单元堆叠,形成堆叠结构的存储器结构,利用位于下方的存储单元金属柱与位于上方的存储单元连接件电连接,从而增加存储器的容量,位于下方的存储单元通过所述金属柱与位于上方的存储单元的连接件电连接,无需在各存储模块之间外接引线,从而可以避免引线之间互相干扰的问题。
本发明金属柱设置在塑封层的侧边,与所述塑封层贴合;也可以是在塑封层中形成通孔,将金属柱贯穿所述通孔,从而形成稳定的连接结构。或者在所述存储模块内预先埋入金属柱,然后整体塑封。
作为一种可选的实施方式,所述存储模块的侧边的塑封层设置有第一通孔,所述金属柱贯穿所述第一通孔。金属柱为导电材料,可以是铜(Cu)也可以是铝(Al),本发明不做限定。
本发明实施例中,通过在塑封层进行打孔,或者在存储模块内预先埋入金属柱。不需要存储模块在流片过程中留出特殊的TSV孔,从而降低了存储器制造成本。
可选地,如图3所示,所述塑封层102覆盖所述存储模块的上表面以及四周,位于下方的存储单元101与位于上方的存储单元101之间的缝隙通过填充有绝缘材料层105’,从而形成对所述存储模块的密封结构,每个存储模块通过连接件103引出。
进一步可选地,上述实施例中,所述绝缘材料层105’为设置在所述存储单元下方的NCF膜105加热和加压后融化填充进位于下方的存储单元与位于上方的存储单元之间的缝隙。
可选地,如图4所示,所述连接件103为多个,分布在所述存储模块的两侧,每个所述连接件对应设置有一个金属柱(图中未示出)。
非导电粘合膜(NCF膜)是将存储单元表面塑封层和存储单元底部粘合在一起的绝缘膜,主要用作底部填充的粘合材料。
本发明实施例通过将粘贴在存储模块底部的NCF膜加热加压融化,使其填充位于下方的存储单元与位于上方的存储单元之间的缝隙,有利于填充细小的空隙或凸点节距,同时也有利于对存储单元进行固定。
如图6-7所示,所述存储器结构还包括:位于所述多个相同结构的存储单元101顶端的盖板201,盖板下方设置有凹槽结构;位于所述多个相同结构的存储单元101四周的侧壁202;位于所述多个相同结构的存储单元101底部的基板203,其中,所述基板203上设置有第二通孔204,所述存储器的引出端205通过所述第二通孔与位于所述基板上方的连接件连接,或者所述存储器的引出端205通过所述基板内的内部线路与所述基板上的连接件连接。。
图6-7是根据本发明实施例提供的存储器结构示意图,如图6-7所示,所述存储器结构包括:盖板201、侧壁202和基板203。盖板201、侧壁202和基板203形成一个内部为空腔的结构,制作存储器时,将存储单元置于空腔结构内部中,存储单元底部的基板上有第二通孔204,用于连接存储器的引出端205和位于基板上方的连接件。当存储模块装入存储器中时,将存储模块底部的NCF材料加热加压使其融化,形成绝缘材料层105’,填充引出端与整体框架之间的空隙,同时对存储模块进行固定。
本发明实施例提供的存储器结构,利用侧壁和基板形成一个空腔结构,放置存储模块后,添加上盖,从而形成最终结构。存储模块数量根据实际存储容量需求决定,比如单个模块16G,存储容量需求32G,即放置两块存储模块,便于定制存储容量。
实施例2
本发明实施例提供一种存储器制造方法,该方法用于制造发明上述实施例1中所述的存储器结构,具体地,如图9-12所示,该存储器制造方法包括:
步骤S301,在存储模块上生成覆盖所述存储模块的塑封层;
步骤S302,在所述存储模块底部装配延伸至所述存储模块的侧边的连接件;
步骤S303,在所述存储模块的侧边装配与所述连接件电连接的金属柱,得到存储单元;
步骤S304,在所述存储单元底部粘贴绝缘膜,并将所述存储单元放置在另一个具有相同结构的存储单元上;
步骤S305,对所述绝缘膜进行加热和加压处理,使得所述绝缘膜融化形成绝缘材料层,填充在上下存储单元之间的缝隙,得到存储单元堆叠设置的存储器结构。
作为一种可选的实施方式,所述在所述存储模块的侧边装配与所述连接件电连接的金属柱,如图10所示,包括:
步骤S3031,在所述存储模块的侧边的塑封层打孔,形成贯穿所述塑封层的第一通孔;
步骤S3032,在所述通孔内插入所述金属柱。作为一种可选的实施方式,所述在所述存储模块的侧边装配与所述连接件电连接的金属柱,如图11所示,包括:
步骤S3033,首先在所述存储模块内预先埋入金属柱,然后整体塑封,然后露出金属柱;
步骤S3034,在塑封后的存储模块表面装配连接件。
作为一种可选的实施方式,所述存储器还包括:
步骤S401,制作所述存储器的盖板,盖在多个相同结构的存储单元堆叠结构的顶端;
步骤S402,制作位于所述多个相同结构的存储单元四周的侧壁;
步骤S403,制作位于所述多个相同结构的存储单元底部的基板,其中,所述基板上设置有第二通孔,所述存储器的引出端通过所述第二通孔与位于所述基板上方的连接件连接,或者所述存储器的引出端通过所述基板内的内部线路与所述基板上的连接件连接。
本发明技术方案,具有如下优点:本发明提供了一种存储器结构及其制造方法,首先制备单独的存储模块,然后制作单独的组装模块,最后把存储模块放入组装模块后,形成模块化的存储器。本发明实施例中,通过模块化方式,对存储器单元进行模块化制作,从而实现存储器的大容量化,因此,只要将单独制备的存储单元进行叠加,就可以实现存储器扩容,相对于现有技术中采用NAND Flash封装,通过打线互连的方式而言,芯片之间互连较短,无需外接引线相对于现有技术对NAND Flash芯片通过TSV直接互连的方式而言,无需定制,成本较低。本发明通过单独制备存储模块,再将存储模块叠加的方式,简化了存储模块的封装工艺,降低了组装成本。
本发明通过在塑封层进行打孔,不需要存储模块在流片过程中留出特殊的TSV孔,从而降低了存储器制造成本。
显然,上述实施例仅仅是为清楚地说明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明创造的保护范围之中。
Claims (11)
1.一种存储器结构,其特征在于,包括:多个相同结构的存储单元;所述存储单元包括:存储模块,所述存储模块上覆盖有塑封层,所述存储模块底部设置有连接件,所述存储模块的侧边设置有金属柱,所述连接件延伸至所述存储模块的侧边,与所述金属柱电连接;
其中,所述多个相同结构的存储单元堆叠设置,位于下方的存储单元通过所述金属柱与位于上方的存储单元的连接件电连接。
2.根据权利要求1所述的存储器结构,其特征在于,所述塑封层覆盖所述存储模块的上表面以及四周,位于下方的存储单元与位于上方的存储单元之间的缝隙通过填充有绝缘材料层。
3.根据权利要求2所述的存储器结构,其特征在于,所述绝缘材料层为设置在所述存储单元下方的NCF膜,经过加热和加压后融化填充进位于下方的存储单元与位于上方的存储单元之间的缝隙。
4.根据权利要求2所述的存储器结构,其特征在于,所述存储模块的侧边的塑封层设置有第一通孔,所述金属柱贯穿所述第一通孔。
5.根据权利要求1所述的存储器结构,其特征在于,还包括:
位于所述多个相同结构的存储单元顶端的盖板;
位于所述多个相同结构的存储单元四周的侧壁;
位于所述多个相同结构的存储单元底部的基板,其中,所述基板上设置有第二通孔,所述存储器的引出端通过所述第二通孔与位于所述基板上方的连接件连接,或者所述存储器的引出端通过所述基板内的内部线路与所述基板上的连接件连接。
6.根据权利要求5所述的存储器结构,其特征在于,所述盖板下方设置有凹槽结构。
7.根据权利要求1所述的存储器结构,其特征在于,所述连接件为多个,分布在所述存储模块的两侧,每个所述连接件对应设置有一个金属柱。
8.一种存储器制造方法,其特征在于,包括:
在存储模块上生成覆盖所述存储模块的塑封层;
在所述存储模块底部装配延伸至所述存储模块的侧边的连接件;
在所述存储模块的侧边装配与所述连接件电连接的金属柱,得到存储单元;
在所述存储单元底部粘贴绝缘膜,并将所述存储单元放置在另一个具有相同结构的存储单元上;
对所述绝缘膜进行加热和加压处理,使得所述绝缘膜融化形成绝缘材料层,填充在上下存储单元之间的缝隙,得到存储单元堆叠设置的存储器结构。
9.根据权利要求8所述的存储器制造方法,其特征在于,所述在所述存储模块的侧边装配与所述连接件电连接的金属柱,包括:
在所述存储模块的侧边的塑封层打孔,形成贯穿所述塑封层的第一通孔;
在所述通孔内插入所述金属柱。
10.根据权利要求8所述的存储器制造方法,其特征在于,所述在所述存储模块的侧边装配与所述连接件电连接的金属柱,包括:
在所述存储模块内预先埋入金属柱,然后整体塑封,在塑封料表面装配连接件。
11.根据权利要求8所述的存储器制造方法,其特征在于,还包括:
制作所述存储器的盖板,盖在多个相同结构的存储单元堆叠结构的顶端;
制作位于所述多个相同结构的存储单元四周的侧壁;
制作位于所述多个相同结构的存储单元底部的基板,其中,所述基板上设置有第二通孔,所述存储器的引出端通过所述第二通孔与位于所述基板上方的连接件连接。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010740492.3A CN111834315A (zh) | 2020-07-28 | 2020-07-28 | 一种存储器结构及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010740492.3A CN111834315A (zh) | 2020-07-28 | 2020-07-28 | 一种存储器结构及其制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111834315A true CN111834315A (zh) | 2020-10-27 |
Family
ID=72919833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010740492.3A Pending CN111834315A (zh) | 2020-07-28 | 2020-07-28 | 一种存储器结构及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111834315A (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009260230A (ja) * | 2008-03-21 | 2009-11-05 | Hitachi Chem Co Ltd | 半導体装置の製造方法 |
CN104282586A (zh) * | 2013-07-02 | 2015-01-14 | 库利克和索夫工业公司 | 用于热压接合器的接合头、热压接合器及其操作方法 |
US20150279431A1 (en) * | 2014-04-01 | 2015-10-01 | Micron Technology, Inc. | Stacked semiconductor die assemblies with partitioned logic and associated systems and methods |
CN110690178A (zh) * | 2019-10-29 | 2020-01-14 | 中国电子科技集团公司第五十八研究所 | 一种dram存储芯片三维集成封装方法及结构 |
CN110828431A (zh) * | 2019-12-06 | 2020-02-21 | 上海先方半导体有限公司 | 一种用于三维扇出型封装的塑封结构 |
-
2020
- 2020-07-28 CN CN202010740492.3A patent/CN111834315A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009260230A (ja) * | 2008-03-21 | 2009-11-05 | Hitachi Chem Co Ltd | 半導体装置の製造方法 |
CN104282586A (zh) * | 2013-07-02 | 2015-01-14 | 库利克和索夫工业公司 | 用于热压接合器的接合头、热压接合器及其操作方法 |
US20150279431A1 (en) * | 2014-04-01 | 2015-10-01 | Micron Technology, Inc. | Stacked semiconductor die assemblies with partitioned logic and associated systems and methods |
CN110690178A (zh) * | 2019-10-29 | 2020-01-14 | 中国电子科技集团公司第五十八研究所 | 一种dram存储芯片三维集成封装方法及结构 |
CN110828431A (zh) * | 2019-12-06 | 2020-02-21 | 上海先方半导体有限公司 | 一种用于三维扇出型封装的塑封结构 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101019793B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US7514297B2 (en) | Methods for a multiple die integrated circuit package | |
US7863755B2 (en) | Package-on-package system with via Z-interconnections | |
US8030135B2 (en) | Methods for a multiple die integrated circuit package | |
US8049314B2 (en) | Integrated circuit package system with insulator over circuitry | |
US7935569B2 (en) | Components, methods and assemblies for stacked packages | |
CN103201836B (zh) | 具有面阵单元连接体的可堆叠模塑微电子封装 | |
KR101653856B1 (ko) | 반도체 장치 및 그 제조방법 | |
US20130049221A1 (en) | Semiconductor package having plural semiconductor chips and method of forming the same | |
CN103283019A (zh) | 半导体装置 | |
US7834469B2 (en) | Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame | |
JP2000269408A (ja) | 半導体装置及びその製造方法 | |
US9917073B2 (en) | Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package | |
TWI404190B (zh) | 具有非對稱配置晶粒與模製之堆疊封裝之多重封裝模組 | |
CN111052366A (zh) | 具有保护机制的半导体装置及其相关系统、装置及方法 | |
CN102110672A (zh) | 芯片堆叠封装结构及其制造方法 | |
CN111834315A (zh) | 一种存储器结构及其制造方法 | |
CN114334851A (zh) | 一种扇出型封装结构及其制备方法 | |
JP2005302815A (ja) | 積層型半導体パッケージおよびその製造方法 | |
US20090020886A1 (en) | Semiconductor device and method of fabricating the same | |
KR100996982B1 (ko) | 다중 다이 집적회로 패키지 | |
CN215600359U (zh) | Pop封装结构和pop封装堆叠结构 | |
JP2008277571A (ja) | 半導体パッケージ | |
CN114284161A (zh) | 半导体芯片封装方法及芯片封装结构 | |
CN115050706A (zh) | 芯片封装结构、电子设备和芯片封装结构的封装方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201027 |