CN111052366A - 具有保护机制的半导体装置及其相关系统、装置及方法 - Google Patents

具有保护机制的半导体装置及其相关系统、装置及方法 Download PDF

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CN111052366A
CN111052366A CN201880056037.2A CN201880056037A CN111052366A CN 111052366 A CN111052366 A CN 111052366A CN 201880056037 A CN201880056037 A CN 201880056037A CN 111052366 A CN111052366 A CN 111052366A
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die
enclosure
substrate
semiconductor device
interconnects
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CN111052366B (zh
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周卫
B·K·施特雷特
M·E·塔特尔
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明揭示一种半导体装置，其包含：衬底，其包含衬底顶面；互连件，其经连接到所述衬底且在所述衬底顶面上方延伸；裸片，其经附接于所述衬底上方，其中所述裸片包含连接到用于电耦合所述裸片及所述衬底的所述互连件的裸片底面；及金属围封体，其直接接触所述衬底顶面及所述裸片底面，且垂直延伸于所述衬底顶面与所述裸片底面之间，其中所述金属围封体沿外围包围所述互连件。

Description

具有保护机制的半导体装置及其相关系统、装置及方法
技术领域
本技术涉及半导体装置，且特定来说，本技术涉及具有保护机制的半导体装置。
背景技术
半导体装置裸片(其包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装于另一结构(例如衬底、另一裸片等等)上且由塑料保护覆盖层包覆的半导体裸片。裸片包含功能构件(例如用于存储器单元、处理器电路及成像器装置)以及电连接到功能构件的互连件。互连件可电连接到保护覆盖层外的端子以将裸片连接到较高级电路。
如图1中所说明，半导体装置100(例如三维互连(3DI)型装置或半导体封装装置)可包含裸片102，其上具有连接到衬底结构106(例如印刷电路板(PCB)、半导体或晶片级衬底、另一裸片等等)的裸片互连件104，衬底结构106上具有衬底互连件108。裸片102及衬底结构106可通过裸片互连件104及衬底互连件108来彼此电耦合。此外，裸片互连件104及衬底互连件108可彼此直接接触(例如，通过接合工艺，例如扩散接合或混合接合)或通过中间结构(例如焊料)来彼此接触。半导体装置100可进一步包含包围或囊封裸片102、裸片互连件104、衬底结构106、衬底互连件108、其部分或其组合的囊封物，例如底部填胶110。
随着其它领域的技术进步及应用增加，市场在不断寻求更快且更小装置。为满足市场需求，不断将半导体装置的物理大小及尺寸推向极限。举例来说，我们一直致力于减小裸片102与衬底结构106之间的间距(例如，对于3DI装置及裸片堆叠封装)。
然而，归因于各种因素(例如底部填胶110的粘度、滞留空气/气体、底部填胶110的不均匀流动、互连件之间的空间等等)，囊封工艺可能并不可靠，例如在裸片102与衬底结构106之间留下空隙114(例如，其中互连件的部分无法直接接触底部填胶110)。空隙114会引起互连件之间(例如衬底互连件108之间及/或裸片互连件104之间)的短路及泄漏，其进而引起半导体装置100的电气故障。此外，制造成本会随着装置逐渐变小而增加(例如，基于使用纳米颗粒底部填胶而非传统底部填胶)。
附图说明
图1是根据现有技术的半导体装置的横截面图。
图2是根据本技术的实施例的半导体装置的沿图3中的线2-2的横截面图。
图3是根据本技术的实施例的图2的半导体装置的平面图。
图4是根据本技术的实施例的半导体装置的沿图5中的线4-4的横截面图。
图5是根据本技术的实施例的图4的半导体装置的平面图。
图6是根据本技术的实施例的半导体装置的沿图7中的线6-6的横截面图。
图7是根据本技术的实施例的半导体装置的沿图6中的线7-7的横截面图。
图8到11是说明根据本技术的实施例的制造方法中的选定阶段中的半导体装置的横截面图。
图12到15是说明根据本技术的实施例的另一制造方法中的选定阶段中的半导体装置的横截面图。
图16是说明根据本技术的实施例的制造半导体装置的实例方法的流程图。
图17是说明根据本技术的实施例的并入半导体装置的系统的框图。
具体实施方式
本文中所揭示的技术涉及半导体装置、具有半导体装置的系统及用于制造半导体装置的相关方法。术语“半导体装置”大体上是指包含一或多个半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置及二极管等等。此外，术语“半导体装置”可指代完成装置或变成完成装置之前的各种处理阶段中的组合件或其它结构。取决于其使用背景，术语“衬底”可指代支撑电子元件(例如裸片)的结构(例如晶片级衬底)或指代单粒化裸片级衬底或用于裸片堆叠或3DI应用的另一裸片。所属领域的一般技术人员将认识到，可在晶片级或裸片级处执行本文中所描述的方法的合适步骤。此外，除非上下文另有指示，否则可使用常规半导体制造技术来形成本文中所揭示的结构。可(例如)使用化学气相沉积、物理气相沉积、原子层沉积、旋转涂布及/或其它合适技术来沉积材料。类似地，可(例如)使用等离子体蚀刻、湿式蚀刻、化学机械平坦化或其它合适技术来移除材料。
下文将在保护半导体裸片及相关电连接件的背景下描述本技术的许多实施例。举例来说，半导体装置(例如3DI封装方案)可各自包含半导体裸片，其上具有连接到衬底结构的数个裸片互连件。为保护裸片及裸片互连件(例如，免受例如湿气、残屑等等的环境因素影响)，半导体装置可各自包含沿水平面包围裸片互连件的金属(例如铜、铝、合金等等)围封体。金属围封体可进一步垂直延伸于裸片与衬底之间及/或直接接触裸片及衬底以围封裸片互连件。因而，半导体装置可使用金属围封体替代任何囊封物(例如底部填胶)来使裸片互连件与周围外部空间及/或环境隔离。
在一些实施例中，可基于铜上覆铜(Cu-Cu)接合(例如，例如基于扩散接合技术)来形成金属围封体。在一些实施例中，金属围封体可包含焊料。
在一些实施例中，每一半导体装置可包含多个围封体。举例来说，半导体装置可包含一组同心围封体。还举例来说，半导体装置可包含各自具有不同形状及/或尺寸的一组围封体。一些围封体可用于载送信号或电平面(例如用于电源连接、接地平面等等)。
如本文中所使用，术语“垂直”、“横向”、“上”及“下”可指代鉴于图中所展示的定向的半导体裸片组合件中的构件的相对方向或位置。举例来说，“上”或“最上”可指代定位成比另一构件更接近于页的顶部的构件。然而，这些术语应被广义解释为包含具有其它定向(例如其中顶部/底部、上方/下方、上/下及左/右可取决于定向而互换的相反或倾斜定向)的半导体装置。
图2是根据本技术的实施例的半导体装置200(例如包含3DI装置或裸片堆叠封装的半导体裸片组合件)的沿图3中的线2-2的横截面图。半导体装置200可包含安装于衬底206(例如另一裸片)上或连接到衬底206的半导体裸片202(“裸片202”)。裸片202可通过金属或导电互连件204(“互连件204”)电连接到衬底206。在一些实施例中，互连件204可为由将从裸片202突出的支柱、衬垫或互连结构接合或结合(例如，例如通过扩散接合或混合接合)到从衬底206突出的对应结构所致的结构。
半导体装置200可包含沿水平面连续包围或围封互连件204的金属(例如铜、铝、合金等等)围封体结构210(“围封体210”)。围封体210(例如形成沿外围包围互连件204的壁的连续固体金属结构)可进一步从裸片底面222延伸到衬底顶面224且直接接触裸片底面222及衬底顶面224以围封内部空间226(“围封空间226”)。除互连件204之外，围封空间226可为真空或填充有惰性或特定气体(例如，其内无任何囊封材料或底部填胶)。因此，围封体210可使互连件204与围封体210外侧上的外部空间隔离。
在一些实施例中，围封体210可定位于与裸片外围边缘230的边缘偏移距离228(例如沿水平方向测量的距离)处。在一些实施例中，围封体210可经定位使得其边缘或表面沿垂直面或垂直线与裸片外围边缘230共面或重合(例如，其中边缘偏移距离228是0)。
图3是根据本技术的实施例的图2的半导体装置200的平面图。图3可对应于无图2的衬底206的半导体装置200的仰视图。如上文所论述，围封体210可沿平面环绕互连件204的外围或周边。
为了说明，围封体210经展示为具有矩形形状、均匀厚度或宽度且与裸片202的形状或轮廓同心。然而，应了解，围封体210可为不同的。举例来说，围封体210可具有椭圆形状、不规则或不对称形状，或任何N边多边形形状。还举例来说，围封体210可在不同部分处具有变动厚度或宽度。还举例来说，围封体210可相对于互连件204或其布置、裸片202的形状或轮廓或其组合偏移或偏心。
围封体210使半导体装置的总大小减小。由于无需底部填胶，所以可减小接合线厚度，从而导致多裸片堆叠的极低封装高度。此外，排除焊料的围封体210(例如固体铜结构，例如由Cu-Cu扩散接合所致)因无需形成支柱凸块而降低制造成本。此外，排除焊料的围封体210因提供无焊料帽的纯净接头而降低故障率，此消除与焊料桥接、崩移、匮乏、金属间化合物(IMC)、电磁(EM)效应等等相关联的故障模式。
围封体210还因封装高度降低而降低制造成本及故障率。围封体210可保护及隔离互连件204免受环境因素(例如湿气、残屑等等)影响，此消除对底部填胶(例如纳米颗粒底部填胶)的需要。因此，可基于使用围封体210替换底部填胶来消除与底部填胶叠层或流动工艺相关联的成本及错误率，两者随裸片底面222与衬底顶面224之间的空间减小而快速提高。此外，围封体210提供满足先前由底部填胶提供的机械、热及电特性或益处的接头。
图4是根据本技术的实施例的半导体装置400(例如包含3DI装置或裸片堆叠封装的半导体裸片组合件)的沿图5中的线4-4的横截面图。类似于图2的半导体装置200，半导体装置400可包含经安装于或经连接到衬底406(例如另一裸片)上的半导体裸片402(“裸片402”)及垂直延伸以直接接触且电耦合裸片402及衬底406的金属或导电互连件404(“互连件404”)。
半导体装置400可包含金属围封体(例如图2的围封体210)的多个例子。举例来说，半导体装置400可具有包含金属(例如铜、铝、合金等等)的第一围封体412及第二围封体414。第一围封体412及第二围封体414两者可为形成壁的连续固体金属结构。金属围封体中的至少一者或全部(例如第一围封体412、第二围封体414或其它额外金属围封体)可沿外围包围互连件204且使互连件204与围封体210外侧上的外部空间隔离。
在一些实施例中，第一围封体412可为内围封体且第二围封体414可为外围封体。举例来说，第一围封体412可定位成比第二围封体414更接近于互连件404，其中第一围封体412定位于互连件404与第二围封体414之间。第一围封体412可沿水平面沿外围包围或环绕互连件404。第二围封体414还可沿水平面沿外围包围或环绕第一围封体412且借此沿水平面沿外围包围或环绕互连件404。
类似于半导体装置200，半导体装置400可使内部空间(例如由第二围封体414环绕的第二空间及由第一围封体412环绕的第一空间，其中第一空间及第二空间可重叠)与围封体外的空间隔离。除互连件404之外，围封空间中的一或多者可为空隙(例如，其内无任何囊封材料或底部填胶)。因此，围封体210可在无需使用底部填胶或其它囊封物的情况下使互连件204与外部空间及对应环境因素隔离。
为了说明，半导体装置400的最外围封体(例如图4中所说明的第二围封体414)经展示为从裸片402的外围边缘或表面(例如裸片外围边缘230)向内定位(例如，借此根据图2的边缘偏移距离228来产生裸片402的外围部分的悬伸)。然而，应了解，最外围封体可定位成使外表面或远端表面(例如，相对于裸片402及/或互连件404的中心部分)与裸片402的外围边缘或表面重合(例如，借此产生跨裸片外围表面、最外围封体的外表面及衬底外围表面的齐平或连续外外围表面)。
图5是根据本技术的实施例的图4的半导体装置400的平面图。图5可对应于无图4的衬底406的半导体装置400的仰视图。如上文所论述，第一围封体412、第二围封体414或其组合可沿平面环绕互连件204的外围或周边。第二围封体414可沿平面进一步环绕第一围封体412的外围或周边。
第一围封体412可具有第一形状502(例如横截面轮廓的形状)且第二围封体414可具有类似于或不同于第一形状502的第二形状504。为了说明，使用圆或椭圆来展示第一形状502且使用矩形来展示第二形状504。然而，应了解，第一形状502及第二形状504可为不同的(例如，例如呈不规则或不对称形状或任何N边多边形形状)。
还为了说明，第一围封体412及第二围封体414经展示为具有相对于彼此及裸片402的同心布置506。然而，应了解，第一围封体412及第二围封体414可彼此偏移及/或从裸片402偏移而呈非同心布置。在一些实施例中，多个围封体可电浮动(例如，无到裸片402中的电路的任何电连接)或连接到信号或电电平(例如电源或接地)。举例来说，第一围封体412可具有第一电连接512(例如作用信号、电源、接地等等)且第二围封体414可具有第二电连接514(例如作用信号、电源、接地等等)。第一电连接512及第二电连接514可连接到相同或不同电平或信号。在一些实施例中，内电连接中的一者(例如图5中所说明的第一电连接512)可到电源/电压源且最外电连接(例如图5中所说明的第二电连接514)可到电接地。在一些实施例中，最内电连接可到接地及/或最外电连接可到电源/电压源。
还为了说明，第一围封体412及第二围封体414经展示为嵌套的(例如，其中第二围封体414环绕第一围封体412)。然而，应了解，第一围封体412及第二围封体414可为非嵌套的(例如，布置为非同心形状、重叠或非重叠形状或其组合)。
电连接金属围封体来传送电压(例如共同电源电压或接地)及/或信号提高半导体装置的效率。举例来说，可从互连件移除电压电平及/或接地，借此允许互连件传送更多信号。还举例来说，可基于互连件与围封体之间的距离或布置来使特定信号(例如噪声源)与互连件分离超过互连件之间所允许的间隔。此外，将金属围封体电连接到电连接(例如接地)可进一步减少与噪声或电磁干扰(EMI)相关联的错误。
图6是根据本技术的实施例的半导体装置600(例如包含3DI装置或裸片堆叠封装的TSV裸片组合件)的沿图7中的线6-6的横截面图。半导体装置600可包含多个堆叠裸片(例如第一裸片601、第二裸片602、额外裸片、衬底606等等)。类似于图2的半导体装置200及/或图4的半导体装置400，第一裸片601及第二裸片602可安装于或连接到衬底606(例如PCB或另一裸片)上。如图6中所说明，第一裸片601可直接附接到第二裸片602且直接位于第二裸片602上方，及第二裸片602可直接附接到衬底606且直接位于衬底606上方。
金属或导电互连件(例如第一顶部互连件603、第二顶部互连件604、底部互连件605等等)可垂直延伸以直接接触及电耦合裸片。如图6中所说明，第一顶部互连件603及/或第二顶部互连件604可垂直延伸于第一裸片601与第二裸片602之间且直接接触第一裸片601及第二裸片602。此外，底部互连件605可垂直延伸于第二裸片602与衬底606之间且直接接触第二裸片602及衬底606。
此外，类似于半导体装置200及/半导体装置400，一或多组互连件可由一或多个金属围封体(图2的围封体210、图4的第一围封体412、图4的第二围封体414等等)环绕或沿外围包围。举例来说，半导体装置600可包含第一顶部围封体612、第二顶部围封体614、第三顶部围封体616、第一底部围封体618、第二底部围封体620或其组合。如图6中所说明，第一顶部围封体612可环绕或包围第一顶部互连件603，且第二顶部围封体614可环绕第二顶部互连件604且与第一顶部围封体612分离(例如，使围封体呈非嵌套配置)。在一些实施例中，第三顶部围封体616可环绕或包围第一顶部围封体612及/或第二顶部围封体614。类似地，如图5及6中所说明，第一底部围封体618可环绕或包围底部互连件605且第二底部围封体620可环绕或包围第一底部围封体618。
在一些实施例中，裸片可在无需通过定位于耦合裸片之间的介入裸片中的电路来路由的情况下彼此直接电连接。举例来说，互连件可绕过中间裸片(例如，在中间裸片的外围边缘(其不延伸到中间裸片上方及中间裸片下方的外裸片的外围边缘)外)而直接接触外裸片。还举例来说，裸片中的一或多者可包含一或多个TSV 608(例如完全穿过其上裸片的垂直互连件)。基于TSV 608，外裸片可彼此直接电连接(例如，无需通过中间裸片中的电路来路由)，同时使电信号或电平通过中间裸片。TSV 608可电接触互连件(例如第一顶部互连件603、第二顶部互连件604、底部互连件605等等)、围封体(例如第一顶部围封体612、第二顶部围封体614、第三顶部围封体616、第一底部围封体618、第二底部围封体620等等)或其组合。
图7是根据本技术的实施例的半导体装置600的沿图6中的线7-7的横截面图。图7可对应于无图6的第一裸片601的半导体装置600的俯视图。
如上文所论述，一或多个金属围封体可为嵌套或同心的(例如图5中所说明)、非嵌套的、重叠的或其组合。举例来说，围封体可为非嵌套的，例如由第一顶部围封体612及第二顶部围封体614所说明。第一顶部围封体612可环绕或包围第一顶部互连件603，且第二顶部围封体614可环绕第二顶部互连件604且与第一顶部围封体612分离(例如，使围封体呈非嵌套配置)。还举例来说，围封体可为嵌套的(例如，呈同心或非同心布置)，例如在第一顶部围封体612与第三顶部围封体616之间及/或第二顶部围封体614与第三顶部围封体616之间所说明。第三顶部围封体616可环绕或包围第一顶部围封体612及第二顶部围封体614。还举例来说，围封体的部分可彼此重叠，例如由围封体重叠部分702所说明。可基于使两个单独且共面围封体重叠来配置第三顶部围封体616，其中重叠形成围封体重叠部分702。
将金属围封体电连接到TSV 608减小封装大小。具有电连接(例如，到信号、电源、接地等等)的围封体与TSV 608之间的直接接触可允许通过允许介入裸片的电路的通过来增大连接可能性。
图8到9是说明根据本技术的实施例的制造方法中的选定阶段中的半导体装置的横截面图。如图8中所说明，方法可包含提供裸片802(例如图2的裸片202或图4的裸片402)的阶段。裸片802可包含在裸片底面(例如图2的裸片底面222)突出的裸片互连件804(例如用于提供到裸片802内的电路的电连接的固体金属结构，例如针对图2的互连件204的部分或图4的互连件404的部分)。裸片802可进一步包含沿水平面环绕裸片互连件804的周边的裸片围封体810(例如固体金属结构，例如针对图2的金属围封体结构210的部分、图4的第一围封体412或图4的第二围封体414的部分等等)。
可使用单独制造工艺(例如晶片或裸片级制造工艺)来制造具有裸片互连件804及裸片围封体806的裸片802。单独制造工艺可根据突出测量812(例如金属结构的高度，例如裸片底面222与裸片互连件804及裸片围封体806的远端部分之间所测量的长度)来产生裸片互连件804及裸片围封体806。在一些实施例中，突出测量812可包含小于20μm的距离。根据突出测量812，裸片互连件804及裸片围封体806的远端部分(例如相对于裸片底面222)可沿与裸片底面222平行的水平面呈共面。
如图9中所说明，方法可包含提供衬底906(例如图2的衬底206或图4的衬底406)的阶段。衬底906可包含在衬底顶面(例如图2的衬底顶面224)上方突出的衬底互连件904(例如用于提供到衬底906的电连接的固体金属结构，例如针对图2的互连件204的部分，或图4的互连件404的部分)。衬底906可进一步包含沿水平面环绕衬底互连件904的周边的衬底围封体910(例如固体金属结构，例如针对图2的金属围封体结构210的部分、图4的第一围封体412或图4的第二围封体414的部分等等)。
可使用单独制造工艺(例如晶片或裸片级制造工艺或用于制造印刷电路板的工艺)来制造具有衬底互连件904及衬底围封体910的衬底906(例如具有互连件及围封体的另一裸片，例如图8中所说明)。类似于图8中所说明的阶段，单独制造工艺可根据突出测量912(例如金属结构的高度，例如衬底顶面224与衬底互连件904及衬底围封体910的远端部分之间所测量的长度)来产生衬底互连件904及衬底围封体910。在一些实施例中，突出测量912可包含小于20μm的距离。根据突出测量912，衬底互连件904及衬底围封体910的远端部分(例如相对于衬底顶面224)可沿与衬底顶面224平行的水平面呈共面。
如图10中所说明，方法可包含使衬底906及裸片802对准的阶段。可基于沿线或平面(例如图10的垂直线或垂直面)使衬底906及裸片802的参考部分(例如中心部分、外围边缘或表面等等)对准来对准衬底906及裸片802。结构可经对准使得裸片围封体810及衬底围封体910沿线或平面(例如垂直线或垂直面)对准。此外，结构可经对准使得裸片围封体810及衬底围封体910彼此直接接触。可类似地使裸片互连件804及衬底互连件904对准。
如图11中所说明，方法可包含接合金属结构(例如，将裸片围封体810接合到衬底围封体910及/或将裸片互连件804接合到衬底互连件904)的阶段。举例来说，图11可表示扩散接合工艺1100(例如Cu-Cu扩散接合)，其包含基于固态扩散来结合金属的固态焊接工艺。扩散接合工艺1100可包含产生真空条件或使用惰性气体来填充空间(例如围封空间)、加热金属结构、将金属结构压合在一起或其组合。
基于接合阶段，金属结构可接合或融合而形成连续结构。举例来说，可接合裸片围封体810及衬底围封体910以形成图2的围封体210、图4的第一围封体412或图4的第二围封体414。还举例来说，可接合裸片互连件804及衬底互连件904以形成图2的互连件204或图4的互连件404。
将裸片围封体810扩散接合到衬底围封体910(例如Cu-Cu扩散接合)且将裸片互连件804扩散接合到衬底互连件904(例如Cu-Cu扩散接合)会降低制造故障及成本。扩散接合工艺可消除焊料，借此降低与焊接工艺相关联的任何潜在故障及成本。此外，可使用一种接合工艺来接合互连件及围封体，这可进一步简化制造工艺。
图12到15是说明根据本技术的实施例的另一制造方法中的选定阶段中的半导体装置的横截面图。如图12中所说明，方法可包含提供裸片1202(例如图2的裸片202或图4的裸片402)的阶段。类似于图6中所说明的阶段，裸片1202可包含在裸片底面(例如图2的裸片底面222)突出的裸片互连件1204(例如用于提供到裸片602内的电路的电连接的固体金属结构，例如针对图2的互连件204的部分或图4的互连件404的部分)。
裸片1202可进一步包含沿水平面环绕裸片互连件1204的周边的裸片围封体1210(例如固体金属结构，例如针对图2的金属围封体结构210的部分、图4的第一围封体412或图4的第二围封体414的部分等等)。在一些实施例中，裸片围封体1210可包含附接于远离裸片底面222延伸的金属壁的远端部分(例如，相对于裸片底面222)处的焊料1220。在一些实施例中，裸片围封体1210可包含直接接触裸片底面222的焊料1220(Cu或Cu+焊料尖端)(例如，其中裸片围封体1210由焊料1220形成)。在一些实施例中，裸片围封体1210可为块状焊料(例如，无任何分离金属壁结构)。
如图13中所说明，方法可包含提供衬底1306(例如图2的衬底206或图4的衬底406)的阶段。类似于图7中所说明的阶段，衬底1306可包含在衬底顶面(例如图2的衬底顶面224)上方突出的衬底互连件1304(例如用于提供到衬底1306的电连接的固体金属结构，例如针对图2的互连件204的部分或图4的互连件404的部分)。衬底1306可进一步包含沿水平面环绕衬底互连件1304的周边的衬底围封体1310(例如固体金属结构，例如针对图2的金属围封体结构210的部分、图4的第一围封体412或图4的第二围封体414的部分等等)。
在一些实施例中，衬底围封体1310可包含图12的焊料1220。举例来说，衬底围封体1310可由焊料1220形成(例如，其中焊料1220直接接触衬底顶面224)。还举例来说，衬底围封体1310可包含附接于远离衬底顶面224延伸的金属壁的远端部分(例如，相对于衬底顶面224)处的焊料1220。还举例来说，焊料1220可包含于衬底围封体1310而非裸片围封体1210中或包含于衬底围封体1310及裸片围封体1210两者中。
如图14中所说明，方法可包含使衬底1306及裸片1202对准的阶段。类似于图8中所说明的阶段，可基于沿线或平面使衬底1306及裸片1202的参考部分(例如中心部分、外围边缘或表面等等)对准来对准衬底1306及裸片1202，其中沿另一线或平面(例如，沿垂直方向)对准裸片围封体1210及衬底围封体1310。此外，结构可经对准使得裸片围封体1210及衬底围封体1310彼此直接接触(例如，其中焊料1220与衬底围封体1310直接接触)。可类似地使裸片互连件1204及衬底互连件1304对准。
如图15中所说明，方法可包含接合金属结构(例如，将图14的裸片围封体1210接合到图14的衬底围封体1310及/或将图14的裸片互连件1204接合到图14的衬底互连件1304)的阶段。举例来说，图15可表示回焊(例如质量回焊)焊料1220的工艺，例如基于加热焊料1220。
可基于回焊焊料1220来形成环绕互连件的连续壁结构。举例来说，可接合裸片围封体1210及衬底围封体1310以形成图2的围封体210、图4的第一围封体412或图4的第二围封体414。类似地，可接合裸片互连件1204及衬底互连件1304以形成图2的互连件204或图4的互连件404。
图16是说明根据本技术的实施例的制造半导体装置的实例方法1600(“方法1600”)的流程图。举例来说，可实施方法1600来制造图2的半导体装置200及/或图4的半导体装置400。还举例来说，方法1600可包含图6到13中所说明的阶段。
方法1600可包含：提供半导体裸片(例如图6的裸片602或图10的裸片1002)，如框1602中所说明。提供半导体裸片可对应于图6及/或图10中所说明的阶段。所提供的裸片可包含从图2的裸片底面222向下突出的裸片互连件(例如图6的裸片互连件604或图10的裸片互连件1004)及裸片围封体(例如图6的裸片围封体610或图10的裸片围封体1010)。裸片围封体可沿外围包围裸片底面222上或沿裸片底面222的裸片互连件。所提供的裸片可进一步具有与裸片围封体的底部或远端部分或表面共面的裸片互连件的底部或远端部分或表面。举例来说，裸片互连件及裸片围封体的底部或远端部分可沿平行于裸片底面222的水平面共面且从裸片底面222垂直偏移图6的突出测量612。
在一些实施例中，裸片围封体可包含铜、铝、镍、其它金属或其组合。在一些实施例中，裸片围封体可包含直接接触裸片底面222或直接附接到金属壁结构的远端表面或部分的焊料。在一些实施例中，裸片围封体可电连接(例如图5的第一电连接512或图5的第二电连接514)到信号或电压电平(例如，例如电压源或接地)。
可使用单独制造工艺来制造或形成裸片，如框1620中所说明。举例来说，裸片制造工艺可包含晶片级处理，例如用于形成集成电路的掺杂工艺及用于分离个别裸片的单粒化工艺。
方法1600可进一步包含：提供衬底(例如图7的衬底706或图13的衬底1306)，如框1604所说明。提供衬底可对应于图7及/或图13中所说明的阶段。所提供的衬底可包含从图2的衬底顶面224向上突出的衬底互连件(例如图7的衬底互连件704或图13的衬底互连件1304)及衬底围封体(例如图7的衬底围封体710或图13的衬底围封体1310)。衬底围封体可沿外围包围衬底顶面224上或沿衬底顶面224的衬底互连件。所提供的衬底可进一步具有与衬底围封体的顶部或远端部分或表面共面的衬底互连件的顶部或远端部分或表面。举例来说，衬底互连件及衬底围封体的顶部或远端部分可沿平行于衬底顶面224的水平面共面且从衬底顶面224垂直偏移图7的突出测量712。
在一些实施例中，衬底围封体可包含铜、铝、镍、其它金属或其组合。在一些实施例中，衬底围封体可包含直接接触衬底顶面224或直接附接到金属壁结构的远端表面或部分的焊料。在一些实施例中，衬底围封体可电连接(例如第一电连接512或第二电连接514)到信号或电压电平(例如，例如电压源或接地)。
可使用单独制造工艺来制造或形成衬底，如框1640中所说明。举例来说，衬底制造工艺(例如，用于制造另一裸片)可包含类似于由框1620说明的工艺的晶片级处理。还举例来说，衬底制造工艺(例如，用于制造PCB衬底)可包含焊料掩模塑形、迹线形成、平坦化等等。
方法1600可进一步包含：使结构(例如裸片及衬底)对准，如框1606中所说明。使结构对准可对应于图8及/或图12中所说明的阶段。举例来说，对准工艺可通过每一裸片互连件的部分沿垂直线与各衬底互连件的对应部分重合及/或裸片围封体的部分沿垂直线与衬底围封体重合来使裸片对准于衬底上方。还举例来说，对准工艺可通过裸片围封体直接接触衬底围封体来使裸片对准于衬底上方。
方法1600可进一步包含：接合结构(例如，将裸片互连件接合到衬底互连件及/或将裸片围封体接合到衬底围封体)，如框1608中所说明。接合工艺可对应于图9及/或图13中所说明的阶段。接合工艺可包含控制一或多个结构的温度(例如加热而接合及冷却而固化结合结构)、对结构施加压力或其组合。举例来说，接合工艺可包含框1612中所说明的扩散接合(例如热压接合或TCB)及/或框1614中所说明的回焊焊料(例如施加焊料时的质量回焊)。
通过接合工艺，围封体210(例如，包含多个围封体，例如第一围封体412及第二围封体414)、围封空间226可形成互连件204。由于金属(例如铜、焊料等等)完全阻挡湿气及其它残屑，所以制造工艺不再需要底部填胶(例如图1的底部填胶110)。因而，接合工艺可在围封空间226或衬底顶面224与裸片底面222之间的空间中无任何底部填胶的情况下接合结构。此外，上述接合工艺可消除氧化物到氧化物接合(例如用于混合接合)及/或对晶片表面条件的要求(例如表面粗糙度控制)，这可导致制造成本及错误降低。
图17是说明根据本技术的实施例的并入半导体装置的系统的框图。具有上文参考图1到16所描述的特征的半导体装置中的任何者可并入到各种更大及/或更复杂系统中的任何者中，图17中所示意性展示的系统1790是所述系统的代表性实例。系统1790可包含处理器1792、存储器1794(例如SRAM、DRAM、快闪存储器及/或其它存储器装置)、输入/输出装置1796及/或其它子系统或元件1798。上文参考图1到14所描述的半导体组合件、装置及装置封装可包含于图17所展示的元件中的任何者中。所得系统1790可经配置以执行各种合适运算、处理、存储、感测、成像及/或其它功能中的任何者。因此，系统1790的代表性实例包含(但不限于)计算机及/或其它数据处理器，例如桌上型计算机、膝上型计算机、因特网设备、手持装置(例如手持式计算机、随身计算机、蜂窝式或移动电话、个人数字助理、音乐播放器等等)、平板计算机、多处理器系统、基于处理器或可编程的消费型电子产品，网络计算机及微型计算机。系统1790的额外代表性实例包含灯、相机、车辆等等。就这些及其它实例来说，系统1790可容置于单个单元中或(例如)通过通信网络分布于多个互连单元上。因此，系统1790的元件可包含本地及/或远程存储器存储装置及各种合适计算机可读媒体中的任何者。
应从上文了解，本文中已为了说明而描述本技术的特定实施例，但可在不背离本发明的情况下作出各种修改。另外，可在其它实施例中组合或消除特定实施例的上下文中所描述的本发明的特定方面。此外，尽管已在特定实施例的上下文中描述与实施例相关联的优点，但其它实施例还可展现此类优点。未必需要全部实施例展现落于本发明的范围内的此类优点。因此，本发明及相关技术可涵盖本文中未明确展示或描述的其它实施例。

Claims (25)

1.一种半导体装置，其包括：
衬底，其包含衬底顶面；
互连件，其经连接到所述衬底且在所述衬底顶面上方延伸；
裸片，其经附接于所述衬底上方，其中所述裸片包含连接到用于电耦合所述裸片及所述衬底的所述互连件的裸片底面；及
金属围封体，其直接接触所述衬底顶面及所述裸片底面，且垂直延伸于所述衬底顶面与所述裸片底面之间，其中所述金属围封体沿外围包围所述互连件。
2.根据权利要求1所述的半导体装置，其中所述金属围封体使围封空间与外部空间隔离，其中所述围封空间包含所述互连件。
3.根据权利要求2所述的半导体装置，其中所述围封空间不包含底部填胶。
4.根据权利要求1所述的半导体装置，其中所述金属围封体包含由扩散接合工艺所致的固体铜。
5.根据权利要求1所述的半导体装置，其中所述金属围封体包含焊料。
6.根据权利要求1所述的半导体装置，其中：
所述金属围封体是第一围封体；且
所述半导体装置进一步包括：
第二围封体，其直接接触所述衬底顶面及所述裸片底面，且垂直延伸于所述衬底顶面与所述裸片底面之间，其中所述第一围封体介于所述互连件与所述第二围封体之间。
7.根据权利要求6所述的半导体装置，其中所述第二围封体沿外围包围所述互连件、所述第一围封体或其组合。
8.根据权利要求7所述的半导体装置，其中所述第一围封体及所述第二围封体具有非嵌套布置或重叠布置。
9.根据权利要求7所述的半导体装置，其中所述第一围封体及所述第二围封体是同心的。
10.根据权利要求6所述的半导体装置，其中：
所述第一围封体具有沿水平面的第一形状；且
所述第二围封体具有不同于所述第一形状的沿所述水平面的第二形状。
11.根据权利要求6所述的半导体装置，其中：
所述第一围封体经电耦合到第一电连接；且
所述第二围封体经电耦合到不同于所述第一电连接的第二电连接。
12.根据权利要求11所述的半导体装置，其中所述第一电连接、所述第二电连接或其组合包含接地或电源连接。
13.根据权利要求12所述的半导体装置，其中：
所述第一电连接是所述电源连接；且
所述第二电连接是所述接地连接，其中所述接地连接沿外围包围所述电源连接。
14.根据权利要求1所述的半导体装置，其中：
所述裸片包含裸片外围边缘；且
所述金属围封体包含沿垂直线与所述裸片外围边缘重合的外围表面。
15.根据权利要求1所述的半导体装置，其中：
所述半导体装置是三维互连3DI装置；且
所述衬底是第二裸片。
16.根据权利要求1所述的半导体装置，其中沿垂直方向的所述裸片底面与所述衬底顶面之间的间距小于20μm。
17.根据权利要求1所述的半导体装置，其中所述半导体装置是包含两个或两个以上裸片的裸片堆叠装置。
18.一种制造半导体装置的方法，其包括：
提供包含数个裸片互连件及裸片围封体的裸片，其中：
所述裸片互连件从裸片底面突出，且
所述裸片围封体从所述裸片底面突出且沿外围包围所述裸片互连件；
提供包含数个衬底互连件及衬底围封体的衬底，其中：
所述衬底互连件从衬底顶面突出，且
所述衬底围封体从所述衬底顶面突出且沿外围包围所述衬底互连件；及
将所述衬底互连件接合到所述裸片互连件，且将所述衬底围封体接合到所述裸片围封体。
19.根据权利要求18所述的方法，其中：
提供所述裸片包含：提供具有与所述裸片围封体的底部部分共面的所述裸片互连件的底部部分的所述裸片；且
提供所述衬底包含：提供具有与所述衬底围封体的顶部部分共面的所述衬底互连件的顶部部分的所述衬底。
20.根据权利要求18所述的方法，其中：
提供所述裸片包含：提供具有与平行于所述裸片底面的水平面共面的所述裸片的所述底部部分及所述裸片围封体的所述底部部分的所述裸片；且
提供所述衬底包含：提供具有与平行于所述衬底顶面的水平面共面的所述衬底互连件的所述顶部部分及所述衬底围封体的所述顶部部分的所述衬底。
21.根据权利要求18所述的方法，其中：
提供所述裸片包含：提供具有包含铜的所述裸片围封体的所述裸片；
提供所述衬底包含：提供具有包含铜的所述衬底围封体的所述衬底；且
接合包含：扩散接合所述裸片围封体及所述衬底围封体。
22.根据权利要求18所述的方法，其中：
提供所述裸片包含：提供具有包含焊料的所述裸片围封体的所述裸片；且接合包含：回焊所述焊料。
23.根据权利要求18所述的方法，其中接合包含：在由所述衬底围封体及所述裸片围封体包围的空间之间无底部填胶的情况下，将所述衬底围封体接合到所述裸片围封体。
24.根据权利要求18所述的方法，其中提供所述裸片包含：提供具有经电耦合到接地或电压源的所述裸片围封体的所述裸片。
25.一种半导体装置，其包含具有至少两个裸片的裸片堆叠，所述半导体装置包括：
多个互连件，其电耦合所述裸片堆叠的两个相邻裸片；及
金属密封构件，其经安置于所述两个相邻裸片之间，其中所述金属密封构件围封所述多个互连件。
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