CN101075594A - 半导体芯片、制造半导体芯片的方法及半导体芯片封装件 - Google Patents

半导体芯片、制造半导体芯片的方法及半导体芯片封装件 Download PDF

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CN101075594A
CN101075594A CNA2007100801372A CN200710080137A CN101075594A CN 101075594 A CN101075594 A CN 101075594A CN A2007100801372 A CNA2007100801372 A CN A2007100801372A CN 200710080137 A CN200710080137 A CN 200710080137A CN 101075594 A CN101075594 A CN 101075594A
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semiconductor chip
top surface
wafer
via hole
electrode pad
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CN100527399C (zh
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李泰秀
朴胤辉
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

在半导体芯片中，本体具有其上形成有图案的顶表面、与顶表面相对的下表面以及多个侧表面。多个电极焊盘形成于本体的顶表面上，以连接至外部端子。屏蔽导电膜形成于本体的除形成有图案的顶表面之外的表面上。导电过孔延伸穿过本体，以连接一个电极焊盘和导电膜。

Description

半导体芯片、制造半导体芯片的方法及半导体芯片封装件
相关申请交叉参考
本申请要求于2006年5月16日向韩国知识产权局提出的韩国专利申请No.2006-43946的优先权，其公开内容整体结合于此作为参考。
技术领域
本发明涉及一种半导体芯片封装件，更具体地说，其中屏蔽导电膜通过过孔连接至地线，本发明还涉及一种半导体芯片封装件的制造方法。
背景技术用于诸如手机等移动通信设备中的高频模块由高频电路构成，所述高频电路包括高频半导体器件和形成于高频电路的基板上的外围电路。
通常，在电子器件中传播的电流在其周围感应出电场和磁场，从而因电势差而产生一空间(space)。在该空间处，电场随时间而变化并在其周围形成电磁场。即，不管器件的感应如何，电流流动而产生电磁噪音，所述电磁噪音是一种多余能量。
这种电磁噪音如果通过路径传输给其它器件，会导致器件性能下降和故障。
为了屏蔽电磁噪音并保护半导体器件，已经采用了形成屏蔽膜的屏蔽技术。
图1a和1b示出了根据现有技术的屏蔽结构。
图1a是示出了具有高频半导体器件12的高频模块的横截面视图，所述高频半导体器件位于基板11上，由金属帽13屏蔽。
在图1a所示的高频模块的传统屏蔽结构中，如果减小金属帽13的厚度，金属帽就不能维持其强度而容易翘曲，从而可能接触高频器件。为了防止由金属帽13与高频器件之间的接触造成的短路，应该在金属帽13下方保留一定间隔，以容纳可能翘曲的金属帽13。例如，金属帽应该形成为100μm的厚度，而其内部间隔应该设计为80μm的厚度。这个物理体积不利于高频模块的小型化。
图1b是示出了另一高频模块的横截面视图，其中在树脂模塑之后通过金属膜15而形成屏蔽膜。
在图1b中，高频半导体器件12安装在基板11上，并进行树脂模塑而气密。然后通过使用金属膜15在模制件14的表面上形成屏蔽膜。
与采用金属帽的情况相比，这种方法使得物理体积更小。然而，由于形成在模制件上的金属膜未连接至基板的地线，因此在屏蔽效应方面没有意义。
发明内容
本发明旨在解决现有技术中的上述问题，因此本发明的一方面在于提供一种半导体芯片，所述半导体芯片具有形成于其上的屏蔽层，当半导体芯片安装在基板上时，所述屏蔽层连接至地线，从而提高了屏蔽效果，并确保芯片以最小体积安装，还提供一种具有半导体芯片的半导体封装件。
本发明的另一方面在于提供制造所述半导体芯片的方法，所述半导体芯片具有形成于晶片上的屏蔽层。
根据本发明的一个方面，本发明提供了一种半导体芯片，包括：本体，具有其上形成有电路图案的顶表面、与顶表面相对的下表面、以及多个侧表面；多个电极焊盘，形成在本体的顶表面上，以连接至外部端子；屏蔽导电膜，形成在本体的除形成有电路图案的顶表面之外的表面上；以及过孔，延伸穿过本体，以将一个电极焊盘与导电膜连接。
连接至导电过孔的电极焊盘可以连接至外部地线并接地。
导电膜仅形成在本体的下表面上。
根据本发明的另一方面，本发明提供了一种半导体芯片封装件，包括：如上所述的半导体芯片；基板，其上形成有接地引线图案和多个引线图案；以及多个凸块，所述凸块设置在半导体芯片的对应电极焊盘与基板的对应引线图案之间，以电连接半导体芯片和基板。
连接至过孔的电极焊盘连接在基板的接地引线图案上。
导电膜仅形成在半导体芯片的下表面上。
根据本发明的再一方面，本发明提供了一种制造半导体芯片的方法，该方法包括：
在包括单位芯片区域(unit chip area)的晶片中形成过孔，以进行从电极焊盘至晶片下表面的连接，所述电极焊盘位于形成有电路图案的晶片的顶表面上，所述晶片下表面与顶表面相对，从而在每个单位芯片区域中形成至少一个过孔；
用导电材料填充过孔；
在晶片下表面上形成导电膜，以接触填充在过孔中的导电材料；
将晶片切割成单位芯片。
该制造方法还可以包括在切割的半导体芯片侧表面上形成屏蔽导电材料。
附图说明
通过下面结合附图的详细描述，本发明的上述及其它目的、特点和其它优点将更容易理解，附图中：
图1a和图1b是示出了根据现有技术的屏蔽结构的横截面视图；
图2是示出了根据本发明实施例的半导体芯片封装件的横截面视图；
图3a是示出了根据本发明另一实施例的半导体芯片的透视图，而图3b是示出了半导体芯片封装件的横截面视图；以及
图4a至图4d是示出了制造图3a半导体芯片的方法的透视图。
具体实施方式
现在将参照附图对本发明的示例性实施例进行详细描述。
图2是示出了根据本发明实施例的半导体芯片封装件的横截面视图，所述半导体芯片封装件具有安装在基板上的半导体芯片。
参照图2，半导体芯片20倒装接合(flip-bond)在基板21上。
半导体芯片20具有本体22，所述本体在其顶表面22a上设置有多个电极焊盘28。
导电膜25形成在半导体芯片本体22的未形成电极焊盘的下表面22b和侧表面上。而且，过孔27穿过本体22的顶表面22a和一个侧表面。
封装基板21可以通过与制造印刷电路板(PCB)相同的过程制造，或者通过高温化学清洗(HTCC)或低温共烧陶瓷(LTCC)方法制造。
电路图案设置在封装基板21上，以输入和输出信号，并且形成过孔，以分别与电路图案上的电极焊盘相连接，从而形成接地引线图案。接地引线图案构造成将上层和下层上的电极焊盘电连接在一起。
如图2所示，由金属制成的多个凸块23形成在设置于封装基板21上的电路图案的引线图案上，而半导体芯片通过凸块23安装在电极焊盘28上。倒装接合的半导体芯片使得电极焊盘28能够通过凸块23电连接至封装基板21上的引线图案。
在半导体芯片中，本体22的顶表面22a上的电极焊盘28通过凸块23连接至基板21，一些凸块是连接至基板地线的接地凸块23a。形成在基板21的引线图案29与半导体芯片的电极焊盘28之间的凸块23由金、铜、铝、或其合金制成，并用于连接基板的引线和半导体芯片。
接地凸块23a与过孔27中填充有导电材料的导电过孔直接接触，并用于电连接导电膜25和地线。当然，尽管导电过孔27a直接连接至凸块23，但是，如果将导电过孔27a电连接至基板上的接地凸块23a，就可以实现本发明的该特征。
通过这种方式，形成在半导体芯片本体22的下表面22b和侧表面上的导电膜25电连接至地线。因此，使得从半导体芯片产生的电磁波流向地线，从而被阻断。这相应地抑制了噪音的发生。此外，这屏蔽了从外界感应给半导体芯片的电磁波，从而抑制了来自电磁波的干扰。
为了在半导体芯片的下表面22b和侧表面上容易形成导电膜25，将导电漆直接涂覆或喷涂在半导体芯片的顶表面和侧表面上。
图3a是示出了根据本发明实施例的半导体芯片的透视图。
参照图3a，半导体芯片具有本体，该本体在其形成有图案的顶表面32a上设置有电极焊盘38，以及在其下表面32b上设置有金属膜35。金属膜35具有过孔37，所述过孔穿过半导体芯片的本体32。金属膜35与过孔37中填充有导电材料的导电过孔37a接触。过孔37连接至半导体芯片本体32的顶表面32a上的电极焊盘38。
过孔37可以通过激光处理或诸如活性离子蚀刻的干法蚀刻形成。过孔37可以具有各种形状，诸如圆形、三角形和多边形。过孔37可以具有一致的横截面。可替换地，过孔37可以具有与其顶表面32a近似成比例的更大或更小的横截面。
过孔37填充有导电材料，以形成导电过孔37a，并且该过孔延伸至半导体芯片32的顶表面32a上的电极焊盘，以电连接导电膜35和基板上的地线。
导电过孔37a可以通过电镀形成，并且导电材料采用所有可电镀的金属，诸如金(Au)、银(Ag)、铜(Cu)、铝(Al)、镍(Ni)、和钨(W)。
可替换地，导电过孔37a可以通过真空蒸发、溅射、化学气相沉积以及通过装填和烧结导电胶而形成。用于填充过孔37的导电材料例如为金(Au)、银(Ag)、铜(Cu)、铝(Al)、镍(Ni)、钨(W)、及其合金。
为了在半导体芯片本体32的下表面32b上容易形成导电膜35，将导电漆直接涂覆或喷涂在半导体芯片本体的下表面上。
图3b示出了具有安装在基板上的半导体芯片的半导体芯片封装件的横截面图。
参照图3b，半导体芯片倒装接合在基板31上。
半导体芯片具有本体32，所述本体在其顶表面32a上设置有多个电极焊盘38。
导电膜35形成在半导体芯片本体32的未形成电极焊盘的下表面32b上。而且，过孔37穿过半导体芯片本体32的顶表面32a和下表面32b。
此外，半导体芯片本体32的顶表面32a上的电极焊盘38通过凸块33连接至基板31上的引线图案39，其中一些凸块是连接至基板上的地线的接地凸块33a。形成在基板31的引线图案39与半导体芯片的电极焊盘38之间的凸块由金、铜、铝、或其合金制成，并用于将基板的导线与芯片连接。
接地凸块33a直接与过孔37中填充有导电材料的导电过孔37a接触，并用于将导电膜35电连接至基板上的地线。当然，尽管导电过孔37a直接连接在另一个凸块33上，但如果将导电过孔37a电连接至基板上的接地凸块33a，就可以实现本发明的该特征。
尽管没有示出，可以形成阻挡金属膜，以方便在接地凸块33a与导电过孔37a之间进行接合，并防止因使用芯片而伴随产生的热量引起裂纹，从而确保芯片的可靠性。阻挡金属膜可以由选自以下组中的一种材料制成：钛(Ti)、氮化钛(TiN)、氮化钽(TaN)、Ti/TiN和Ta/TaN。阻挡金属膜优选地通过化学气相沉积法形成。
过孔37填充有导电材料，以形成导电过孔37a，并且该过孔延伸至接地凸块33a，所述接地凸块形成于设置在半导体芯片本体32的顶表面32a上的电极焊盘上，以将导电膜35与基板上的地线电连接。
通过这种方式，形成在半导体芯片本体32的下表面32b上的导电膜35电连接至地线。因此，使得从半导体芯片产生的电磁波流向地线，从而被阻断。这相应地抑制了噪音的发生。此外，这屏蔽了从外界感应给半导体芯片的电磁波，从而抑制了来自电磁波的干扰。
当在各个半导体芯片上设置相互隔离的导电膜材料时，导电膜35可以仅形成在半导体芯片本体32的下表面32b上。
此处，至少一个过孔穿过半导体芯片本体32的顶表面和下表面，并填充有导电材料。然后导电膜形成在半导体芯片本体的下表面上，以与导电材料接触。导电膜35可以通过直接涂覆或喷涂用于屏蔽电磁波的导电漆而容易地形成。
可替换地，在导电膜形成于半导体芯片下表面上的结构中，过孔和导电膜形成于被切割成单位芯片之前的晶片上，然后将晶片切割成单位芯片。因此，这简化了制造方法。
图4a至图4d示出了在晶片上制造图3a的半导体芯片的制造方法。
为了在晶片上制作其中具有导电膜的半导体芯片，准备好晶片，在晶片上的每个单位晶片区域中形成至少一个过孔，在过孔中填充导电材料，在晶片的下表面上形成导电膜，并将晶片切割成单位芯片。
参照图4a，在每个单位芯片区域上形成过孔，以进行从晶片顶表面上的电极焊盘至晶片下表面的连接，晶片顶表面上形成有电路图案和电极焊盘。图4a是晶片的下表面朝上的透视图。过孔47通过机械抛光或激光处理形成。为实现本发明的一个方面，必须在每个单位芯片区域上形成至少一个过孔。此处，过孔连接至设置在电路图案周围(未示出)的一个电极焊盘，所述电路图案形成于晶片的顶表面上。即，电极焊盘连接至基板的地线。
参照图4b，用导电材料填充形成于每个单位芯片区域上的过孔47，以形成导电过孔47a。这使得半导体芯片本体42的下表面上的导电膜45能够电连接至基板的地线。
参照图4c，在晶片的下表面上形成导电膜。导电膜45可以通过直接涂覆或喷涂用于屏蔽电磁波的导电漆而形成。与在每个单位芯片上形成半导体膜的情况相比，这简化了工序并且节省了材料成本。
此处，导电膜45与过孔47中填充有导电材料的导电过孔47a直接接触。优选地，导电膜45由与填充在过孔47中的材料相同的导电材料制成。
参照图4d，将晶片切割成每个单位芯片，以生产根据本发明的半导体芯片。在半导体芯片本体42的下表面上形成导电膜45，并使导电膜与填充在过孔47中的导电材料相接触。因此，导电过孔47a连接导电膜45和基板的地线。
此外，可选地，可以在切割的半导体芯片的侧表面上形成屏蔽导电材料，以增强导电膜的屏蔽效果。
尽管未示出，切割的半导体芯片倒装接合在基板上，以将导电过孔连接至基板的地线，从而生产根据本发明的半导体芯片封装件。
实施例和附图仅是示例性的，并不限制本发明。因此，可以以不同方式设置导电膜和过孔。
如上所述，根据本发明的示例性实施例，当半导体芯片安装在基板上时，屏蔽金属膜连接至地线，以增强电磁波的屏蔽效果，并确保芯片以最小体积安装。
另外，可以在晶片上制造半导体芯片，以简化制造过程。
尽管已经结合优选实施例示出并描述了本发明，但是对本领域技术人员很显然，在不脱离由所附权利要求限定的本发明精神和范围的条件下，可以进行修改和变换。

Claims (8)

1.一种半导体芯片，包括：
本体，具有其上形成有电路图案的顶表面、与所述顶表面相对的下表面以及多个侧表面；
多个电极焊盘，形成在所述本体的顶表面上，以连接至外部端子；
屏蔽导电膜，形成在所述本体的除形成有所述图案的顶表面之外的表面上；以及
导电过孔，延伸穿过所述本体，以将一个所述电极焊盘与所述导电膜连接。
2.根据权利要求1所述的半导体芯片，其中，连接至所述导电过孔的所述电极焊盘接地。
3.根据权利要求1所述的半导体芯片，其中，所述导电膜仅形成于所述本体的下表面上。
4.一种半导体芯片封装件，包括：
半导体芯片，所述芯片包括：
本体，具有其上形成有电路图案的顶表面、与所述顶表面相对的下表面以及多个侧表面；
多个电极焊盘，形成在所述本体的顶表面上，以连接至外部端子；
屏蔽导电膜，形成于所述本体的除形成有所述图案的顶表面之外的表面上；以及
导电过孔，延伸穿过所述本体，以将一个所述电极焊盘与所述导电膜连接，
基板，所述基板上形成有接地引线图案和多个引线图案；以及
多个凸块，设置在所述半导体芯片的各个所述电极焊盘与所述基板的各个引线图案之间，以将所述半导体芯片与所述基板电连接。
5.根据权利要求4所述的半导体芯片封装件，其中，连接至所述过孔的所述电极焊盘连接在所述基板的所述接地引线图案上。
6.根据权利要求4所述的半导体芯片封装件，其中，所述导电膜仅形成于所述半导体芯片的下表面上。
7.一种制造半导体芯片的方法，该方法包括：
在包括单位芯片区域的晶片中形成过孔，以进行从所述晶片的顶表面上的电极焊盘至所述晶片下表面的连接，所述晶片的顶表面上形成有电路图案，所述晶片下表面与所述顶表面相对，从而在每个单位芯片区域中形成至少一个过孔；用导电材料填充所述过孔；
在所述晶片的下表面上形成导电膜，以与填充在所述过孔中的导电材料接触；以及
将所述晶片切割成单位芯片。
8.根据权利要求7所述的制造方法，还包括：
在切割的半导体芯片的侧表面上形成屏蔽导电材料。
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