CN108352329A - 用于减轻封装集成电路中的寄生耦合的方法和装置 - Google Patents

用于减轻封装集成电路中的寄生耦合的方法和装置 Download PDF

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Publication number
CN108352329A
CN108352329A CN201680047952.6A CN201680047952A CN108352329A CN 108352329 A CN108352329 A CN 108352329A CN 201680047952 A CN201680047952 A CN 201680047952A CN 108352329 A CN108352329 A CN 108352329A
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China
Prior art keywords
pad
chip
ground
lead
encapsulation
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CN201680047952.6A
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Inventor
V·贾恩
N·金伊曼
A·伊斯玛利
G·梅农
N·贾恩
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Anoi Kiwi Co
Anokiwave Inc
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Anoi Kiwi Co
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Publication of CN108352329A publication Critical patent/CN108352329A/zh
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Abstract

一种封装IC，其具有封装件，该封装件具有芯片焊盘、信号引线、以及接地引线。所述封装IC还具有固定至所述封装件的芯片，该芯片具有接地焊垫和信号焊垫。所述信号焊垫电连接至所述信号引线，并且所述接地焊垫电连接至所述芯片焊盘和所述接地引线。

Description

用于减轻封装集成电路中的寄生耦合的方法和装置
优先权
本专利申请要求保护2015年9月4日提交的、名为“METHOD AND APPARATUS FORMITIGATING PARASITIC COUPLING IN A PACKATED INTEGRATED CIRCUIT”并将VipulJain、Noyan Kinayman、Amir Esmaili、Guarav Menon以及Nitin Jain作为发明人的临时美国专利申请号14/846092的优先权，其公开通过引用其全部内容而并入于此。
技术领域
本发明总体上涉及集成电路/芯片，并且更具体地，本发明涉及封装集成电路/芯片并且减轻在封装集成电路/芯片时的噪声问题。
背景技术
集成电路芯片通常安装在集成电路封装件内。在其它功能中，集成电路封装件既可以保护芯片免受环境影响，又可以方便地安装至底层系统，诸如印刷电路板或其它集成电路。
本领域技术人员已经开发了许多不同类型的封装件以用于各种各样的应用。更常用类型的封装件之一被已知为“引线框”封装件。具体而言，引线框封装件通常具有用于将芯片/集成电路电连接至外部环境的金属引线框(例如，由铜形成)、以及诸如注模材料或塑料的包封件(encapsulant)，包封件包封大部分的引线框和芯片。通常是，包封件和引线框形成矩形主体，以容易固定至底层系统。
引线框通常具有两个主要部分；即，用于支承集成电路芯片的芯片焊盘(paddle)、以及用于将芯片与底层系统电连接的多条引线。为此，芯片附接材料通常将芯片物理地固定至芯片焊盘，而焊线(wirebond)或其它互连将芯片电连接至引线。实际上，封装集成电路的内部通常具有将芯片连接至引线的几十条或数百条焊线。
不期望地是，在使用期间，鉴于它们在小体积封装件内的紧密接近度，焊线可能电耦合以劣化由芯片产生的信号。当在高频下操作芯片时，这个问题会变得特别严重。实际上，这种耦合可以限制高频芯片可以工作的频率范围。
发明内容
根据本发明的一个实施方式，封装集成电路(“封装IC”)具有封装件，该封装件具有芯片焊盘、信号引线、以及接地引线。所述封装IC还具有固定至所述封装件的芯片，该芯片具有接地焊垫(pad)和信号焊垫。所述信号焊垫电连接至所述信号引线，并且所述接地焊垫电连接至所述芯片焊盘和所述接地引线两者。
尤其是，所述芯片可以包括从所述接地焊垫延伸并且与所述芯片焊盘电连接的通孔。为了节约总体不动产(real-estate)，所述芯片可以具有形成芯片覆盖区(footprint)的多个边缘，并且所述芯片焊盘可以处于所述芯片覆盖区内(总体上或者部分地)。而且，就像其它芯片，所述芯片具有正面和相反背面。所述正面具有所述接地焊垫和所述信号焊垫，而所述背面具有贯穿所述通孔与所述接地焊垫接触的背面芯片金属。为了进行期望电连接，所述背面芯片金属与所述芯片焊盘电连接(例如，利用导电粘合剂)。除了具有利用所述通孔的连接以外，所述封装IC还可以具有将同一接地焊垫连接至所述接地引线的焊线。
其它实施方式不必须使用通孔。而是，这种实施方式可以使用连接在所述接地焊垫与所述接地引线之间的第一焊线。这样，所述第一焊线可以被认为物理地连接所述接地焊垫与所述接地引线。所述封装IC还具有第二焊线，该第二焊线连接在同一接地焊垫与所述芯片焊盘之间，由此电连接所述接地焊垫与所述芯片焊盘。
所述封装件优选地为引线框封装件，并且其芯片焊盘和接地焊垫被配置成，在通电时(例如，当安装至印刷电路板并在更大电路中使用时)处于地电位。在其它应用中，所述芯片可以实现按大约1兆赫兹到100吉赫兹之间的频率操作的相控阵。其它实施方式可以扩展至更低频率(例如，100赫兹)或更高频率(例如，直至大约110吉赫兹)。
所述芯片优选地具有第二接地焊垫，并且所述封装件优选地具有对应第二接地引线。所述第二接地焊垫可以电连接至所述芯片焊盘和所述第二接地引线两者。在该情况下，所述信号引线优选地定位在所述接地引线与所述第二接地引线之间。
根据另一实施方式，封装IC具有相控阵芯片(例如，具有相控阵系统的至少一部分的芯片)，该相控阵芯片具有多个芯片RF组。每个芯片RF组都包括第一接地焊垫、信号焊垫、以及第二接地焊垫。另外，所述芯片还具有封装件，该封装件具有芯片焊盘和多个封装件RF组。按与芯片RF组相似的方式，每个封装件RF组都包括第一接地引线、信号引线、以及第二接地引线。多个连接件连接给定芯片RF组与给定封装件RF组。所述给定芯片RF组具有给定第一接地焊垫和给定第二接地焊垫以及给定信号焊垫。按类似方式，所述给定封装件RF组具有给定第一接地引线和给定第二接地引线以及给定信号引线。
为了进行恰当连接，所述多个连接件包括第一连接件、第二连接件、以及第三连接件。所述第一连接件将所述给定第一接地焊垫连接至所述给定第一接地引线，所述第二连接件将所述给定第二接地焊垫连接至所述给定第二接地引线，以及所述第三连接件将所述给定信号焊垫连接至所述给定信号引线。所述多个连接件还具有将所述给定第一接地焊垫连接至所述芯片焊盘的第一焊盘连接件、将所述给定第二接地焊垫连接至所述芯片焊盘的第二焊盘连接件。
根据本发明其它实施方式，形成封装IC的方法设置具有接地焊垫和信号焊垫的芯片，并且还设置具有芯片焊盘、接地引线、以及信号引线的引线框基部。该方法接着电连接所述芯片的所述信号焊垫与所述引线框基部的所述信号引线，并且电连接所述芯片的所述接地焊垫与所述引线框基部的所述接地引线。另外，所述方法电连接所述芯片的同一接地焊垫与所述引线框基部的所述芯片焊盘，并且包封所述引线框基部的至少一部分和所述芯片。诸如环氧树脂的附加材料还可以与引线框基部结合地包封所述芯片。
附图说明
根据参照下面紧接着概述的附图所讨论的下列“具体实施方式”，本领域技术人员应当更全面想到本发明各种实施方式的优点。
图1示意性地示出了可以实现本发明的示例性实施方式的系统。
图2A示意性地示出了印刷电路板的具有根据本发明的一个实施方式配置的利用焊线与芯片焊盘连接的封装IC的较小部分的立体图。为了清楚起见，该图仅示出了封装IC的一侧；其它实施方式可以在所有侧都有连接。
图2B示意性地示出了图2A的封装IC和印刷电路板的引线和焊垫的RF组的平面图。
图2C示意性地示出了图2A的封装IC和印刷电路板的截面图。
图3A示意性地示出了印刷电路板的具有根据本发明的另一实施方式配置的利用通孔与芯片焊盘连接的封装IC的较小部分的立体图。为了清楚起见，该图仅示出了封装IC的一侧；其它实施方式可以在所有侧都有连接。
图3B示意性地示出了图3A的封装IC和印刷电路板的引线和焊垫的RF组的平面图。
图3C示意性地示出了图3A的封装IC和印刷电路板的截面图。
图4示出了根据本发明的示例性实施方式形成图1、图2A以及图3A的封装IC的处理。
具体实施方式
在示例性实施方式中，封装集成电路(“封装IC”)具有优化的连接布置以减轻其内部电连接之间的寄生干扰。为此，封装IC具有包括接地引线和芯片焊盘的封装件。由该封装件包封的内部芯片具有对应接地焊垫，该对应接地焊垫利用两个分离导电路径连接至该封装件的接地引线和芯片焊盘。
在其它方面，那两个导电路径可以通过一对单独焊线形成，或者通过利用贯穿芯片形成的导电通孔(例如，“硅通孔(through-silicon-via)”)和单独焊线形成。如此，电连接的总长度减小，从而减少了那两个连接之间以及那两个连接与封装IC中的其它导体(例如，将其它芯片焊垫连接至其它封装引线的焊线)之间的寄生耦合。与本发明人已知的多种现有技术装置相比，较少的寄生耦合改进了芯片性能。下面，对示例性实施方式的细节进行讨论。
图1示意性地示出了利用根据本发明的示例性实施方式配置的引线框封装件的系统10。具体而言，系统10包括安装在常规印刷电路板12上的多个电路组件。尤其是，那些组件包括三个封装IC 14。具体来说，封装IC 14包括第一类封装IC，其具有包封一个或更多个芯片20(在图2A和后面的图中示出)的“有引线”引线框封装件18(由标号“14A”标识)。因此，该封装IC 14A具有从其底面延伸的焊接至电路板12的多条引线15。那些引线15中的每个都将内部芯片20与其它电子组件和装置电连接。
另外，系统10还具有两个其它封装IC 14，每个封装IC 14都包括包封一个或更多个芯片20的无引线封装件18(由标号“14B”标识)。更具体地说，无引线封装件14B皆具有终止于安装至电路板12的底面焊垫(未示出)表面的内部引线。因此，因为它们没有从其主体延伸的引线15(引线15在内部)，所以无引线封装件14B有利地不需要由引线封装件18(诸如封装IC 14A的封装件18)要求的额外横向空间。
本领域技术人员可以在电路板12上包括其它电路组件16(在图1中示意性地示出)。例如，那些组件16可以包括附加集成电路(例如，转换器、MEMS、功率芯片等)和/或分立组件(例如，二极管、晶体管、电容器、以及电阻器)。本领域技术人员可以为必要应用选择恰当组件。
在示例性实施方式中，一个或更多个封装IC 14在所谓的“扁平无引线(quad-flatno-leads)”(“QFN”)封装件内实现相控阵。因此，封装件18可以被认为是具有暴露引线框/芯片焊盘(在下面详细讨论)以辅助热管理、接地以及信号传送的准芯片级封装件。实际上，应该重申，QFN封装件仅出于示例性目的而加以讨论，并非旨在限制各种实施方式。本领域技术人员明白，其它类型的引线框封装件18以及在某些情况下的非引线框封装件18可以有效地实现本发明的各种实施方式。
示例性实施方式应用于实现多种功能中的任一个功能的芯片20。举例来说，如上所述，各种实施方式应用于实现相控阵的封装IC 14。在该情况下，芯片20可以产生多个相移信号。具体而言，如本领域技术人员所知，相控阵装置可以与天线一起操作以产生彼此相对相移的电可操纵信号。这样，信号相长地和/或相消地彼此干涉以使射束沿期望方向转向，以预先指定的方式放大，和/或改善射束清晰度。
相控阵封装IC 14优选地跨各种各样的频率操作。例如，那些频率可以在从25赫兹到几十吉赫兹(例如，100吉赫兹)的范围内变动。然而，本发明人已知的用于相控阵芯片的现有技术封装方案基本上是有限的。例如，这种现有技术封装件使用许多相对较长的焊线来将芯片20与封装件18电连接。然而，在使用期间，那些长的焊线会产生寄生电感，这不利地限制芯片20可以使用的可用频率。例如，这种寄生电感通常将频率限制在20吉赫兹或更低。另外，发明人已知的用于相控阵芯片的现有封装技术常常不能在封装件中的不同RF信号线之间提供足够的隔离。然而，如下文所解释的，示例性实施方式优化芯片封装，以有效地扩展相控阵芯片20可用的频率范围-优选超过20吉赫兹。事实上，在模拟期间，发明人惊奇地发现实质上使这种封装IC 14的有效频率范围加倍的改进。
应注意到，关于上述封装示例，各种实施方式都可以应用于其它类型的芯片20。例如，示例性实施方式可以应用于实现RF放大器的芯片20，该RF放大器控制传送至天线及从天线传送的信号的幅度。因此，讨论实现相控阵的芯片20以及在特定频率下工作的这种芯片20仅出于示例性目的。
图2A示意性地示出了图1的系统10的较小部分的立体图。在示例性实施方式中，芯片可以由多种不同技术形成。例如，芯片可以利用CMOS、SOI(绝缘体上硅)CMOS或硅锗BiCMOS技术中的任何技术来制造。
如所示，芯片20具有多个焊垫(示意性地示出并且通常由标号22标识)，使得其能够通过封装件18的引线15与其它装置通信。具体来说，如上所述，封装件18优选地是具有铜引线框24和包封材料(“包封件26”)的引线框封装件18。然而，为了更好地显示组件，该视图示出了包封件26是大致透明的。本领域技术人员应该明白，包封件26通常是不透明的，诸如实心黑色。引线框24(无论其是后成型的还是预成型的引线框封装件18的一部分)可以被认为形成了安装有芯片20的基部。
引线框24具有相对平坦的骨料形状(aggregate shape)，沿其外围具有多条引线15。例如，图2A所示的引线框24沿其三个外围边缘具有多条引线15。在该实施方式中，引线15通常与封装件18的底面齐平，并因此不从封装件18延伸。这种类型的封装件类似于图1的无引线封装件14B。这样，该封装件18可以被表面安装至印刷电路板12。然而，其它实施方式可以具有从封装件18延伸的引线15，并因此可以利用其它技术(诸如传统穿孔安装技术)将其连接至印刷电路板12。实际上，本领域技术人员可以为引线15的特定应用选择恰当位置和数量、它们的用途、以及类型。因此，对引线15的具体定位和数量的讨论是出于示例性目的。
引线框24还具有在本领域中被已知为“芯片焊盘30”的大中心定位部分。在示例性实施方式中，芯片焊盘30优选在使用期间具有地电位。如下更详细讨论的，芯片20具有指定焊垫22，该指定焊垫沿着引线框24的外围与芯片焊盘30和至少一条引线15两者电连接。令本发明人惊讶的是，模拟已经表明，这种双重连接大幅度减轻了寄生RF耦合，有效提高了装置性能，并且扩展了封装IC 14的有效频率范围。
封装件18的引线15优选地形成用于管理去往和来自芯片20和印刷电路板12的信号传送的多个“RF组32”。按类似方式，印刷电路板12和芯片20均可以被认为分别形成焊垫22和导电传输线34的对应RF组32。示例性实施方式减轻或减少不同RF组32之间的RF寄生耦合。
具体而言，图2B示意性地示出了封装件18(即，引线框24)的引线15、封装IC 14的焊垫22、以及印刷电路板12的线路34的RF组32的放大平面图。如所示，图2B的RF组32具有用于将芯片20上的信号焊垫22B与印刷电路板12的对应信号线34B电连接的中心信号引线15B。在所示实施方式中，针对给定RF组32，一对焊线36将信号焊垫22B与引线框24上的单条信号引线15B电连接。信号引线15B对应地直接表面安装至印刷电路板12中的信号线34B。
相信以这种方式使用两条焊线36能够改进性能。然而，一些实施方式可以使用多于两条焊线36来进行这种连接。其它实施方式可以仅使用一条焊线36。本领域技术人员可以基于期望性能选择恰当的焊线数量和构造。
除了具有信号引线15B以外，每个芯片/引线框/电路板RF组32还优选地在其相应信号接口的每一侧上具有一对接地接口。因此，引线RF组32包括在使用期间优选地接地的一对接地引线15A。根据其在图2B中的取向，引线框24的RF组32具有物理上位于信号引线15B的每一侧上的接地引线15A。按类似方式，芯片20和印刷电路板12还在其相应信号焊垫22B和信号线34B的每一侧上分别具有接地焊垫22A和接地线34A以实现它们的相应RF组32。焊线36将芯片20的每个接地焊垫22A与封装18的每条接地引线15A电气和物理地连接。例如，图2B示出了从(所讨论的RF组32的)每个接地焊垫22A延伸至封装件18的一条对应接地引线15A的单条焊线36。按对应方式，封装件18的每条接地引线15A电连接至印刷电路板12的接地线34A中的一个。
如上所述，每个接地焊垫22A也通过较短焊线36直接连接至芯片焊盘30。图2C(其示意性地示出了图2A的封装IC 14和印刷电路板12的截面图)还示出了这种连接。这样，RF组32的每个接地焊垫22A都与芯片焊盘30和对应接地引线15A两者电连接。如所提到，在使用期间，芯片焊盘30和接地引线15A均接地。
由于引线框24和芯片20的物体结构，针对给定接地焊垫22A，连接至接地引线15A的焊线36比连接至芯片焊盘30的焊线36更长。从而，该布置应有利地减轻不同RF组32之间的寄生RF耦合(与在接地焊垫22A和接地引线15A之间具有两条长焊线36相比)，同时为该装置提供必要接地。
图2C还示出了至少部分地形成信号线34B和接地线34A的金属层38和印刷电路板通孔40。例如，在图2A-2C中所示的实施方式中，印刷电路板12的顶表面的信号线34B与至少一个印刷电路板通孔40连接，该至少一个印刷电路板通孔电连接至印刷电路板12内或上的其它金属38。
本发明人模拟了三种类似的装置：1)不与芯片焊盘30连接的现有技术装置，2)仅连接至焊盘30的现有技术装置，以及3)图2A-2C的实施方式。在所有情况下，芯片20在10到25吉赫兹的频率范围内实现相控阵。现有技术装置在大约20吉赫兹时具有实质寄生耦合，这不利地限制了可以使用的应用的数量。与此相反，图2A-2C的实施方式显示了在整个频率范围内可忽略不计的寄生耦合。因此，示例性实施方式应该能够在更宽频率范围内操作。例如，预期这样的实施方式在1兆赫与50吉赫兹或更高的频率(例如，高达100吉赫兹)之间工作。
不利用焊线36，其它实施方式通过导电芯片通孔42(即，通过芯片20本身)将RF组32的接地焊垫22A物理地和电连接至芯片焊盘30。图3A至图3C示意性地示出了一个这样的实施方式。为了展示它们的一些相似和不同之处，图3A至图3C示出了与图2A至图2C中相同的三个视图；即，立体图、单个RF组32的放大平面图、以及截面图。
具体而言，以类似于图2A至图2C的实施方式的方式，该实施方式也具有相同RF组32以及安装在芯片焊盘30上的芯片20。另外，该实施方式还具有连接在每个信号焊垫22B与其对应信号引线15B之间的一对焊线36。然而，关于每个芯片接地焊垫22A与芯片焊盘30和接地引线15A的两个连接之间的连接，构造与早前实施方式不同。
为此，该实施方式在每个接地焊垫22A与其对应接地引线15A之间连接一对焊线36。另选的是，该实施方式可以在每个接地焊垫22A与其对应接地引线15A之间仅连接单条焊线36或者多于两条焊线36。此外，为了进一步减轻潜在寄生RF耦合，该实施方式借助于延伸通过芯片20的一个或更多个芯片通孔42将每个接地焊垫22A与芯片焊盘30连接。例如，芯片20可以具有将RF组32的每个接地焊垫22A电连接至芯片20的底部上的金属化部的多个芯片通孔42。在一些实施方式中，芯片通孔42本身在芯片20的底部上形成金属化部。如下关于图4提到的，在芯片20的底部上的该金属化层直接连接至芯片焊盘30，从而制成必要电连接。
通过利用芯片通孔42，芯片20和印刷电路板12可以比上面关于图2A至图2C描述的实施方式更小。具体而言，图2A至图2C的实施方式要求芯片20不完全覆盖芯片焊盘30-芯片焊盘30必须暴露，使得其可以与焊线36物理连接。然而，在不要求所述焊线连接的情况下，图3A至图3C的实施方式的芯片20的覆盖区可以非常接近芯片焊盘30的尺寸。换句话说，芯片20的覆盖区(从图的角度看，其由其底部外围限定)可以非常接近芯片焊盘30的尺寸，因为没有到芯片焊盘30的焊线接入是必须的。因此，后一个实施方式有利地减轻了寄生RF耦合，同时减小了封装件18和印刷电路板12的尺寸要求。
本发明人还模拟了图3A至图3C的实施方式，并将其与同图2A至图2C的实施方式进行比较而模拟的上述现有技术装置进行比较。芯片20在25吉赫兹至40吉赫兹之间的频率范围内(即，比前述模拟的那些频率更高的频率)实现相控阵。现有技术装置在大约37吉赫兹下显示出实质寄生耦合，其再次限制了可以使用的应用的数量。与此相反，图3A至图3C的实施方式显示了在整个频率范围内可忽略不计的寄生耦合。因此，如图2A至图2C的实施方式那样，示例性实施方式应该能够在更宽频率范围内操作(直至或超过50吉赫兹)。
图4示出了根据本发明的示例性实施方式形成图1、图2A、以及图3A的封装IC 14的处理。应注意到，该处理从通常用于形成封装IC 14的较长处理大大简化。因此，形成封装IC14的处理具有本领域技术人员可能使用的许多步骤，诸如测试步骤、蚀刻步骤、或附加钝化步骤。另外，一些步骤可以按与所示不同的次序执行或者同时执行。因此，本领域技术人员可以适当地修改该处理。此外，如上面和下面所提到的，提到的许多材料和结构是可以使用的各种不同材料和结构中的一种。本领域技术人员可以根据应用和其它约束来选择恰当的材料和结构。因此，对特定材料和结构的讨论并不旨在限制所有实施方式。
图4的处理优选使用成批封装技术，其同时在大片单独形成的引线框24上形成多个封装IC 14。尽管效率低得多，但本领域技术人员可以将这些原理应用于仅形成一个封装IC 14的处理。
图4的处理在步骤400开始，其设置芯片20。如上所述，芯片20可以具有焊垫22，焊垫具有从顶部延伸到底部的芯片通孔42，或者芯片可以具有焊垫22但是不具有芯片通孔42。选择恰当的芯片20取决于所实现的实施方式。
该处理还在步骤402设置引线框基部。在批处理时，引线框基部由经蚀刻或以其它方式处理的铜片形成，以形成具有芯片焊盘30和引线15的单独引线框24的二维阵列。每个单独引线框24接收/连接单个芯片20。
步骤402通过将芯片20固定至引线框基部继续。为此，该处理将粘合剂施加至每个芯片20的底部，并将芯片20放置在引线框基部的相应芯片焊盘30上。图3A至图3C的实施方式(其具有芯片通孔42)优选地利用导电粘合剂来固定芯片20，该导电粘合剂在芯片焊盘30与终止于芯片20的底部的芯片通孔42/金属化部之间提供恰当电接触。然而，其它实施方式(诸如图2A至图2C的那些)可以使用不导电粘合剂或某些其它固定手段。本领域技术人员可以选择用于将芯片20连接至它们的相应芯片焊盘30的恰当手段。
在芯片20被固定至引线框基部之后，该处理继续到步骤404，引线框基部电连接焊垫22和引线15，如图2A至图2C、图3A至图3C所示，或者在其它另选实施方式中。为此，该处理可以将焊线焊接至恰当引线15和焊垫22。
接下来，步骤406将引线框基部、芯片20、以及它们的连接包封在上述包封件26中，诸如不透明塑料。然而，引线框基部是预成型引线框封装件18的实施方式可能不需要这种包封件26。相反的是，这样的实施方式可以将盖子阵列固定至引线框24阵列。
该处理在步骤408结束，其将各种引线框24及其固化包封件26分离成单独封装IC14。因此，常规切割操作切开封装IC 14的二维阵列的包封件26和引线框24，结束该处理。
因此，示例性实施方式有效地形成具有减轻的RF干扰的封装IC 14，从而有效地延长其频率范围。这样，这些装置可以被用于更广泛应用。另外，一些实施方式具有减小的覆盖区，从而允许整个系统10具有更小的覆盖区。
尽管上述讨论公开了本发明的各种示例性实施方式，但应当明白，在不脱离本发明的真实范围的情况下，本领域技术人员可以进行将实现本发明的一些优点的各种修改。

Claims (24)

1.一种封装IC，所述封装IC包括：
封装件，所述封装件具有芯片焊盘、信号引线、以及接地引线；以及
芯片，所述芯片具有接地焊垫和信号焊垫，所述芯片被固定至所述封装件；
所述信号焊垫电连接至所述信号引线，
所述接地焊垫电连接至所述芯片焊盘和所述接地引线。
2.根据权利要求1所述的封装IC，其中，所述芯片包括从所述接地焊垫延伸的通孔，所述通孔与所述芯片焊盘电连接。
3.根据权利要求2所述的封装IC，其中，所述芯片包括：CMOS、绝缘体上硅SOI CMOS、或硅锗BiCMOS基板。
4.根据权利要求2所述的封装IC，其中，所述芯片具有正面和背面，所述正面包括所述接地焊垫和所述信号焊垫，所述背面包括通过所述通孔与所述接地焊垫接触的背面芯片金属，所述背面芯片金属与所述芯片焊盘电连接。
5.根据权利要求2所述的封装IC，所述封装IC还包括焊线，所述焊线将所述接地焊垫连接至所述接地引线。
6.根据权利要求1所述的封装IC，所述封装IC还包括连接在所述接地焊垫与所述接地引线之间的第一焊线，所述第一焊线物理连接所述接地焊垫与所述接地引线，所述封装IC还包括连接在所述接地焊垫与所述芯片焊盘之间的第二焊线，所述第二焊线电连接所述接地焊垫与所述芯片焊盘。
7.根据权利要求1所述的封装IC，其中，所述封装件包括引线框封装件。
8.根据权利要求1所述的封装IC，其中，所述芯片焊盘和接地焊垫被配置成在通电时处于地电位。
9.根据权利要求1所述的封装IC，其中，所述芯片包括相控阵，所述相控阵被配置成按大约1兆赫兹到100吉赫兹之间的频率操作。
10.根据权利要求1所述的封装IC，其中，所述芯片具有第二接地焊垫，所述封装件具有第二接地引线，所述第二接地焊垫电连接至所述芯片焊盘和所述第二接地引线二者。
11.根据权利要求10所述的封装IC，其中，所述信号引线定位在所述接地引线与所述第二接地引线之间。
12.一种封装IC，所述封装IC包括：
相控阵芯片，所述相控阵芯片具有多个芯片RF组，每个芯片RF组都包括第一接地焊垫、信号焊垫、以及第二接地焊垫；
封装件，所述封装件具有芯片焊盘和多个封装件RF组，每个封装件RF组都包括第一接地引线、信号引线、以及第二接地引线；以及
多个连接件，所述多个连接件连接给定芯片RF组与给定封装件RF组，所述给定芯片RF组具有给定第一接地焊垫和给定第二接地焊垫以及给定信号焊垫，所述给定封装件RF组具有给定第一接地引线和给定第二接地引线以及给定信号引线，
所述多个连接件包括第一连接件、第二连接件、以及第三连接件，所述第一连接件将所述给定第一接地焊垫连接至所述给定第一接地引线，所述第二连接件将所述给定第二接地焊垫连接至所述给定第二接地引线，以及所述第三连接件将所述给定信号焊垫连接至所述给定信号引线，
所述多个连接件还具有第一焊盘连接件，所述第一焊盘连接件将所述给定第一接地焊垫连接至所述芯片焊盘，
所述多个连接件还具有第二焊盘连接件，所述第二焊盘连接件将所述给定第二接地焊垫连接至所述芯片焊盘。
13.根据权利要求12所述的封装IC，其中，所述给定信号引线定位在所述第一接地引线与所述第二接地引线之间。
14.根据权利要求12所述的封装IC，其中，所述第一焊盘连接件包括从所述给定第一接地焊垫延伸的通孔。
15.根据权利要求14所述的封装IC，其中，所述第二焊盘连接件包括从所述给定第二接地焊垫延伸的通孔。
16.根据权利要求12所述的封装IC，其中，所述第一焊盘连接件包括第一焊线。
17.根据权利要求16所述的封装IC，其中，所述第二焊盘连接件包括从所述给定第二接地焊垫延伸的第二焊线。
18.根据权利要求12所述的封装IC，其中，所述封装件包括引线框封装件。
19.根据权利要求12所述的封装IC，其中，所述相控阵芯片按大约1兆赫兹与100吉赫兹之间的频率操作。
20.根据权利要求12所述的封装IC，其中，所述芯片包括：CMOS、绝缘体上硅SOI CMOS、或硅锗BiCMOS基板。
21.一种形成封装IC的方法，所述方法包括以下步骤：
设置芯片，所述芯片具有接地焊垫和信号焊垫；
设置引线框基部，所述引线框基部具有芯片焊盘、接地引线、以及信号引线；
电连接所述芯片的所述信号焊垫与所述引线框基部的所述信号引线；
电连接所述芯片的所述接地焊垫与所述引线框基部的所述接地引线；
电连接所述芯片的所述接地焊垫与所述引线框基部的所述芯片焊盘；以及
包封所述引线框基部的至少一部分和所述芯片。
22.根据权利要求21所述的方法，其中，电连接所述芯片的所述接地焊垫与所述芯片焊盘的步骤包括：将所述芯片固定至所述引线框。
23.根据权利要求21所述的方法，其中，所述芯片包括从所述接地焊垫延伸的通孔，电连接所述芯片的所述接地焊垫与所述芯片焊盘的步骤包括：电连接所述通孔与所述芯片焊盘。
24.根据权利要求21所述的方法，其中，电连接所述芯片的所述接地焊垫与所述引线框基部的所述芯片焊盘的步骤包括：在所述芯片的所述接地焊垫与所述芯片焊盘之间连接焊线。
CN201680047952.6A 2015-09-04 2016-08-25 用于减轻封装集成电路中的寄生耦合的方法和装置 Pending CN108352329A (zh)

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