TWI479577B - 形成屏障材料於晶粒之周圍以減少翹曲之半導體裝置和方法 - Google Patents

形成屏障材料於晶粒之周圍以減少翹曲之半導體裝置和方法 Download PDF

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TWI479577B
TWI479577B TW099123254A TW99123254A TWI479577B TW I479577 B TWI479577 B TW I479577B TW 099123254 A TW099123254 A TW 099123254A TW 99123254 A TW99123254 A TW 99123254A TW I479577 B TWI479577 B TW I479577B
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semiconductor die
encapsulant
semiconductor
barrier material
interconnect structure
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TW099123254A
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English (en)
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TW201108335A (en
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Reza A Pagaila
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Stats Chippac Ltd
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Description

形成屏障材料於晶粒之周圍以減少翹曲之半導體裝置和方法
本發明大體上關於半導體裝置，且更明確地說，係關於形成屏障材料於半導體晶粒之周圍以減少翹曲之半導體裝置和方法。
在現代的電子產品中經常會發現半導體裝置。半導體裝置會有不同數量與密度的電子組件。離散半導體裝置通常含有一種類型的電子組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。整合半導體裝置典型地含有數百個至數百萬個電子組件。整合半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施廣泛的功能，例如，高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置利用半導體材料的電氣特性。半導體材料的原子結構使得可藉由施加電場或基礎電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至該半導體材料之中，以便操縱及控制該半導體裝置的傳導性。
半導體裝置含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)控制電流的流動。藉由改變摻雜程度以及施加電場或基礎電流，該電晶體會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)創造用以實施各式各樣電功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電連接以形成讓該半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常相同並且含有藉由電連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的晶粒並且封裝該晶粒以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便係製造較小的半導體裝置。較小的裝置典型地會消耗較少電力，具有較高效能，並且能夠更有效地生產。此外，較小的半導體裝置還具有較小的覆蓋面積，這係為較小的末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小以及較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電互連材料及封裝材料而導致具有較小覆蓋面積的半導體裝置封裝。
在含有被堆疊在多層上之多個半導體裝置的扇出晶圓程度晶片級封裝(Fan-Out Wafer Level Chip Scale Package，FO-WLCSP)中的電互連能夠利用下面來完成：導體的直通矽晶穿孔(Through Silicon Via，TSV)、直通孔洞穿孔(Through Hole Via，THV)或是鍍銅傳導柱。多個穿孔會使用雷射鑽鑿或深反應離子蝕刻(Deep Reactive Ion Etching，DRIE)被形成在該晶粒附近的矽質材料或有機材料中。該等穿孔會被傳導材料填充(舉例來說，藉由使用電鍍製程的銅沉積法)，用以形成該等傳導直通矽晶穿孔與直通孔洞穿孔。該等直通矽晶穿孔與直通孔洞穿孔會經由被形成跨越每一個半導體晶粒的增進互連結構來進一步連接。一囊封劑會被沉積在該堆疊半導體晶粒的上方。
扇出晶圓程度晶片級封裝的一共同故障問題係翹曲。當半導體晶粒被鑲嵌至一暫時性載體以進行囊封時，囊封劑和暫時性載體的熱膨脹係數(Coefficient of Thermal Expansion，CTE)之間的匹配誤差會引起可能導致翹曲的應力。此外，在形成扇出晶圓程度晶片級封裝之後，即在溫度循環測試或極端溫度測試期間，囊封劑和增進互連結構的熱膨脹係數之間的匹配誤差也會引起可能導致翹曲的應力。當缺陷的代價很高的時候，因翹曲所造成的裝置故障應該要被避免或者至少要被最小化；尤其是在製造過程的最後階段處。
在製造過程期間必須減少扇出晶圓程度晶片級封裝中的翹曲。據此，於一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一暫時性載體，其具有一用於一第一半導體晶粒的指定區；將屏障材料沉積在一第一半導體晶粒的指定區周圍的暫時性載體之上；鑲嵌該第一半導體晶粒於該暫時性載體之上，使該第一半導體晶粒的主動表面朝向該指定區；以及將一囊封劑沉積在該第一半導體晶粒與暫時性載體的上方。該屏障材料經過選擇，以便具有對應於該囊封劑之熱膨脹係數的熱膨脹係數。該方法還進一步包含下面步驟：移除該暫時性載體，以便露出該囊封劑的第一側及該第一半導體晶粒的主動表面；以及在該囊封劑的該第一側上方形成一第一互連結構。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一暫時性載體，其具有一用於一第一半導體組件的指定區；將屏障材料沉積在一第一半導體組件的指定區周圍的載體之上；鑲嵌該第一半導體組件至該載體上的該指定區；將一囊封劑沉積在該第一半導體組件與暫時性載體的上方；移除該暫時性載體；以及在該囊封劑的上方形成一第一互連結構。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一第一半導體組件；將屏障材料沉積在該第一半導體組件的周圍並且將一囊封劑沉積在該第一半導體組件的上方。該屏障材料經過選擇，以便具有對應於該囊封劑之熱膨脹係數的熱膨脹係數。該方法還進一步包含下面步驟：在該囊封劑的上方形成一第一互連結構。
於另一實施例中，本發明係一種半導體裝置，其包括一第一半導體組件以及被沉積在該第一半導體組件周圍的屏障材料。一囊封劑會被沉積在該第一半導體組件的上方。該屏障材料經過選擇，以便具有對應於該囊封劑之熱膨脹係數的熱膨脹係數。一第一互連結構會被形成在該囊封劑的上方。
下面的說明書中會參考圖式於一或多個實施例中來說明本發明，於該等圖式中，相同的符號代表相同或相似的元件。雖然本文會以達成本發明目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效物所定義的本發明的精神與範疇內可能併入的替代、修正、以及等效物。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電子組件和被動式電子組件，它們會被電連接而形成功能性電路。主動式電子組件(例如電晶體與二極體)能夠控制電流的流動。被動式電子組件(例如電容器、電感器、電阻器、以及變壓器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻、以及平坦化。摻雜會藉由離子植入或是熱擴散將雜質引入至半導體材料之中。摻雜製程會修改主動式裝置中半導體材料的導電性，將該半導體材料轉換成絕緣體、導體，或是響應於電場或基礎電流來動態改變半導體材料傳導性。含有摻雜的不同類型和程度的範圍，參雜安排為必要的，以在施加一電場或基礎電流時讓該電晶體會提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料構成。該等層能夠藉由各式各樣的沉積技術來形成，其某種程度上取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程、以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件、或是組件之間的電連接線的一部分。
該等層能夠利用光微影術來圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一已圖樣化層。或者，某些類型的材料會利用無電極電鍍以及電解質電鍍之類的技術，藉由將該材料直接沉積至先前沉積及/或蝕刻製程所形成的區域或空隙(void)之中而被圖樣化。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。在研磨期間加入研磨材料以及腐蝕性的化學藥劑到晶圓的表面。結合研磨料的機械作用及化學藥劑的磨蝕作用來移除任何不規律的表面形狀，從而產生均勻平坦的表面。
後端製造係指將已完成的晶圓切割或單體化裁切成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為單體化裁切晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。該晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別晶粒便會被鑲嵌至包含接針或接觸觸墊的封裝基板，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸觸墊接著會被連接至該封裝裡面的接觸觸墊。該等電連接線可利用焊料凸塊、短柱凸塊、導電膏、或是焊線來製成。一囊封劑或是其它模造材料會被沉積在該封裝的上方，以提供物理性支撐和電隔離。接著，該已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖1說明一電子裝置50，其具有一晶片載體基板或是印刷電路板(PCB)52，其表面上鑲嵌複數個半導體封裝。電子裝置50可能係某一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋目的，圖1中顯示不同類型的半導體封裝。
電子裝置50可能係一獨立系統，其會使用該等半導體封裝來實施一或多項電功能。或者，電子裝置50亦可能係一較大型系統中的一子組件。舉例來說，電子裝置50可能係一圖形卡、一網路介面卡、或是能夠被插入在一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、射頻電路、離散式裝置、或是其它半導體晶粒或電子組件。
在圖1中，印刷電路板52提供一通用基板，用以結構性支撐及電互連被鑲嵌在該印刷電路板之上的半導體封裝。利用蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程形成導體訊號線路54於印刷電路板52的一表面上方或是多層裡面。訊號線路54在該等半導體封裝、被鑲嵌的組件、以及其它外部系統組件中的每一者之間提供電通訊。線路54還會提供連接至每一個該等半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種以機械方式及電氣方式將該半導體晶粒附接至一中間載體的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載體附接至該印刷電路板。於其它實施例中，一半導體裝置可能僅有該第一層封裝，其中，該晶粒會以機械方式及電氣方式直接被鑲嵌至該印刷電路板。
為達解釋目的，在印刷電路板52上之顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，還顯示被鑲嵌在印刷電路板52之上的數種類型之第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載體(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，任何半導體封裝之組合、任何結合第一及第二層封裝形式之組合和其他電子組件皆能夠被連接至印刷電路板52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製造的組件併入電子裝置和系統之中。因為該等半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而讓消費者的成本會較低。
圖2a至2c所示的係示範性半導體封裝。圖2a所示的係被鑲嵌在印刷電路板52之上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被執行為被形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74之主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸觸墊76係一或多層傳導材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或是銀(Ag))製成，並且會被電連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂)被黏著至一中間載體78。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與印刷電路板52之間提供電互連。囊封劑84會被沉積在該封裝的上方，防止濕氣和粒子進入該封裝並污染晶粒74或焊線82以達環境保護的目的。
圖2b所示的係被鑲嵌在印刷電路板52之上的BCC 62的進一步細節。半導體晶粒88會利用底層填充材料或環氧樹脂膠黏材料92被黏著在載體90的上方。焊線94會在接觸觸墊96與98之間提供第一層封裝互連。模造化合物或囊封劑100會被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。接觸觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在印刷電路板52的表面上方以防止氧化。接觸觸墊102會被電連接至印刷電路板52中的一或多條導體訊號線路54。凸塊104會被形成在BCC 62的接觸觸墊98和印刷電路板52的接觸觸墊102之間。
在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載體106。半導體晶粒58的主動區108含有類比電路或數位電路，該等類比電路或數位電路會被執行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、傳導層、以及介電層。舉例來說，該電路可能包含在主動區108裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載體106。
BGA 60會利用凸塊112的BGA樣式第二層封裝以電氣方式及機械方式被連接至印刷電路板52。半導體晶粒58會經由凸塊110、訊號線114、以及凸塊112被電連接至印刷電路板52中的導體訊號線路54。一模造化合物或囊封劑116會被沉積在半導體晶粒58和載體106的上方，以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置從半導體晶粒58上的主動式裝置至印刷電路板52上的傳導軌提供一條短的電傳導路徑，以便縮短訊號傳導距離、降低電容、並且改善整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接連接至印刷電路板52，而沒有中間載體106。
圖3a至3e所示的係和圖1及2a至2c有關之在一半導體晶粒周圍形成屏障材料以減少扇出晶圓程度晶片級封裝中之翹曲的製程。在圖3a中，一晶圓形狀的基板或載體120含有暫時性或犧牲性基礎材料，例如，矽、聚合物、聚合復合物、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、或是其它合宜的低成本剛性材料或大型半導體材料，用以達到結構性支撐的目的。載體120亦可能為膠帶。一非必要的介面層122可能會被形成在載體120的上方，成為一暫時性的焊接膜或是蝕刻阻止層。
載體120具有一被指定用於鑲嵌一半導體晶粒的區域123。一屏障材料124會被沉積在介面層122上方，至少部分或完全在區域123的周圍。屏障材料124可能係膠黏劑、聚合物、或是金屬層。屏障材料124會藉由網印製程、電解質電鍍製程、無電極電鍍製程、噴塗製程、或是其它合宜的沉積製程來形成，端視該材料而定。
在圖3b中，半導體晶粒或組件126會被鑲嵌至介面層122上的指定區123，主動表面130上的接觸觸墊128向下朝向載體120。主動表面130含有類比電路或數位電路，該等類比電路或數位電路會被執行作為形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面130裡面的一或多個電晶體、二極體、以及其它電路元件，用以執行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒126可能還含有用於射頻訊號處理的整合被動元件(IPD)，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。
在圖3c中，一囊封劑或模造化合物132會利用焊膏印刷(paste printing)塗敷機、壓縮模造(compressive molding)塗敷機、轉印模造(transfer molding)塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在屏障材料124與半導體晶粒126的上方。囊封劑132可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑132係非導體並且為半導體裝置提供環境保護，避免受到外部元素與污染物破壞。
在圖3d中，暫時性載體120與非必要的介面層122會藉由化學性蝕刻、機械性剝離、CMP、機械性研磨、熱烘烤、雷射掃描或是濕式剝除被移除。一底邊增進互連結構134會被形成在屏障材料124、半導體晶粒126、以及囊封劑132的上方。該增進互連結構134包含一絕緣層或鈍化層136，其含有由二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)或是具有雷同絕緣特性及結構性特性的其它材料所製成的一或多層。該絕緣層136係利用PVD、CVD、印刷、旋塗、噴塗、燒結或是熱氧化方法所形成。
該底邊增進互連結構134還進一步包含一導電層138，其會使用圖樣化與金屬沉積製程(例如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍)被形成在絕緣層136中。傳導層138可能係由Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料所製成的一或多層。傳導層138中的一部分會被電連接至半導體晶粒126的接觸觸墊128。傳導層138中的其它部分可能為共電或被電隔離，端視該半導體裝置的設計及功能而定。
在圖3e中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程(ball drop)、或是網印製程被沉積在增進互連結構134的上方並且會被電連接至傳導層138。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，具有一非必要的助熔溶劑。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至傳導層138。於一實施例中，該凸塊材料會藉由將該凸塊材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊140。於某些應用中，凸塊140會被二次回焊，以便改善和傳導層138的電接觸效果。該等凸塊也能夠被壓縮焊接至傳導層138。凸塊140代表能夠被形成在傳導層138上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、短柱凸塊、微凸塊、或是其它電互連線。
半導體晶粒126會利用鋸片或雷射切割裝置142被單體化裁切成個別的半導體裝置。圖4所示的係在單體化裁切之後被鑲嵌至印刷電路板146的扇出晶圓程度晶片級封裝144。半導體晶粒126會被電連接至底邊增進互連結構134以及凸塊140。屏障材料124具有和囊封劑132反向的翹曲特徵。舉例來說，隨著溫度升高，囊封劑132會有內凹的傾向而屏障材料124會有外凸的傾向。由於反向翹曲特性的關係，在囊封之後，屏障材料124會讓半導體晶粒126的周圍變硬。此外，屏障材料124經過選擇，俾使得其熱膨脹係數會對應於囊封劑132的熱膨脹係數，也就是，屏障材料124的熱膨脹係數相似於或略小於囊封劑132的熱膨脹係數。屏障材料124的熱膨脹係數會在溫度循環測試與極端溫度測試期間在扇出晶圓程度晶片級封裝144中補償因被鑲嵌至增進互連結構134的經囊封半導體晶粒126所引起的應力。藉由減少翹曲及由熱膨脹係數誘發的應力，扇出晶圓程度晶片級封裝144的焊接故障會下降，尤其是在半導體晶粒的周圍。
圖5所示的係一被形成在半導體晶粒126及囊封劑132的頂邊與側邊的遮蔽層150。遮蔽層150可能係Cu、Al、鐵氧體或羰基鐵(carbonyl iron)、不鏽鋼、鎳銀合金、低碳鋼、矽鐵鋼(silicon-iron steel)、金屬箔、環氧樹脂、導體樹脂、以及能夠阻隔或吸收電磁干擾(ElectroMagnetic Interference，EMI)、射頻干擾(Radio Frequency Interference，RFI)、以及其它裝置間干擾的其它金屬與復合物。遮蔽層150亦可能係非金屬材料，例如，碳黑或鋁質薄片，用以降低電磁干擾與射頻干擾的效應。遮蔽層150會經由傳導層138被接地至凸塊140。
圖6所示的係被形成在半導體晶粒126的接觸觸墊128及增進互連結構134中之傳導層138之間的互連凸塊152。半導體晶粒126會受到屏障材料124的支撐，其會減少凸塊152塌陷的可能性。
在圖7所示的扇出晶圓程度晶片級封裝154中，屏障材料124會向上形成至囊封劑132的頂端表面。屏障材料124會在扇出晶圓程度晶片級封裝154處被露出。
在圖8所示的屏障材料124中，其會向上形成至囊封劑132的頂端表面並且自該扇出晶圓程度晶片級封裝處被露出，如圖7中所述。一熱介面材料(Thermal Interface Material，TIM)156會被沉積在半導體晶粒126的背表面上方，和主動表面130反向。熱介面材料156可能係氧化鋁、氧化鋅、氮化硼或是粉銀(pulverized silver)。一散熱片158會被鑲嵌在熱介面材料156、囊封劑132以及屏障材料124的上方。散熱片158可能係Al、Cu或是具有高導熱係數的另一材料，以便為半導體晶粒126提供熱消散作用。熱介面材料156有助於分佈與消散半導體晶粒126所產生的熱。
圖9所示的係扇出晶圓程度晶片級封裝的另一實施例，其中，屏障材料會被形成在該半導體晶粒的周圍。一屏障材料160會被沉積在一暫時性載體及非必要介面層上方，至少部分或完全在被指定用於半導體晶粒164的區域的周圍。屏障材料160可能係膠黏劑、聚合物、或是金屬層。屏障材料160會藉由網印製程、電解質電鍍製程、無電極電鍍製程、噴塗製程、或是其它合宜的沉積製程來形成，端視該材料而定。
一或多層的光阻會被沉積在該載體和非必要的介面層上方。該光阻中的一部分會藉由蝕刻顯影製程被裸露且移除，用以形成多個穿孔。傳導材料(例如Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、鎢(W)、焊料、多晶矽、或是它們的組合)會利用選擇性電鍍製程被沉積在該等穿孔中。該光阻會被剝除，留下個別的傳導柱162。於另一實施例中，傳導柱140會被形成短柱凸塊或堆疊凸塊。
一半導體晶粒或組件164會被鑲嵌至該載體和非必要的介面層，主動表面168上的接觸觸墊166會向下朝向該載體。主動表面168含有類比電路或數位電路，該等類比電路或數位電路會被執行作為形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面168裡面的一或多個電晶體、二極體、以及其它電路元件，用以執行類比電路或數位電路，例如，數位訊號處理器、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒164可能還含有用於射頻訊號處理的整合被動元件，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。
一囊封劑或模造化合物170會利用焊膏印刷(paste printing)塗敷機、壓縮模造(compressive molding)塗敷機、轉印模造(transfer molding)塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在屏障材料160與半導體晶粒164的上方。囊封劑170可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑170係非導體並且會為半導體裝置提供環境保護，避免受到外部元素與污染物破壞。
該暫時性載體與非必要的介面層會藉由下面方式被移除：化學性蝕刻、機械性剝離、CMP、機械性研磨、熱烘烤、雷射掃描、或是濕式剝除。一底邊增進互連結構174會被形成在屏障材料160、半導體晶粒164、以及囊封劑170的上方。該增進互連結構174包含一絕緣層或鈍化層176，其含有由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3或是具有相似絕緣特性及結構性特性的其它材料。該絕緣層176係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化所形成。
該底邊增進互連結構174還進一步包含一導電層178，其會使用圖樣化與金屬沉積製程(例如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍)被形成在絕緣層176中。傳導層178可能係由Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料所製成的一或多層。傳導層178中的一部分會被電連接至半導體晶粒164的接觸觸墊166；傳導層178中的另一部分會被電連接至傳導柱162。傳導層178中的其它部分可能為共電或被電隔離，端視該半導體裝置的設計及功能而定。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在增進互連結構174的上方並且會被電連接至傳導層178。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，具有一非必要的助熔溶劑。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至傳導層178。於一實施例中，該凸塊材料會藉由將該凸塊材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊180。於某些應用中，凸塊180會被二次回焊，以便改善和傳導層178的電接觸效果。該等凸塊也能夠被壓縮焊接至傳導層178。凸塊180代表能夠被形成在傳導層178上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、短柱凸塊、微凸塊、或是其它電互連線。
一頂邊增進互連結構184會被形成在囊封劑170中於主動表面168對面的一表面的上方。該增進互連結構184包含一絕緣層或鈍化層186，其含有由SiO2、Si3N4、SiON、Ta2O5、A12O3或是具有雷同絕緣特性及結構性特性的其它材料所製成的一或多層。該絕緣層186係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化所形成。
該頂邊增進互連結構184還進一步包含一導電層188，其會使用圖樣化與金屬沉積製程(例如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍)被形成在絕緣層186中。傳導層188可能係由Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料所製成的一或多層。傳導層188中的一部分會被電連接至傳導柱162。傳導層188中的其它部分可能為共電或被電隔離，端視該半導體裝置的設計及功能而定。
一半導體晶粒或組件190會被鑲嵌至頂邊增進互連結構184，主動表面194上的接觸觸墊192會向下朝向該增進互連結構。主動表面194含有類比電路或數位電路，該等類比電路或數位電路會被執行作為形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面194裡面的一或多個電晶體、二極體、以及其它電路元件，用以執行類比電路或數位電路，例如，數位訊號處理器、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒190可能還含有用於射頻訊號處理的整合被動元件，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。於另一實施例中，一離散半導體裝置會被鑲嵌至頂邊增進互連結構184。凸塊196會將半導體晶粒190的接觸觸墊192電連接至傳導層188。一底層填充材料198(例如環氧樹脂)會被沉積在半導體晶粒190的下面。
在扇出晶圓程度晶片級封裝200中，半導體晶粒164與190會經由z方向互連傳導柱162被電連接至底邊增進互連結構174與凸塊180及頂邊增進互連結構184。屏障材料160具有和囊封劑170反向的翹曲特徵。舉例來說，隨著溫度升高，囊封劑170會有內凹的傾向而屏障材料160會有外凸的傾向。由於反向翹曲特性的關係，在囊封之後，屏障材料160會讓半導體晶粒164的周圍變硬。此外，屏障材料160還經過選擇，俾使得其熱膨脹係數會對應於囊封劑170的熱膨脹係數，也就是，屏障材料160的熱膨脹係數雷同於或略小於囊封劑170的熱膨脹係數。屏障材料170的熱膨脹係數會在溫度循環測試與極端溫度測試期間在扇出晶圓程度晶片級封裝200中補償因被鑲嵌至增進互連結構174的經囊封半導體晶粒164所引起的應力。藉由減少翹曲及由熱膨脹係數引起的應力，扇出晶圓程度晶片級封裝200的焊接故障會下降，尤其是在半導體晶粒的周圍。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會瞭解，可以對該些實施例進行修正與改變，其並不會脫離隨後申請專利範圍中所提出的本發明的範疇。
50．．．電子裝置
52．．．印刷電路板(PCB)
54．．．線路
56．．．焊線封裝
58．．．覆晶
60．．．球柵陣列(BGA)
62．．．凸塊晶片載體(BCC)
64．．．雙直列封裝(DIP)
66．．．平台格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．方形扁平無導線封裝(QFN)
72．．．方形扁平封裝
74．．．半導體晶粒
76．．．接觸觸墊
78．．．中間載體
80．．．導體導線
82．．．焊線
84．．．囊封劑
88．．．半導體晶粒
90．．．載體
92．．．底層填充材料或環氧樹脂膠黏材料
94．．．焊線
96．．．接觸觸墊
98．．．接觸觸墊
100．．．模造化合物或囊封劑
102．．．接觸觸墊
104．．．凸塊
106．．．中間載體
108．．．主動區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．模造化合物或囊封劑
120．．．基板或載體
122．．．介面層
123．．．區域
124．．．屏障材料
126．．．半導體晶粒或組件
128．．．接觸觸墊
130．．．主動表面
132．．．囊封劑或模造化合物
134．．．互連結構
136．．．絕緣層或鈍化層
138．．．傳導層
140．．．球狀的丸體或凸塊
142．．．鋸片或雷射切割裝置
144．．．扇出晶圓程度晶片級封裝
146．．．印刷電路板
150．．．遮蔽層
152．．．凸塊
154．．．扇出晶圓程度晶片級封裝
156．．．熱介面材料(TIM)
158．．．散熱片
160．．．屏障材料
162．．．傳導柱
164‧‧‧半導體晶粒
166‧‧‧接觸觸墊
168‧‧‧主動表面
170‧‧‧模造化合物或囊封劑
174‧‧‧互連結構
176‧‧‧絕緣層
178‧‧‧傳導層
180‧‧‧球狀的丸體或凸塊
184‧‧‧互連結構
186‧‧‧絕緣層
188‧‧‧傳導層
190‧‧‧半導體晶粒或組件
192‧‧‧接觸觸墊
194‧‧‧主動表面
196‧‧‧凸塊
198‧‧‧底層填充材料
200‧‧‧扇出晶圓程度晶片級封裝
圖1係說明一印刷電路板，在其表面上鑲嵌著不同類型的封裝；
圖2a至2c係說明被鑲嵌至該印刷電路板的代表性半導體封裝的進一步細節；
圖3a至3e係說明在一半導體晶粒周圍形成屏障材料以減少扇出晶圓程度晶片級封裝中之翹曲的製程；
圖4係說明被鑲嵌至一印刷電路板的晶圓程度晶片級封裝，屏障材料會被形成在該半導體晶粒周圍；
圖5係說明一被形成在該半導體晶粒周圍的EMI遮蔽層；
圖6係說明受到該屏障材料支撐的半導體晶粒，以便防止互連凸塊塌陷；
圖7係說明向上延伸到囊封劑之頂端表面的屏障材料；
圖8係說明被形成在半導體晶粒上方的熱介面材料與散熱片；以及
圖9係說明被形成在囊封劑上方的半導體晶粒與頂邊增進互連結構。
124．．．屏障材料
126．．．半導體晶粒或組件
128．．．接觸觸墊
130．．．主動表面
132．．．囊封劑或模造化合物
134．．．互連結構
136．．．絕緣層或鈍化層
138．．．傳導層
140．．．球狀的丸體或凸塊
144．．．扇出晶圓程度晶片級封裝
146．．．印刷電路板

Claims (15)

  1. 一種製造半導體裝置的方法，其包括：提供一載體，其具有一用於一第一半導體晶粒的指定區；將屏障材料沉積在該第一半導體晶粒的指定區周圍的載體之上；鑲嵌該第一半導體晶粒至該載體上的該指定區；將一囊封劑沉積在該第一半導體晶粒與載體的上方，該囊封劑包含一翹曲特徵，其反向於該屏障材料之翹曲特徵，以使得該第一半導體晶粒的周圍變硬；移除該載體；以及在該囊封劑的上方形成一第一互連結構。
  2. 如申請專利範圍第1項的方法，其進一步包含選擇該屏障材料的熱膨脹係數為小於或等於該囊封劑的熱膨脹係數。
  3. 如申請專利範圍第1項的方法，其進一步包含在該第一半導體晶粒的上方形成一遮蔽層或一散熱片。
  4. 如申請專利範圍第1項的方法，其進一步包含：在該第一半導體晶粒的上方形成一第二互連結構；以及將一第二半導體晶粒鑲嵌至該第二互連結構。
  5. 如申請專利範圍第1項的方法，其進一步包含：藉由該屏障材料來支撐該第一半導體晶粒；以及在該第一半導體晶粒上的一接觸觸墊及第一互連結構之間形成一凸塊。
  6. 一種製造半導體裝置的方法，其包括：提供一第一半導體晶粒；將含有一第一翹曲特徵之屏障材料沉積圍繞該第一半導體晶粒；將含有相反於該第一翹曲特徵之一第二翹曲特徵的一囊封劑沉積圍繞該第一半導體晶粒。
  7. 如申請專利範圍第6項的方法，其中，該屏障材料的熱膨脹係數(CTE)小於或等於該囊封劑的熱膨脹係數。
  8. 如申請專利範圍第6項的方法，其進一步包含在該囊封劑和該第一半導體晶粒上方形成一遮蔽層或一散熱片。
  9. 如申請專利範圍第6項的方法，其進一步包含形成該屏障材料，使其向上直到該囊封劑的頂端表面。
  10. 如申請專利範圍第6項的方法，其進一步包含：在該第一半導體晶粒的一第一表面上方形成一第一互連結構；在相反於該半導體晶粒之該第一表面的該第一半導體晶粒之一第二表面的上方形成一第二互連結構；以及在該第一和第二互連結構之間形成一傳導柱。
  11. 一種半導體裝置，其包括：一第一半導體晶粒；一囊封劑，其會被沉積在該第一半導體晶粒的上方；一屏障材料，其會被沉積圍繞該第一半導體晶粒的一周圍，該屏障材料經過選擇，以便具有對應於該囊封劑之熱膨脹係數的熱膨脹係數以及一相反於該囊封劑之翹曲特徵的翹曲特徵；以及 一第一互連結構，其會被形成在該囊封劑的上方。
  12. 如申請專利範圍第11項的半導體裝置，其中，該屏障材料的熱膨脹係數小於或等於該囊封劑的熱膨脹係數。
  13. 如申請專利範圍第11項的半導體裝置，其進一步包含在該第一半導體晶粒的上方形成一遮蔽層。
  14. 如申請專利範圍第11項的半導體裝置，其中該屏障材料的該翹曲特徵為凹的或凸的。
  15. 如申請專利範圍第11項的半導體裝置，其進一步包含：一第二互連結構，其會被形成在該第一半導體晶粒的上方；以及一第二半導體晶粒，其會被鑲嵌至該第二互連結構。
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