CN101996894A - 半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法 - Google Patents

半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法 Download PDF

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CN101996894A
CN101996894A CN2010102542177A CN201010254217A CN101996894A CN 101996894 A CN101996894 A CN 101996894A CN 2010102542177 A CN2010102542177 A CN 2010102542177A CN 201010254217 A CN201010254217 A CN 201010254217A CN 101996894 A CN101996894 A CN 101996894A
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semiconductor device
sealant
cte
interconnection structure
semiconductor element
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CN101996894B (zh
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R·A·帕盖拉
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法。一种半导体器件具有临时载体，所述临时载体具有用于第一半导体管芯的指定区域。坝材料被沉积在用于第一半导体管芯的指定区域周围的载体上。第一半导体管芯被安装到载体上的指定区域。在第一半导体管芯和载体上沉积密封剂。坝材料被选择为具有等于或小于密封剂的CTE的CTE。除去所述临时载体以暴露密封剂和第一半导体管芯。在密封剂上形成第一互连结构。可以在第一半导体管芯上形成EMI屏蔽层。在第一半导体管芯的后表面上形成第二互连结构。在第一和第二互连结构之间形成导电柱。第二半导体管芯被安装到第二互连结构。

Description

半导体器件和围绕管芯周边形成坝材料以减小翘曲的方法 
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和围绕半导体管芯周边形成坝(dam)材料以减小翘曲(warpage)的方法。 
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。 
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。 
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流(base current)或者通过掺杂工艺来操纵(manipulated)它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。 
半导体器件包括有源和无源电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器、和电感器)产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。 
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的 表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化(singulating)单个管芯并且封装管芯以提供结构支撑和环境隔离。 
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积(footprint)，其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占地面积的半导体器件封装。 
可以利用导电直通硅通路(TSV)、直通孔通路(THV)、或镀铜导电柱实现包含堆叠于多级之上的半导体器件的扇出型晶片级芯片规模封装(FO-WLCSP)中的电互连。利用激光钻孔或深反应离子刻蚀(DRIE)在管芯周围的硅或有机材料中形成通路。例如使用电镀工艺通过铜沉积，利用导电材料来填充所述通路，以形成导电TSV和THV。所述TSV和THV进一步通过跨越每个半导体管芯形成的内建互连结构连接。在堆叠半导体管芯上沉积密封剂。 
FO-WLCSP的普通的故障问题是翘曲。当半导体管芯被安装到临时载体进行密封时，密封剂和临时载体的热膨胀系数(CTE)之间的失配引起可能导致翘曲的应力。另外，在形成FO-WLCSP后，密封剂和内建互连结构的CTE之间的失配引起可能导致翘曲的应力(例如在温度循环或极端温度测试期间)。由于翘曲引起的器件故障应当被避免或至少被最小化，尤其是在制造工艺的最后阶段(这时缺陷的代价很高)。 
发明内容
在制造工艺期间存在对减小FO-WLCSP中的翘曲的需要。因此，在一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供具有用于第一半导体管芯的指定区域的临时载体，在用于第一半导体管芯的指定区域周围的临时载体上沉积坝材料，安装第一半导体管芯并且它的有源表面面向临时载体上的指定区域，以及在第一半导体管芯和临时载体上沉积密封剂。选择所述坝材料为具有与密封剂的CTE相对应的CTE。所述方法进一步包括以下步骤：除去临时载体以暴露密封剂的第一侧和第一半导体管芯的有源表面，以及在密封剂的第一侧上形成第一互连结构。 
在另一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供具有用于第一半导体部件的指定区域的载体，在用于第一半导体部件的指定区域周围的载体上沉积坝材料，安装第一半导体部件到载体上的指定区域，在第一半导体部件和临时载体上沉积密封剂，除去所述载体，以及在密封剂上形成第一互连结构。 
在另一个实施例中，本发明是包括以下步骤的制造半导体器件的方法：提供第一半导体部件，围绕第一半导体部件的周边沉积坝材料，以及在第一半导体部件上沉积密封剂。所述坝材料被选择为具有与密封剂的CTE相对应的CTE。所述方法进一步包括在密封剂上形成第一互连结构的步骤。 
在另一个实施例中，本发明是包括第一半导体部件和围绕第一半导体部件的周边沉积的坝材料的半导体器件。在第一半导体部件上沉积密封剂。坝材料被选择为具有与密封剂的CTE相对应的CTE。在密封剂上形成第一互连结构。 
附图说明
图1示出具有安装到其表面的不同类型封装的PCB； 
图2a-2c示出安装到所述PCB的典型半导体封装的更多细节； 
图3a-3e示出围绕半导体管芯的周边形成坝材料以减少FO-WLCSP中的翘曲的工艺； 
图4示出具有围绕半导体管芯的周边形成的坝材料的、被安装到PCB的FO-WLCSP； 
图5示出形成在半导体管芯周围的EMI屏蔽层； 
图6示出由坝材料支撑以防止互连凸块坍塌(collapse)的半导体管芯； 
图7示出向上延伸到密封剂的顶部表面的坝材料； 
图8示出形成在半导体管芯上的TIM和热沉；以及 
图9示出半导体管芯和形成在密封剂上的顶侧内建互连结构。 
具体实施方式
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器， 产生执行电路功能所必需的电压和电流之间的关系。 
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。 
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀、以及无电电镀(electroless plating)工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。 
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。 
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌(topography)，产生均匀的平面。 
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区(saw street)或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块(stud bump)、导电胶、或线结合(wirebond)来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中 并且半导体器件的功能可以用到其它系统部件。 
图1示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，所述芯片载体衬底或印刷电路板(PCB)52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。 
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。 
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线(trace)54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。 
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。 
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(land grid array，LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(quad flat non-leaded package，QFN)70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得 到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。 
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料(例如铝(AL)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、或银(Ag))的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料(例如热的环氧树脂)将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。 
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填料(underfill)或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级包装(packing)互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。 
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。 
BGA 60利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯 片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。 
相对于图1和2a-2c，图3a-3e示出围绕半导体管芯的周边形成坝材料以减小FO-WLCSP中的翘曲的工艺。在图3a中，晶片形式的衬底或载体120包括临时或牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或用于结构支撑的其它合适的低成本、刚性材料或体半导体材料。载体120也可以是带。可以在载体120上形成可选界面层122作为临时粘性结合膜或腐蚀停层。 
载体120具有指定用来安装半导体管芯的区域123。在界面层122上沉积坝材料124，至少部分地或完全围绕区域123的周边。坝材料124可以是粘合剂、聚合物、或金属层。取决于材料，通过丝网印刷、电解电镀、无电电镀、喷涂、或其它合适的沉积工艺形成坝材料124。 
在图3b中，利用面向下朝向载体120的有源表面130上的接触焊盘128将半导体管芯或部件126安装到界面层122上的指定区域123。有源表面130包括模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器(DSP)、ASIC、存储器、或其它信号处理电路。半导体管芯126也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。 
在图3c中，利用浆料印刷(paste printing)、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器(applicator)将密封剂或模塑料132沉积在坝材料124和半导体管芯126上。密封剂132可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂132不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。 
在图3d中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模(wet stripping)来除去临时载体120和可选界 面层122。底侧内建互连结构134形成在坝材料124、半导体管芯126、和密封剂132上。内建互连结构134包括绝缘或钝化层136，所述绝缘或钝化层136包括二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、或具有类似绝缘和结构特性的其它材料的一个或多个层。利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化来形成绝缘层136。 
底侧内建互连结构134进一步包括利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀、和无电电镀)形成在绝缘层136中的导电层138。导电层138可以是Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料的一个或多个层。导电层138的一部分被电连接到半导体管芯126的接触焊盘128。导电层138的其它部分可以根据半导体器件的设计和功能是电共有的(electrically common)或被电隔离。 
在图3e中，利用蒸发、电解电镀、无电电镀、球滴(ball drop)、或丝网印刷工艺将导电凸块材料沉积到内建互连结构134上并且电连接到导电层138。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层138。在一个实施例中，通过将所述凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块140。在一些应用中，凸块140二次回流以改善到导电层138的电接触。所述凸块也可以被压缩结合到导电层138。凸块140表示一种可以形成在导电层138上的互连结构。所述互连结构也可以使用结合线(bond wire)、柱形凸块(stud bump)、微凸块、或其它电互连。 
利用锯条或激光切割装置142将半导体管芯126单体化成单个半导体器件。图4示出安装到PCB 146的单体化后的FO-WLCSP 144。半导体管芯126被电连接到底侧内建互连结构134和凸块140。坝材料124具有与密封剂132相反的翘曲特性。例如，随着温度升高，密封剂132易于凹入并且坝材料124易于凸出。由于相反的翘曲特性，在密封之后坝材料124加固了半导体管芯126的周边。另外，坝材料124被选择为具有与密封剂132的CTE相对应的CTE，即坝材料132的CTE类似于或稍微小于密封剂132的CTE。在温度循环和极端温度测试期间，坝材料124的CTE补偿由安装到FO-WLCSP 144中的内建互连结构134的密封的半导体管芯126引起的应力。通过减小翘 曲和CTE引起的应力，FO-WLCSP 144具有减少的焊点故障(尤其是在半导体管芯周边的周围)。 
图5示出形成在密封剂132和半导体管芯126的顶部和各侧上的屏蔽层150。屏蔽层150可以是Cu、Al、铁氧体或羰基铁(carbonyliron)、不锈钢、镍银、低碳钢、硅铁钢、箔、环氧树脂、导电树脂、以及能够阻挡或吸收电磁干扰(EMI)、射频干扰(RFI)、和其它器件之间的干扰的其它金属和复合物。屏蔽层150也可以是非金属材料(例如碳黑)或铝片(aluminum flake)，以减小EMI和RFI的影响。屏蔽层150通过导电层138到凸块140而接地。 
图6示出形成在半导体管芯126的接触焊盘128和内建互连结构134中的导电层138之间的互连凸块152。半导体管芯126由坝材料134支撑，这减小了凸块152坍塌的可能性。 
图7示出具有被形成得直到密封剂132的顶表面的坝材料124的FO-WLCSP 154。坝材料124从FO-WLCSP 154被暴露。 
图8示出如图7中所述的被形成得直到密封剂132的顶表面并且从FO-WLCSP被暴露的坝材料124。在与有源表面130相对的半导体管芯126的后表面上沉积热界面材料(TIM)156。TIM 156可以是氧化铝、氧化锌、氮化硼、或粉状银。热沉158被安装在TIM 156、密封剂132、和坝材料124上。热沉158可以是Al、Cu、或具有高热导率的另外的材料，以为半导体管芯126提供热耗散。TIM 156帮助散布和耗散由半导体管芯126产生的热。 
图9示出具有围绕半导体管芯的周边形成的坝材料的FO-WLCSP的另一个实施例。在临时载体和可选界面层上沉积坝材料160，至少部分地或完全围绕被指定用于半导体管芯164的区域的周边。坝材料160可以是粘合剂、聚合物、或金属层。取决于材料，通过丝网印刷、电解电镀、无电电镀、喷涂、或其它合适的沉积工艺形成坝材料160。 
光致抗蚀剂的一个或多个层被沉积在载体和可选界面层上。通过刻蚀显影工艺曝光和除去光致抗蚀剂的一部分以形成通路。利用选择性电镀工艺在所述通路中沉积导电材料，例如Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、钨(W)、焊料、多晶硅、或其组合。光致抗蚀剂被剥离掉，留下单个导电柱162。在另一个实施例中，导电柱162可以被形成为柱形凸块或堆叠凸块。 
半导体管芯或部件164利用面向下朝向载体的有源表面168上的接触焊盘166被安装到载体和可选界面层。有源表面168包括模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形 成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面168内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯164也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。 
利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器将密封剂或模塑料170沉积在坝材料160和半导体管芯164上。密封剂170可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂170不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。 
通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去临时载体和可选界面层。底侧内建互连结构174形成在坝材料160、半导体管芯164、和密封剂170上。内建互连结构174包括绝缘或钝化层176，所述绝缘或钝化层176包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料的一个或多个层。利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化来形成绝缘层176。 
底侧内建互连结构174进一步包括利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀、和无电电镀)形成在绝缘层176中的导电层178。导电层178可以是Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料的一个或多个层。导电层178的一部分被电连接到半导体管芯164的接触焊盘166，导电层178的另一部分被电连接到导电柱162。导电层178的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。 
利用蒸发、电解电镀、无电电镀、球滴、或丝网印刷工艺将导电凸块材料沉积到内建互连结构174上并且电连接到导电层178。所述凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、及其组合，连同可选的焊剂溶液一起。例如，所述凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将所述凸块材料结合到导电层178。在一个实施例中，通过将所述凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块180。在一些应用中，凸块180二次回流以改善到导电层178的电接触。所述凸块也可以被压缩结合到导电层178。凸块180表示一种可以形成在导电层 138上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。 
顶侧内建互连结构184形成在与有源表面168相对的密封剂170的表面上。内建互连结构184包括绝缘或钝化层186，所述绝缘或钝化层186包括SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料的一个或多个层。利用PVD、CVD、印刷、旋涂、喷涂、烧结、或热氧化来形成绝缘层186。 
顶侧内建互连结构184进一步包括利用图案化和金属沉积工艺(例如PVD、CVD、溅射、电解电镀、和无电电镀)形成在绝缘层186中的导电层188。导电层188可以是Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料的一个或多个层。导电层188的一部分被电连接导电柱162。导电层188的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。 
半导体管芯或部件190利用面向下朝向内建互连结构的有源表面194上的接触焊盘192被安装到顶侧内建互连结构184。有源表面194包括模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面194内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯190也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。典型的RF系统需要在一个或多个半导体封装中的多个IPD以执行必要的电功能。在另一个实施例中，分立半导体器件可以被安装到顶侧内建互连结构184。凸块196将半导体管芯190的接触焊盘192电连接到导电层188。底层填料材料198，例如环氧树脂，被沉积在半导体管芯190之下。 
在FO-WLCSP 200中，半导体管芯164和190通过z向导电柱162被电连接到底侧内建互连结构174和凸块180以及顶侧内建互连结构184。坝材料160具有与密封剂170相反的翘曲特性。例如，随着温度升高，密封剂170易于凹入并且坝材料160易于凸出。由于相反的翘曲特性，在密封之后，坝材料160加固了半导体管芯164的周边。另外，坝材料160被选择为具有与密封剂170的CTE相对应的CTE，即坝材料160的CTE类似于或稍微小于密封剂170的CTE。在温度循环和极端温度测试期间，坝材料170的CTE补偿由安装到FO-WLCSP 200中的内建互连结构174的密封的半导体管芯126引起 的应力。通过减小翘曲和CTE引起的应力，FO-WLCSP 200具有减少的焊点故障(尤其是在半导体管芯周边的周围)。 
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。 

Claims (25)

1.一种制造半导体器件的方法，包括：
提供具有用于第一半导体管芯的指定区域的临时载体；
在用于第一半导体管芯的指定区域周围的临时载体上沉积坝材料；
安装第一半导体管芯，并且它的有源表面面向所述临时载体上的指定区域；
在第一半导体管芯和所述临时载体上沉积密封剂，所述坝材料被选择为具有与密封剂的热膨胀系数(CTE)相对应的热膨胀系数(CTE)；
除去所述临时载体以暴露密封剂的第一侧和第一半导体管芯的有源表面；以及
在密封剂的第一侧上形成第一互连结构。
2.如权利要求1所述的方法，其中坝材料的CTE等于或小于密封剂的CTE。
3.如权利要求1所述的方法，进一步包括在第一半导体管芯上形成屏蔽层。
4.如权利要求1所述的方法，进一步包括形成直到密封剂的顶表面的坝材料。
5.如权利要求1所述的方法，进一步包括在密封剂和第一半导体管芯上安装热沉。
6.如权利要求1所述的方法，进一步包括：
在与第一半导体管芯的有源表面相对的第一半导体管芯的后表面上形成第二互连结构；
在第一和第二互连结构之间形成导电柱；以及
将第二半导体管芯安装到第二互连结构。
7.如权利要求1所述的方法，进一步包括：
安装第一半导体管芯使得第一半导体的一部分由所述坝材料支撑；以及
在第一半导体管芯上的接触焊盘和第一互连结构之间形成凸块。
8.一种制造半导体器件的方法，包括：
提供具有用于第一半导体部件的指定区域的载体；
在用于第一半导体部件的指定区域周围的载体上沉积坝材料；
将第一半导体部件安装到所述载体上的指定区域；
在第一半导体部件和临时载体上沉积密封剂；
除去所述载体；以及
在密封剂上形成第一互连结构。
9.如权利要求8所述的方法，其中所述坝材料的热膨胀系数(CTE)等于或小于密封剂的CTE。
10.如权利要求8所述的方法，进一步包括在第一半导体部件上形成屏蔽层。
11.如权利要求8所述的方法，进一步包括形成直到密封剂的顶表面的坝材料。
12.如权利要求8所述的方法，进一步包括在密封剂和第一半导体部件上安装热沉。
13.如权利要求8所述的方法，进一步包括：
在第一半导体部件上形成第二互连结构；以及
将第二半导体部件安装到第二互连结构。
14.如权利要求8所述的方法，进一步包括：
安装第一半导体部件使得第一半导体的一部分由所述坝材料支撑；以及
在第一半导体部件上的接触焊盘和第一互连结构之间形成凸块。
15.一种制造半导体器件的方法，包括：
提供第一半导体部件；
围绕第一半导体部件的周边沉积坝材料；
在第一半导体部件上沉积密封剂，所述坝材料被选择为具有与密封剂的热膨胀系数(CTE)相对应的热膨胀系数(CTE)；以及
在密封剂上形成第一互连结构。
16.如权利要求15所述的方法，其中所述坝材料的CTE等于或小于密封剂的CTE。
17.如权利要求15所述的方法，进一步包括在第一半导体部件的周围形成屏蔽层。
18.如权利要求15所述的方法，进一步包括形成直到密封剂的顶表面的坝材料。
19.如权利要求15所述的方法，进一步包括在密封剂和第一半导体部件上安装热沉。
20.如权利要求15所述的方法，进一步包括：
在第一半导体部件上形成第二互连结构；以及
将第二半导体部件安装到第二互连结构。
21.一种半导体器件，包括：
第一半导体部件；
围绕第一半导体部件的周边沉积的坝材料；
沉积在第一半导体部件上的密封剂，所述坝材料被选择为具有与密封剂的热膨胀系数(CTE)相对应的热膨胀系数(CTE)；以及
形成在密封剂上的第一互连结构。
22.如权利要求21所述的半导体器件，其中所述坝材料的CTE等于或小于密封剂的CTE。
23.如权利要求21所述的半导体器件，进一步包括形成在第一半导体部件上的屏蔽层。
24.如权利要求21所述的半导体器件，进一步包括安装在密封剂和第一半导体部件上的热沉。
25.如权利要求21所述的半导体器件，进一步包括：
形成在第一半导体部件上的第二互连结构；以及
安装到第二互连结构的第二半导体部件。
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