CN102244013B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN102244013B
CN102244013B CN201110123641.2A CN201110123641A CN102244013B CN 102244013 B CN102244013 B CN 102244013B CN 201110123641 A CN201110123641 A CN 201110123641A CN 102244013 B CN102244013 B CN 102244013B
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semiconductor element
esd protection
protection layer
semiconductor
layer
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CN102244013A (zh
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R.A.帕盖拉
J.A.卡帕拉斯
P.C.马里穆图
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件及其制造方法。一种半导体晶片具有被划片街区分开的多个半导体管芯。所述晶片被安装到切割胶带。所述晶片通过划片街区被单体化以暴露半导体管芯的侧表面。在半导体管芯上以及在半导体管芯的暴露的侧表面周围形成ESD保护层。所述ESD保护层可以是金属层、密封剂膜、导电聚合物、导电墨水、或被金属层覆盖的绝缘层。在半导体管芯之间单体化ESD保护层。将被ESD保护层覆盖的半导体管芯安装到临时载体。在覆盖半导体管芯的ESD保护层上沉积密封剂。除去载体。在半导体管芯和密封剂上形成互连结构。ESD保护层被电连接到互连结构以提供ESD路径。

Description

半导体器件及其制造方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和在半导体管芯之间形成不连续ESD保护层的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（basecurrent）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占地面积的半导体器件封装。
许多半导体器件容易由于静电放电（ESD）而损坏。图1a示出具有多个半导体管芯10的常规设置，所述半导体管芯10具有有源表面12和安装到双面粘附层16的接触焊盘14，所述双面粘附层16被施加在临时载体18上。ESD保护层20形成在半导体管芯10上。ESD保护层20是形成在半导体管芯10以及半导体管芯之间的区域22上的物理和电连续层。密封剂24形成在半导体管芯10和载体18上。在图1b中，粘附层16和临时载体18被除去并且装配互连结构26形成在半导体管芯10的有源表面12和密封剂24上。在装配互连结构26的形成期间，ESD保护层20保留作为在半导体管芯10以及半导体管芯之间的区域22上的物理和电连续层。
当双面粘附层16和临时载体18被除去时，静电电荷可能累积。静电电荷必须被除去以避免缩短半导体管芯10的使用寿命。通常使用电离器来中和静电电荷。然而，电离器增加了制造过程的成本。ESD保护层20也除去静电电荷但是需要昂贵且费时的沉积工艺（例如化学气相沉积（CVD）和溅射）来形成物理和电连续层。
发明内容
存在对用于半导体管芯的节省成本的ESD保护方案的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有多个被划片街区分开的半导体管芯的半导体晶片，将半导体晶片安装到切割胶带，通过划片街区单体化半导体晶片以暴露半导体管芯的侧表面，在半导体管芯上以及在半导体管芯的暴露的侧表面周围形成ESD保护层，单体化ESD保护层以使ESD保护层在半导体管芯之间不连续，将被ESD保护层覆盖的半导体管芯安装到临时载体，在覆盖半导体管芯的ESD保护层上沉积密封剂，除去临时载体，以及在半导体管芯和密封剂上形成互连结构。ESD保护层被电连接到互连结构以提供ESD路径。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有多个被划片街区分开的第一半导体管芯的半导体晶片，通过划片街区单体化半导体晶片以暴露第一半导体管芯的侧表面，在第一半导体管芯上以及在第一半导体管芯的暴露的侧表面周围形成ESD保护层，在第一半导体管芯之间单体化ESD保护层，将被ESD保护层覆盖的第一半导体管芯安装到载体，在ESD保护层上沉积密封剂，除去载体，以及在第一半导体管芯和密封剂上形成互连结构。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有多个被划片街区分开的第一半导体管芯的半导体晶片，通过划片街区单体化半导体晶片以暴露第一半导体管芯的侧表面，在第一半导体管芯上以及在第一半导体管芯的暴露的侧表面周围形成ESD保护层，在第一半导体管芯之间单体化ESD保护层，以及在ESD保护层上沉积密封剂。
在另一个实施例中，本发明是一种半导体器件，该半导体器件包括多个半导体管芯和形成在半导体管芯上以及半导体管芯的侧表面周围的ESD保护层。ESD保护层在半导体管芯之间不连续。密封剂被沉积在ESD保护层上。互连结构形成在半导体管芯和密封剂上。ESD保护层电连接到互连结构。
附图说明
图1a-1b示出具有连续ESD保护层的常规半导体管芯；
图2示出具有安装到其表面的不同类型封装的PCB；
图3a-3c示出安装到PCB的典型半导体封装的更多细节；
图4a-4l示出在半导体管芯的侧表面和后表面上形成不连续ESD保护层的过程；
图5示出具有形成在其侧表面和后表面上的不连续ESD保护层的半导体管芯；
图6a-6j示出形成不连续ESD保护层作为密封剂膜的过程；
图7示出具有形成在其侧表面和后表面上作为密封剂膜的不连续ESD保护层的半导体管芯；
图8a-8i示出形成不连续ESD保护层作为绝缘层和导电层的过程；
图9示出具有形成在其侧表面和后表面上作为绝缘层和导电层的不连续ESD保护层的半导体管芯；
图10示出均被不连续ESD保护层覆盖的并排的半导体管芯；
图11示出并排的半导体管芯，一个管芯被不连续ESD保护层覆盖并且一个管芯没有ESD保护层；
图12示出层叠半导体管芯，一个管芯被不连续ESD保护层覆盖并且一个管芯没有ESD保护层；以及
图13示出层叠半导体管芯，每个管芯都被不连续ESD保护层覆盖。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electrolessplating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（sawstreet）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（studbump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图2示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图2中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图2中，PCB52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（landgridarray，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quadflatnon-leadedpackage，QFN）70、以及四侧扁平封装72被示出安装在PCB52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图3a-3c示出示范性半导体封装。图3a示出安装在PCB52上的DIP64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是一层或多层的导电材料，例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag），并且电连接到形成在半导体管芯74内的电路元件。在DIP64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图3b示出安装在PCB52上的BCC62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB52的表面上以防止氧化。接触焊盘102电连接到PCB52中的一个或多个导电信号迹线54。凸块104被形成在BCC62的接触焊盘98与PCB52的接触焊盘102之间。
在图3c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA60利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB52。
相对于图2和3a-3c，图4a-4l示出在半导体管芯的侧表面和后表面上形成不连续ESD保护层的过程。图4a示出具有用于结构支撑的基底衬底材料122（例如硅、锗、砷化镓、磷化铟、或碳化硅）的半导体晶片120。多个半导体管芯或部件124形成在晶片120上，被划片街区126分开，如上所述。
图4b示出半导体晶片120的一部分的截面图。每个半导体管芯124具有有源表面130，所述有源表面130包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面130上形成导电层132。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层132用作电连接到有源表面130上的电路的接触焊盘。
半导体晶片120被安装到切割胶带136，如图4c中所示。在图4d中，利用锯条或激光切割工具138，半导体晶片120通过划片街区126被向下单体化至切割胶带136以暴露半导体管芯124的侧表面142。
在图4e中，导电层140形成在半导体管芯124的暴露的侧表面142上，即在单体化的划片街区126中。导电层140也形成在与有源表面130相对的后表面144上。在一个实施例中，导电层140可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。利用电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成导电层140。以金属形式，导电层140在后表面144上具有0.1到2.0微米（μm）的厚度。可替换地，导电层140可以是具有小于100μm（优选20-50μm）厚度的导电聚合物或导电墨水，即具有导电粒子的聚合物或墨水基底材料。例如，导电聚合物可以是聚乙炔、聚苯基乙烯（polyphenylenevinylene）、聚吡咯、聚噻吩、聚苯胺、聚亚苯基、或其它有机聚合物。通过印刷、溅射、或汽相沉积在形成在半导体管芯124上的金属网或其它中间导电层上形成导电聚合物或导电墨水。取决于材料，导电层140也可以通过模版印刷、丝网印刷、旋涂、或针滴（needledispensing）形成。导电层140用作用于半导体管芯124的ESD保护层。
在图4f中，利用锯条或激光切割工具148在半导体管芯124之间将ESD保护层140向下单体化至切割胶带136。锯条或激光切割工具148通常比锯条或激光切割工具138窄，使得ESD保护层140保持覆盖侧表面142。在单体化之后，ESD保护层140在半导体管芯124之间不连续同时仍然覆盖半导体管芯124的侧表面142和后表面144。
在图4g中，临时衬底或载体150包括用于结构支撑的牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或其它合适的低成本、刚性材料。界面层或胶带152被施加在载体150上作为可由热或紫外（UV）光释放的双面粘附层。
采用拾取和放置操作，被ESD保护层140覆盖的半导体124a从切割胶带136被除去并且被安装到载体150上的界面层152。类似地，被ESD保护层140覆盖的半导体124b从切割胶带136被除去并且被安装到界面层152，如图4h中所示。形成在半导体管芯124a上的ESD保护层140不连续，即与形成在半导体管芯124b上的ESD保护层140物理分离和电隔离。安装到载体150的均具有分离和不连续ESD保护层140的半导体管芯124a和124b被称作“重新配置的晶片”。
在图4i中，密封剂或模塑料154被沉积在半导体管芯124a和124b以及载体150上，所述密封剂或模塑料154的用量为覆盖形成在半导体管芯124a和124b的侧表面142和后表面144上的ESD保护层140。利用浆料印刷（pasteprinting）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器（applicator）沉积密封剂154。密封剂154可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂154不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图4j中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体150和界面层152。
在图4k中，底侧装配互连结构158形成在半导体管芯124a和124b的有源表面130和密封剂154上。装配互连结构158包括利用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）形成的导电层160。导电层160可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层160的一部分被电连接到半导体管芯124a和124b的接触焊盘132。导电层160的另一部分被电连接到ESD保护层140作为低阻抗接地点。导电层160的其它部分可以根据半导体器件的设计和功能是电共有的（electricallycommon）或被电隔离。
装配互连结构158进一步包括绝缘或钝化层162，所述绝缘或钝化层162形成在导电层160之间并且包括一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、或具有类似绝缘和结构特性的其它材料。绝缘层162利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。
在图4l中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在装配互连结构158上沉积导电凸块材料并将导电凸块材料电连接到导电层160。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层160。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块164。在一些应用中，凸块164被二次回流以改善到导电层160的电接触。所述凸块也可以被压缩结合到导电层160。凸块164表示一种可以形成在导电层160上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具166将半导体管芯124a和124b单体化成单个半导体器件。
图5示出单体化之后的半导体器件168。半导体管芯124电连接到装配互连结构158和凸块164。形成在半导体管芯124的有源表面130内的有源和无源电路容易由于ESD事件而损坏。静电电荷可能例如在除去载体150和界面层152期间累积。静电电荷必须被除去以避免缩短半导体管芯124的使用寿命。导电层140通过中和静电电荷为半导体管芯124提供ESD保护。导电层140提供通过导电层160和凸块164到外部低阻抗接地点的ESD放电路径170以安全地放出静电电荷并且保护半导体管芯124。静电电荷向着ESD放电路径170迁移，所述放电路径170的电阻比通向接触焊盘132和有源表面130的路径的电阻低。通过在每个半导体管芯124的侧表面142和后表面144上沉积不连续的ESD保护层140，可以使用节省成本的沉积工艺，例如模版印刷、丝网印刷、旋涂、和针滴。
在另一个实施例中，从图4d继续，导电密封剂膜174被施加到胶带载体176并且位于半导体管芯124上，如图6a中所示。密封剂膜174可以是包括填充物（例如铝、铜、炭黑、金、或铂）的b阶段（b-staged）可固化可流动膜密封剂。例如，所述b阶段膜可以是包含导电粒子并且具有小于100μm（优选20-50μm）的厚度的环氧树脂。导电密封剂膜174用作用于半导体管芯124的ESD保护层。
在图6b中，ESD保护层174被层压在半导体管芯124上。在图6c中，ESD保护层174被固化并且胶带载体176被除去。在图6d中，利用锯条或激光切割工具178，ESD保护层174在半导体管芯124之间被向下单体化至切割胶带136。在单体化之后，ESD保护层174在半导体管芯124之间不连续同时仍然覆盖半导体管芯124的侧表面142和后表面144。
在图6e中，临时衬底或载体180包括用于结构支撑的牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或其它合适的低成本、刚性材料。界面层或胶带182被施加在载体180上作为可由热或UV光释放的双面粘附层。
采用拾取和放置操作，被ESD保护层174覆盖的半导体124a从切割胶带136被除去并且被安装到载体180上的界面层182。类似地，被ESD保护层174覆盖的半导体124b从切割胶带136被除去并且被安装到界面层182，如图6f中所示。形成在半导体管芯124a上的ESD保护层174不连续，即与形成在半导体管芯124b上的ESD保护层140物理分离和电隔离。安装到载体150的均具有不连续ESD保护层174的半导体管芯124a和124b被称作“重新配置的晶片”。
在图6g中，密封剂或模塑料184被沉积在半导体管芯124a和124b以及载体180上，所述密封剂或模塑料184的用量为覆盖形成在半导体管芯124a和124b的侧表面142和后表面144上的ESD保护层174。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器沉积密封剂184。密封剂184可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂184不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图6h中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体180和界面层182。
在图6i中，底侧装配互连结构188形成在半导体管芯124a和124b的有源表面130和密封剂184上。装配互连结构188包括利用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）形成的导电层190。导电层190可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层190的一部分被电连接到半导体管芯124a和124b的接触焊盘132。导电层190的另一部分被电连接到ESD保护层174作为低阻抗接地点。导电层190的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构188进一步包括绝缘或钝化层192，所述绝缘或钝化层192形成在导电层190之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层192利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。
在图6j中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在装配互连结构188上沉积导电凸块材料并将导电凸块材料电连接到导电层190。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层190。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块194。在一些应用中，凸块194被二次回流以改善到导电层190的电接触。所述凸块也可以被压缩结合到导电层190。凸块194表示一种可以形成在导电层190上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具196将半导体管芯124a和124b单体化成单个半导体器件。
图7示出单体化之后的半导体器件198。半导体管芯124电连接到装配互连结构188和凸块194。形成在半导体管芯124的有源表面130内的有源和无源电路容易由于ESD事件而损坏。静电电荷可能例如在除去载体180和界面层182期间累积。静电电荷必须被除去以避免缩短半导体管芯124的使用寿命。密封剂膜174通过中和静电电荷为半导体管芯124提供ESD保护。密封剂膜174提供通过导电层190和凸块194到外部低阻抗接地点的ESD放电路径200以安全地放出静电电荷并且保护半导体管芯124。静电电荷向着ESD放电路径200迁移，所述放电路径200的电阻比通向接触焊盘132和有源表面130的路径的电阻低。通过在每个半导体管芯124的侧表面142和后表面144上沉积不连续的ESD保护层174，可以使用节省成本的沉积工艺，例如模版印刷、丝网印刷、旋涂、和针滴。
在另一个实施例中，从图4d继续，绝缘或介电层210共形地形成在半导体管芯124的侧表面142和后表面144上，如图8a中所示。绝缘层210包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层210利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。
在图8b中，导电层212形成在绝缘层210上，即在单体化的划片街区126中的侧表面142和后表面144上。在一个实施例中，导电层212可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。利用电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成导电层212。以金属形式，导电层212在后表面144上具有0.1到2.0μm的厚度。可替换地，导电层212可以是具有小于100μm（优选20-50μm）厚度的导电聚合物或导电墨水，即具有导电粒子的聚合物或墨水基底材料。例如，导电聚合物可以是聚乙炔、聚苯基乙烯、聚吡咯、聚噻吩、聚苯胺、聚亚苯基、或其它有机聚合物。通过印刷、溅射、或汽相沉积在形成在半导体管芯124上的金属网或其它中间导电层上形成导电聚合物或导电墨水。取决于材料，导电层212也可以通过模版印刷、丝网印刷、旋涂、或针滴形成。绝缘层210和导电层212用作用于半导体管芯124的ESD保护层。
在图8c中，利用锯条或激光切割工具214在半导体管芯124之间将ESD保护层210－212向下单体化至切割胶带136。锯条或激光切割工具214通常比锯条或激光切割工具138窄，使得ESD保护层210－212保持覆盖侧表面142。在单体化之后，ESD保护层210－212在半导体管芯124之间不连续同时仍然覆盖半导体管芯124的侧表面142和后表面144。
在图8d中，临时衬底或载体220包括用于结构支撑的牺牲基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、或其它合适的低成本、刚性材料。界面层或胶带222被施加在载体220上作为可由热或UV光释放的双面粘附层。
采用拾取和放置操作，具有ESD保护层210－212的半导体124a从切割胶带136被除去并且被安装到载体220上的界面层222。类似地，具有ESD保护层210－212的半导体124b从切割胶带136被除去并且被安装到界面层222，如图8e中所示。形成在半导体管芯124a上的ESD保护层210－212不连续，即与形成在半导体管芯124b上的ESD保护层210－212物理分离和电隔离。安装到载体220的均具有不连续ESD保护层210－212的半导体管芯124a和124b被称作“重新配置的晶片”。
在图8f中，密封剂或模塑料226被沉积在半导体管芯124a和124b以及载体220上，所述密封剂或模塑料220的用量为覆盖形成在半导体管芯124a和124b的侧表面142和后表面144上的ESD保护层210－212。利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器沉积密封剂226。密封剂226可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂226不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图8g中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体220和界面层222。
在图8h中，底侧装配互连结构228形成在半导体管芯124a和124b的有源表面130和密封剂226上。装配互连结构228包括利用图案化和金属沉积工艺（例如PVD、CVD、溅射、电解电镀、和无电极电镀）形成的导电层230。导电层230可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层230的一部分被电连接到半导体管芯124a和124b的接触焊盘132。导电层230的另一部分被电连接到导电层212作为低阻抗接地点。导电层230的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构228进一步包括绝缘或钝化层232，所述绝缘或钝化层232形成在导电层230之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层232利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。
在图8i中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺，导电凸块材料被沉积在装配互连结构228上并且被电连接到导电层230。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层230。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料被回流以形成球形球或凸块234。在一些应用中，凸块234被二次回流以改善到导电层230的电接触。所述凸块也可以被压缩结合到导电层230。凸块234表示一种可以形成在导电层230上的互连结构。所述互连结构也可以使用结合线、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具236将半导体管芯124a和124b单体化成单个半导体器件。
图9示出单体化之后的半导体器件238。半导体管芯124电连接到装配互连结构228和凸块234。形成在半导体管芯124的有源表面130内的有源和无源电路容易由于ESD事件而损坏。静电电荷可能例如在除去载体220和界面层222期间累积。静电电荷必须被除去以避免缩短半导体管芯124的使用寿命。绝缘层210和导电层212通过中和静电电荷为半导体管芯124提供ESD保护。导电层212提供通过导电层230和凸块234到外部低阻抗接地点的ESD放电路径200以安全地放出静电电荷并且保护半导体管芯124。静电电荷向着ESD放电路径240迁移，所述放电路径240的电阻比通向接触焊盘132和有源表面130的路径的电阻低。通过在每个半导体管芯124的侧表面142和后表面144上沉积不连续的ESD保护层210－212，可以使用节省成本的沉积工艺，例如模版印刷、丝网印刷、旋涂、和针滴。另外，绝缘层210和导电层212充当屏蔽层以抑制电磁干扰（EMI）和射频干扰（RFI）。绝缘层210也防止导电层212和半导体管芯124之间的电短路。
图10示出被安装到互连结构158的、均具有ESD保护层140的两个并排半导体管芯124。
图11示出被安装到互连结构158的两个并排的半导体管芯124，一个管芯具有ESD保护层140并且一个管芯没有ESD保护层140。
图12示出一个实施例，从图4h继续，被ESD保护层140覆盖的半导体管芯124被安装到临时载体。半导体管芯250具有有源表面252，所述有源表面252包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面252内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯252也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘254形成在有源表面252上。半导体管芯250的后表面256利用粘附层258被安装到半导体管芯124的后表面144上的ESD保护层140。
利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器，密封剂或模塑料260被沉积在半导体管芯124和250以及载体上。密封剂260可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂260不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
利用激光钻孔、机械钻孔、或深反应离子刻蚀（DRIE）形成通过密封剂260的多个通孔。利用电解电镀、无电极电镀、或其它合适的金属沉积工艺利用Al、Cu、Sn、Ni、Au、Ag、Ti、钨（W）、多晶硅、或其它合适的导电材料来填充所述通孔以形成导电通孔262。
通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来除去临时载体。
底侧装配互连结构264形成在半导体管芯124的有源表面130和密封剂260上。装配互连结构264包括利用图案化和金属沉积工艺（例如PVD、CVD、溅射、电解电镀、和无电极电镀）形成的导电层266。导电层266可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层266的一部分被电连接到半导体管芯124接触焊盘132。导电层266的另一部分被电连接到ESD保护层140作为低阻抗接地点。导电层266的另一部分被电连接到导电通孔262。导电层266的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构264进一步包括绝缘或钝化层268，所述绝缘或钝化层268形成在导电层266之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层268利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。在导电层266上形成多个凸块270。
顶侧装配互连结构272形成在半导体管芯250的有源表面252和密封剂260上。装配互连结构272包括利用图案化和金属沉积工艺（例如PVD、CVD、溅射、电解电镀、和无电极电镀）形成的导电层274。导电层274可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层274的一部分被电连接到半导体管芯250的接触焊盘254。导电层274的另一部分被电连接到导电通孔262。导电层274的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构272进一步包括绝缘或钝化层276，所述绝缘或钝化层276形成在导电层274之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层276利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。
图13示出一个实施例，从图5继续，利用激光钻孔、机械钻孔、或DRIE形成通过密封剂154的多个通孔。利用电解电镀、无电极电镀、或其它合适的金属沉积工艺利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料来填充所述通孔以形成导电通孔280。
顶侧装配互连结构282形成在密封剂154上。装配互连结构282包括利用图案化和金属沉积工艺（例如PVD、CVD、溅射、电解电镀、和无电极电镀）形成的导电层284。导电层284可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层284的一部分被电连接到导电通孔280。导电层274的其它部分可以根据半导体器件的设计和功能是电共有的或被电隔离。
装配互连结构282进一步包括绝缘或钝化层286，所述绝缘或钝化层286形成在导电层284之间并且包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层286利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化形成。
半导体器件288包括被ESD保护层140覆盖并且电连接到装配互连结构158和282以及凸块164的半导体管芯124。导电层140为半导体管芯124提供ESD保护。两个半导体器件288被层叠并且通过互连结构158和282以及凸块164电连接。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (12)

1.一种制造半导体器件的方法，包括：
提供包括被划片街区分开的多个第一半导体管芯的半导体晶片；
通过划片街区单体化半导体晶片以暴露第一半导体管芯的侧表面；
在第一半导体管芯上以及在第一半导体管芯的侧表面周围形成静电放电ESD保护层，
其中ESD保护层跨第一半导体管芯之间的整个区域在第一半导体管芯上延伸；
将ESD保护层单体化以使ESD保护层在第一半导体管芯之间不连续；
将被ESD保护层覆盖的半导体管芯安装到临时载体；
在将ESD保护层单体化之后，在第一半导体管芯上沉积密封剂以包围不连续的ESD保护层；
除去临时载体；
在第一半导体管芯和密封剂上形成互连结构；
提供缺乏ESD保护层的第二半导体管芯；以及
将第二半导体管芯安装得邻近被不连续的ESD保护层覆盖的第一半导体管芯或安装在被不连续的ESD保护层覆盖的第一半导体管芯上方。
2.根据权利要求1的方法，其中不连续的ESD保护层被电连接到互连结构。
3.根据权利要求1的方法，其中形成ESD保护层包括在半导体管芯上以及在半导体管芯的侧表面周围形成金属层。
4.根据权利要求1的方法，其中形成ESD保护层包括：
在第一半导体管芯上以及在第一半导体管芯的侧表面周围形成绝缘层；以及
在绝缘层上形成金属层。
5.一种制造半导体器件的方法，包括：
提供包括被划片街区分开的多个第一半导体管芯的半导体晶片；
通过划片街区单体化半导体晶片以暴露第一半导体管芯的侧表面；
在第一半导体管芯的第一表面上以及在第一半导体管芯的侧表面周围形成静电放电ESD保护层；
在第一半导体管芯之间单体化ESD保护层，ESD保护层在与第一半导体管芯的第一表面相对的第一半导体管芯的第二表面处终止；
将被ESD保护层覆盖的半导体管芯安装到临时载体；
在将ESD保护层单体化之后在ESD保护层上沉积密封剂；
除去临时载体；
层叠被ESD保护层覆盖的多个第一半导体管芯；以及
电连接层叠的半导体管芯。
6.根据权利要求5的方法，进一步包括在第一半导体管芯和密封剂上形成互连结构。
7.根据权利要求5的方法，其中形成ESD保护层包括在半导体管芯上以及在半导体管芯的侧表面周围形成金属层。
8.根据权利要求5的方法，其中形成ESD保护层包括：
在第一半导体管芯上以及在第一半导体管芯的侧表面周围形成绝缘层；以及
在绝缘层上形成金属层。
9.根据权利要求5的方法，其中形成ESD保护层包括在半导体管芯上以及在半导体管芯的侧表面周围形成密封剂膜、导电聚合物、或导电墨水。
10.一种半导体器件，包括：
多个第一半导体管芯；
设置在半导体管芯的第一表面上和半导体管芯的各侧表面之间的静电放电ESD保护层，其中ESD保护层跨半导体管芯之间的整个区域在第一半导体管芯上延伸，并且ESD保护层在第一半导体管芯之间不连续；
沉积在覆盖第一半导体管芯的ESD保护层上的密封剂；
在第一半导体管芯和密封剂上形成的互连结构；以及
缺乏ESD保护层的多个第二半导体管芯，其中第二半导体管芯安装得邻近被不连续的ESD保护层覆盖的第一半导体管芯或安装在被不连续的ESD保护层覆盖的第一半导体管芯上方。
11.根据权利要求10的半导体器件，其中ESD保护层包括在半导体管芯的第一表面上和半导体管芯的各侧表面之间形成的金属层。
12.根据权利要求10的半导体器件，其中ESD保护层包括：
形成在半导体管芯的第一表面上和半导体管芯的侧表面周围的绝缘层；和
形成在绝缘层上的导电层。
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