CN102163561B - 半导体器件和使用相同载体在wlcsp中形成tmv和tsv的方法 - Google Patents

半导体器件和使用相同载体在wlcsp中形成tmv和tsv的方法 Download PDF

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CN102163561B
CN102163561B CN201110043183.1A CN201110043183A CN102163561B CN 102163561 B CN102163561 B CN 102163561B CN 201110043183 A CN201110043183 A CN 201110043183A CN 102163561 B CN102163561 B CN 102163561B
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conductive path
semiconductor element
sealing agent
insulation layer
interconnection structure
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CN102163561A (zh
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R·A·帕盖拉
林耀剑
尹胜煜
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件和使用相同载体在WLCSP中形成TMV和TSV的方法。一种半导体器件具有安装在载体上的半导体管芯。密封剂沉积在半导体管芯和载体上。绝缘层形成在半导体管芯和密封剂上。在半导体管芯安装到载体时多个第一通路被形成为通过绝缘层和半导体管芯。在半导体管芯安装到载体时多个第二通路被形成为在与第一通路相同的方向上通过绝缘层和密封剂。在第一通路中沉积导电材料以形成导电TSV并且在第二通路中沉积导电材料以形成导电TMV。第一互连结构形成在绝缘层上并电连接到TSV和TMV。除去载体。第二互连结构形成在半导体管芯和密封剂上并电连接到TSV和TMV。

Description

半导体器件和使用相同载体在WLCSP中形成TMV和TSV的方法
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件和在同一制造过程期间使用相同载体在相同方向上在WLCSP中形成TMV和TSV的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（basecurrent）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占地面积（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占地面积的半导体器件封装。
例如当堆叠器件以便有效集成时，半导体器件通常需要垂直互连结构。多级半导体器件（例如包含半导体管芯的扇出型晶片级芯片规模封装（FO-WLCSP））和外部器件之间的电互连可以利用导电直通硅通路（TSV）、导电直通孔通路（THV）、导电直通铸模通路（throughmoldvias，TMV）、镀铜导电柱和导电凸块来实现。这些垂直互连结构在制造过程期间耗费成本且耗时，并且在形成期间容易受到缺陷影响。
特别地，在WLCSP中，在单体化之前同时仍是晶片形式，使用用于支撑的第一载体首先形成导电TSV。在密封之后使用用于支撑的不同载体在该过程中稍后形成导电TMV。装配互连结构（build-upinterconnectstructure）一般形成在半导体管芯上。需要另外的加工步骤在装配层中形成通路以便对TSV重新布线（reroute）以互连到上部半导体器件。在半导体管芯中形成TSV之后，必须在TSV上在钝化层中形成导电通路以将TSV电连接到上部导电层。由于TSV和TMV通过单独的工艺形成在不同载体上，因此制造过程需要更多的时间、材料和步骤，这增加了成本和在半导体器件或整个晶片中引入缺陷的较大风险。例如，由于TSV是在晶片形式时形成的，因此半导体晶片受到损坏。
发明内容
存在对在WLCSP中形成TSV和TMV的简单且节省成本的工艺的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供临时载体，在临时载体上安装半导体管芯，在半导体管芯和临时载体上沉积密封剂，在半导体管芯和密封剂上形成第一绝缘层，在半导体管芯安装到临时载体上时形成通过第一绝缘层和半导体管芯的多个第一通路，在半导体管芯安装到临时载体上时形成通过第一绝缘层和密封剂的多个第二通路，在第一通路中沉积导电材料以形成导电TSV，在第二通路中沉积导电材料以形成导电TMV，在第一绝缘层上形成第一互连结构并且电连接到导电TSV和导电TMV，除去临时载体，以及在半导体管芯和密封剂上与第一互连结构相对地形成第二互连结构并且电连接到导电TSV和导电TMV。
在另一实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供载体，在载体上安装半导体管芯，在半导体管芯和载体上沉积密封剂，在半导体管芯安装到载体上时形成通过半导体管芯的多个第一通路，在与第一通路相同的方向上形成通过密封剂的多个第二通路，在第一通路中沉积导电材料以形成第一导电通路并且在第二通路中沉积导电材料以形成第二导电通路，在密封剂上形成第一互连结构并且电连接到第一导电通路和第二导电通路，除去载体，以及在密封剂上与第一互连结构相对地形成第二互连结构并且电连接到第一导电通路和第二导电通路。
在另一实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供载体，在载体上安装半导体管芯且半导体管芯的有源表面面向载体，在半导体管芯和载体上沉积密封剂，除去载体，在密封剂和半导体管芯的有源表面上形成第一互连结构，形成通过半导体管芯和第一互连结构的一部分的多个第一通路，在与第一通路相同的方向上形成通过密封剂和第一互连结构的一部分的多个第二通路，在第一通路中沉积导电材料以形成第一导电通路并且在第二通路中沉积导电材料以形成第二导电通路，以及在密封剂上与第一互连结构相对地形成第二互连结构并且电连接到第一导电通路和第二导电通路。
在另一实施例中，本发明是一种半导体器件，该半导体器件包括：半导体管芯和沉积在该半导体管芯上的密封剂。第一导电通路被形成为通过半导体管芯。第二导电通路被形成为在与第一导电通路相同的方向上通过密封剂。第一互连结构形成在密封剂上并且电连接到第一导电通路和第二导电通路。第二互连结构与第一互连结构相对地形成在密封剂上并且电连接到第一导电通路和第二导电通路。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的半导体封装的更多细节；
图3a-3j示出在同一制造过程期间使用相同载体在相同方向上在WLCSP中形成TMV和TSV的过程；
图4示出具有TMV和TSV的可堆叠的WLCSP；
图5示出电连接到管芯的有源表面的TSV；
图6示出覆盖半导体管芯的后表面的密封剂；
图7示出共形地形成在通路中然后被填充光致抗蚀剂材料的TMV和TSV；
图8示出安装到载体上的接触焊盘的凸起的半导体管芯；
图9示出安装到载体上的接触焊盘的凸起的半导体管芯和电连接到管芯的有源表面的TSV；
图10示出利用底层填充材料安装到载体上的接触焊盘的凸起的半导体管芯；
图11示出使用较低装配互连结构作为支撑来在同一制造过程期间在相同方向上形成TMV和TSV；以及
图12示出通过TMV、TSV和互连结构互连的堆叠WLCSP。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electrolessplating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（sawstreet）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（studbump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。
在图1中，PCB52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括线结合封装56和倒装芯片58，被示出在PCB52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（landgridarray，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quadflatnon-leadedpackage，QFN）70、以及四侧扁平封装72被示出安装在PCB52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB52上的DIP64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料（例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag））的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和线结合82在半导体管芯74和PCB52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或线结合82来进行环境保护。
图2b示出安装在PCB52上的BCC62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。线结合94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和线结合94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB52的表面上以防止氧化。接触焊盘102电连接到PCB52中的一个或多个导电信号迹线54。凸块104被形成在BCC62的接触焊盘98与PCB52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA60利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB52。
图3a-3j示出在同一制造过程期间使用相同载体在相同方向上在WLCSP中形成TMV和TSV的过程。在图3a中，牺牲或临时衬底或载体120包含基底材料，例如硅、聚合物、聚合物复合材料、金属、陶瓷、玻璃、玻璃纤维环氧树脂、氧化铍、带（tape）、或用于结构支撑的其它合适的低成本、刚性材料。可以在载体120上形成可选界面层122作为临时双面粘合带或结合膜或腐蚀停层。
在图3b中，半导体管芯或部件124安装到载体120且载体上的接触焊盘126面向下。半导体管芯124具有有源区128，其包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面128内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。半导体管芯124可以是倒装芯片类型的器件或线结合类型的器件。在另一实施例中，分立部件可以安装在界面层122和载体120上。
图3c示出利用浆料印刷（pasteprinting）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、或其它合适的施加器（applicator）沉积在半导体管芯124和载体120上的密封剂或模塑料130。密封剂130可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂130不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。密封剂130被平面化以暴露半导体管芯124的与有源表面128相对的后表面132。
在图3d中，利用PVD、CVD、印刷、旋涂、喷涂或热氧化工艺将绝缘或钝化层134形成在半导体管芯124的后表面132和密封剂130上。绝缘层134可以是一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、或具有类似绝缘和结构特性的其它材料。
在图3e中，在将半导体管芯124安装到载体120时，利用激光钻孔、机械钻孔或深反应离子刻蚀（DRIE）工艺来形成通过绝缘层134和半导体管芯124的多个通路136。在沉积密封剂130之后，从绝缘层134和背面132形成通路136，且半导体管芯124的有源表面128面向下。通路136延伸通过半导体管芯124的硅区至接触焊盘126。类似地，在图3f中，在将半导体管芯124安装到载体120时，利用激光钻孔、机械钻孔或DRIE来形成通过绝缘层134和密封剂130的多个通路138。通路138从与通路136相同的侧面形成并延伸到界面层122。通路136和138在同一制造过程期间使用相同的载体120同时形成或者从相同侧面连续形成。
可以使用PVD、CVD或热氧化工艺在通路136和138的侧壁上形成可选绝缘或介电层140。绝缘层140可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、苯并环丁烯（benzocyclobutene，BCB）、聚苯并恶唑（polybenzoxazole，PBO）或其它适当的介电材料。在没有可选绝缘层140的情况下继续其余的描述。
在图3g中，利用电解电镀、无电极电镀工艺或其它适当的金属沉积工艺，使用Al、Cu、Sn、Ni、Au、Ag、钛（Ti）、W、多晶硅或其它适当的导电材料来填充通路138以形成导电直通铸模通路（TMV）142。利用电解电镀、无电极电镀工艺或其它适当的金属沉积工艺，使用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其它适当的导电材料来填充通路136以形成导电直通硅通路（TSV）144。TSV144电连接到接触焊盘126。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层134、TMV142和TSV144上形成导电层146。导电层146可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层146的各个部分电连接到TMV142和TSV144并且用作再分配层（RDL）以扩展TMV和TSV的电连接性。
在图3h中，在绝缘层134和导电层146上沉积并图案化光致抗蚀剂层148。除去光致抗蚀剂层148的一部分以暴露导电层146。使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在导电层146上形成可选导电层147。导电层147可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层147形成包括阻挡层和粘附层的多层凸块下金属化（UBM）。在一个实施例中，阻挡层包含Ni、钛钨（TiW）、铬铜（CrCu）、镍钒（NiV）、铂（Pt）、或钯（Pd）。粘附层包含Al、钛(Ti)、铬(Cr)、或氮化钛(TiN)。UBM147提供低电阻互连，以及对Cu或焊料扩散的阻挡。可替换地，还可以在导电层146上形成可线结合的焊盘。导电层146、光致抗蚀剂层148和UBM147构成装配互连结构149。
在图3i中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去载体120和界面层122。在有源表面128和密封剂130上形成装配互连结构150。装配互连结构150包括通过PVD、CVD、印刷、旋涂、喷涂或热氧化形成的绝缘或钝化层152。绝缘层152可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。通过刻蚀工艺除去绝缘层152的一部分以暴露TMV142和TSV144。使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层152的被除去的部分中形成导电层154。导电层154可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层154的各个部分电连接到TMV142和TSV144。
在图3j中，装配互连结构150进一步包括使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺形成在绝缘层152和导电层154上的导电层156。导电层156可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层156的各个部分电连接到TMV142和TSV144并且用作RDL以扩展TMV和TSV的电连接性。
通过PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层152和导电层156上形成绝缘或钝化层158。绝缘层158可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。通过刻蚀工艺除去绝缘层158的一部分以暴露导电层156。
使用蒸发、电解电镀、无电极电镀、球滴（balldrop）或丝网印刷工艺在导电层156上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层156。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块160。在一些应用中，凸块160二次回流以改善到导电层156的电接触。所述凸块也可以被压缩结合到导电层156。凸块160表示一种可以形成在导电层156上的互连结构。所述互连结构也可以使用结合线、导电胶、柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割装置162将半导体管芯124单体化成单个可堆叠的WLCSP164。图4示出单体化之后的WLCSP164。装配互连结构149通过导电TMV142和TSV144电连接到半导体管芯124的接触焊盘126和装配互连结构150的导电层154和156。在沉积密封剂130之后，TMV142和TSV144在同一制造过程期间从相同侧面形成。由于TSV144在密封之后形成，因此相同的载体120用于形成TMV142和TSV144两者。背景技术中提到的单独的制造工艺和不同的载体不再是必要的。此外，可以避免现有技术中要求的在TSV上的钝化层中形成通路。用于形成TSV144的通路136延伸通过钝化层134，由此节省了现有技术中需要的工艺步骤。TMV142和TSV144的连续结构降低了接触电阻，提高了导电性，并改善了信号完整性。因此，在同一制造过程期间使用相同的载体120从相同侧面形成TMV142和TSV144简化了制造，降低了成本，并减小了缺陷的风险。在将半导体管芯124安装到载体120之后以及在沉积密封剂130之后形成TSV144降低了由于在晶片级TSV形成缺陷引起的器件失效。
图5示出类似于图4的实施例，其中TSV144电连接到有源表面128内的电路节点以提供附加垂直（z方向）互连来增加上部堆叠半导体器件的输入/输出（I/O）数和密度。TSV144还电连接到导电层154和导电层156的多个部分。导电层156和导电层154的其它部分电连接到接触焊盘126。
图6示出类似于图4的实施例，其中密封剂130覆盖半导体管芯124的后表面132。图3d中描述的绝缘层134可以被省略，因为密封剂130提供了电隔离和结构隔离。
图7示出从图3f继续的实施例，其中使用图案化和电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺将导电层166共形地形成在通路136和138的侧壁上，而没有完全填充通路。导电层166可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层134上形成导电层168。导电层168可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层168电连接到形成在通路136和138中的导电层166并且用作RDL以扩展TMV和TSV的电连接性。
在绝缘层134和导电层168上沉积并图案化光致抗蚀剂或绝缘层170。光致抗蚀剂170填充导电层166上的通路136和138的剩余区域。光致抗蚀剂层170的一部分被除去以暴露导电层168。在导电层168上形成可选的UBM171。导电层168、光致抗蚀剂层170和UBM171构成装配互连结构173。该过程的其余部分遵循图3g-3j。
图8示出类似于图4的实施例，其中在将半导体管芯124安装到载体120之前，凸块172形成在接触焊盘126上，并且接触焊盘174形成在载体120上。具有凸块172的半导体管芯124安装到接触焊盘174。接触焊盘174电连接到导电层154。凸块172提供更精细的互连间距并增加I/O密度。密封剂130底层填充半导体管芯124。
图9示出类似于图8的实施例，其中TSV144电连接到有源表面128内的电路节点以提供附加垂直（z方向）互连来增加上部堆叠半导体器件的输入/输出（I/O）数和密度。TSV144延伸通过密封剂130以电连接到导电层154和导电层156的多个部分。导电层156和导电层154的其它部分电连接到凸块172以及接触焊盘126和174。
图10示出类似于图9的实施例，其中诸如环氧树脂的底层填充材料176沉积在半导体管芯124之下。TSV144电连接到有源表面128内的电路节点以提供附加垂直（z方向）互连来增加上部堆叠半导体器件的输入/输出（I/O）数和密度。TSV144延伸通过底层填充材料176以电连接到导电层154和导电层156的多个部分。导电层156和导电层154的其它部分电连接到接触焊盘126。
图11示出从图3c继续的实施例，其中通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去载体120和界面层122。在有源表面128和密封剂130上形成装配互连结构180。装配互连结构180包括通过PVD、CVD、印刷、旋涂、喷涂或热氧化形成的绝缘或钝化层182。绝缘层182可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。通过刻蚀工艺除去绝缘层182的一部分以暴露接触焊盘126。使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层182的被除去的部分中形成导电层184。导电层184可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层184电连接到接触焊盘126。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层182上形成导电层186。导电层186可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层186的各个部分用作RDL以扩展电连接性。
通过PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层182和导电层186上形成绝缘或钝化层188。绝缘层188可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。通过刻蚀工艺除去绝缘层188的一部分以暴露导电层186。
使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在导电层186上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层186。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块190。在一些应用中，凸块190二次回流以改善到导电层186的电接触。所述凸块也可以被压缩结合到导电层186。凸块190表示一种可以形成在导电层186上的互连结构。所述互连结构也可以使用结合线、导电胶、柱形凸块、微凸块、或其它电互连。
利用PVD、CVD、印刷、旋涂、喷涂或热氧化工艺将绝缘或钝化层191形成在半导体管芯124的后表面132和密封剂130上。绝缘层191可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。
类似于图3e，利用激光钻孔、机械钻孔或DRIE来形成通过绝缘层191和半导体管芯124以及绝缘层182的多个通路。在沉积密封剂130之后形成这些通路，且半导体管芯124的有源表面128面向下。这些通路延伸通过绝缘层191和半导体管芯124的硅区以及绝缘层182至导电层186。类似地，类似于图3f，利用激光钻孔、机械钻孔或DRIE来形成通过绝缘层191和密封剂130以及绝缘层182的多个通路。这些通路从相同侧面形成并延伸到导电层186。这些通路在同一制造过程期间使用相同的载体120同时形成或者从相同侧面连续形成。
可以使用PVD、CVD或热氧化工艺在通路的侧壁上形成可选绝缘或介电层。绝缘层可以是一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO或其它适当的介电材料。
利用电解电镀、无电极电镀工艺或其它适当的金属沉积工艺，使用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其它适当的导电材料来填充通过密封剂130的通路以形成导电TMV192。TMV192电连接到导电层186的多个部分。利用电解电镀、无电极电镀工艺或其它适当的金属沉积工艺，使用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其它适当的导电材料来填充通过半导体管芯124的通路以形成导电TSV194。TSV194电连接到导电层186的其它部分。
使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在绝缘层191、TMV192和TSV194上形成导电层196。导电层196可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层196电连接到TMV192和TSV194并且用作RDL以扩展TMV和TSV的电连接性。
在绝缘层191和导电层196上沉积并图案化光致抗蚀剂层198。除去光致抗蚀剂层198的一部分以暴露导电层196。使用图案化和PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在导电层198上形成可选导电层200。导电层200可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层200形成包括阻挡层和粘附层的多层UBM。在一个实施例中，阻挡层包含Ni、TiW、CrCu、NiV、Pt、或Pd。粘附层包含Al、Ti、Cr、或TiN。UBM200提供低电阻互连，以及对Cu或焊料扩散的阻挡。可替换地，还可以在导电层196上形成可线结合的焊盘。导电层196、光致抗蚀剂层198和UBM200构成装配互连结构202。
在WLCSP204中，装配互连结构202通过导电TMV192和TSV194电连接到半导体管芯124的接触焊盘126和装配互连结构180的导电层184和186。在沉积密封剂130之后，TMV192和TSV194在同一制造过程期间从相同侧面形成。由于TSV194在密封之后形成，因此相同的支撑结构，即装配互连结构180，用于形成TMV192和TSV194两者。背景技术中提到的单独的制造工艺和不同的载体不再是必要的。此外，可以避免现有技术中要求的在TSV上的钝化层中形成通路。用于形成TSV194的通路延伸通过钝化层191，由此节省了现有技术中需要的工艺步骤。TMV192和TSV194的连续结构降低了接触电阻，提高了导电性，并改善了信号完整性。因此，在同一制造过程期间使用相同的支撑结构从相同侧面形成TMV192和TSV194简化了制造，降低了成本，并减小了缺陷的风险。在将半导体管芯124安装到载体120之后以及在沉积密封剂130之后形成TSV194减少了由于在晶片级TSV形成缺陷引起的器件失效。
图12示出来自图4的堆叠WLCSP164，其通过装配互连结构150的导电层146、UBM147、TMV142、TSV144、凸块160和导电层154和156在z方向上被电互连。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供半导体管芯；
在半导体管芯周围沉积密封剂；
在密封剂和半导体管芯上形成绝缘层；
形成多个第一导电通路，每个第一导电通路包含延伸通过绝缘层和半导体管芯的连续的侧壁；
在与第一导电通路相同的方向上形成多个第二导电通路，每个第二导电通路包含延伸通过绝缘层和密封剂的连续的侧壁；
在半导体管芯上形成第一互连结构；以及
在密封剂上与第一互连结构相对地形成第二互连结构并且电连接到第一导电通路和第二导电通路。
2.根据权利要求1的方法，进一步包括在于半导体管芯和密封剂上形成绝缘层之前平面化密封剂和半导体管芯的表面。
3.根据权利要求1的方法，其中形成多个第一导电通路的步骤进一步包括：
形成连续延伸通过绝缘层和半导体管芯的多个第一通路；
在第一通路的多个侧壁上沉积导电材料以形成第一导电通路；以及
在第一导电通路上在第一通路中沉积绝缘材料。
4.根据权利要求1的方法，进一步包括沉积围绕第一导电通路和第二导电通路的连续的侧壁的绝缘材料。
5.根据权利要求1的方法，进一步包括：
堆叠多个所述半导体器件；以及
通过第一和第二互连结构以及第一导电通路和第二导电通路电连接所述堆叠的半导体器件。
6.一种半导体器件，包括：
半导体管芯；
沉积在该半导体管芯周围的密封剂；
形成在密封剂和半导体管芯上的绝缘层；
第一导电通路，每个第一导电通路具有延伸通过绝缘层和半导体管芯的连续的侧壁；
在与第一导电通路相同的方向上的第二导电通路，每个第二导电通路具有延伸通过绝缘层和密封剂的连续的侧壁；
形成在密封剂上并且电连接到第一导电通路和第二导电通路的第一互连结构；
与第一互连结构相对地形成在密封剂上并且电连接到第一导电通路和第二导电通路的第二互连结构。
7.根据权利要求6的半导体器件，进一步包括形成在半导体管芯的接触焊盘上的凸块。
8.根据权利要求7的半导体器件，进一步包括沉积在凸块周围和半导体管芯下面的底层填充材料或密封剂。
9.根据权利要求6的半导体器件，进一步包括形成在第一导电通路和第二导电通路的连续的侧壁上的绝缘材料。
10.根据权利要求6的半导体器件，进一步包括通过第一和第二互连结构以及第一导电通路和第二导电通路被电连接的多个堆叠半导体器件。
11.一种制造半导体器件的方法，包括：
在半导体管芯周围沉积密封剂；
在半导体管芯和密封剂上形成绝缘层；
形成多个第一导电通路，每个第一导电通路具有延伸通过绝缘层和半导体管芯的连续的侧壁；以及
形成多个第二导电通路，每个第二导电通路具有延伸通过绝缘层和密封剂的连续的侧壁。
12.根据权利要求11的方法，进一步包括平面化密封剂和半导体管芯的表面。
13.根据权利要求11的方法，进一步包括在半导体管芯上形成多个凸块。
14.根据权利要求11的方法，进一步包括在绝缘层上形成第一互连结构。
15.根据权利要求14的方法，进一步包括与第一互连结构相对地形成在半导体管芯上的第二互连结构。
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