TWI531011B - 使用相同的載體在ｗｌｃｓｐ中形成ｔｍｖ和ｔｓｖ的半導體裝置及方法 - Google Patents

使用相同的載體在ｗｌｃｓｐ中形成ｔｍｖ和ｔｓｖ的半導體裝置及方法 Download PDF

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TWI531011B
TWI531011B TW100105582A TW100105582A TWI531011B TW I531011 B TWI531011 B TW I531011B TW 100105582 A TW100105582 A TW 100105582A TW 100105582 A TW100105582 A TW 100105582A TW I531011 B TWI531011 B TW I531011B
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conductor
semiconductor die
encapsulant
insulating layer
semiconductor
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TW100105582A
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TW201145416A (en
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瑞莎Ａ 派蓋菈
林耀劍
尹勝煜
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史達晶片有限公司
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Publication of TW201145416A publication Critical patent/TW201145416A/zh
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Description

使用相同的載體在WLCSP中形成TMV和TSV的半導體裝置及方法
本發明大體上和半導體裝置有關，且更明確地說，和使用相同的載板在相同的製程期間於相同的方向中在WLCSP中形成TMV和TSV的半導體裝置及方法有關。
在現代的電子產品中經常會發現半導體裝置。半導體裝置會有不同數量與密度的電組件。離散式半導體裝置通常含有某一種類型的電組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。積體式半導體裝置通常含有數百個至數百萬個電組件。積體式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施各式各樣的功能，例如，高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置會利用半導體材料的電氣特性。半導體材料的原子結構會使得可藉由施加電場或基礎電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至該半導體材料之中，以便操縱及控制該半導體裝置的傳導性。
一半導體裝置會含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜程度以及施加電場或基礎電流，該電晶體便會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電連接以形成讓該半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常相同並且含有藉由電連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的晶粒並且封裝該晶粒，用以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便係生產較小型半導體裝置。較小型裝置通常會消耗較少的電力，具有較高的效能，並且能夠被更有效地生產。此外，較小型半導體裝置還具有較小的覆蓋區，這係較小型末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小尺寸以及較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電互連材料及封裝材料而導致具有較小覆蓋區的半導體裝置封裝。
半導體裝置通常需要用到垂直互連結構，舉例來說，當堆疊多個裝置以達有效整合的目的時。半導體裝置(例如，在多層之中含有半導體晶粒的扇出晶圓級晶片規模封裝(Fan-Out Wafer Level Chip Scale Package，FO-WLCSP))和外部裝置之間的電互連能夠利用下面來完成：導體直通矽晶穿孔(Through Silicon Via，TSV)、導體直通孔洞穿孔(Through Hole Via，THV)、導體直通模具穿孔(Through Mold Via，TMV)、鍍銅導體柱、以及導體凸塊。該些垂直互連結構既昂貴且在製造過程期間相當耗時，並且在形成期間很容易會有缺陷。
明確地說，在一WLCSP中，會在進行單體化裁切之前以晶圓的形式利用第一載板作支撐先形成該導體TSV。稍後，則會在該製程中於進行囊封之後利用一不同的載板作支撐來形成該導體TMV。一增進互連結構通常會被形成在該半導體晶粒的上方。其還會需要用到額外的處理步驟在該等增進層中形成多個穿孔，用以改變TSV的路徑，以便互連至上方半導體裝置。於該半導體晶粒中形成TSV之後，必須在該等TSV上方的鈍化層中形成多個導體穿孔，用以將該等TSV電連接至上方導體層。因為TSV和TMV係在不同的載板上藉由不同的製程所形成，所以，該製程會需要用到更多時間、材料、以及步驟，其會增加成本並且提高在該半導體裝置或整個晶圓中產生缺陷的風險。舉例來說，因為該TSV係在仍處於晶圓形式時被形成，所以，該半導體晶圓很容易遭到損壞。
本技術領域需要一種用以在WLCSP中形成TSV和TMV的簡單且低成本的製程。據此，於其中一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一暫時性載板；將一半導體晶粒鑲嵌在該暫時性載板的上方；將一囊封劑沉積在該半導體晶粒與暫時性載板的上方；在該半導體晶粒與囊封劑的上方形成一第一絕緣層；在被鑲嵌至該暫時性載板時形成複數個第一穿孔，貫穿該第一絕緣層與半導體晶粒；在該半導體晶粒被鑲嵌至該暫時性載板時形成複數個第二穿孔，貫穿該第一絕緣層與囊封劑；於該等第一穿孔中沉積導電材料，用以形成導體TSV；於該等第二穿孔中沉積導電材料，用以形成導體TMV；在該第一絕緣層的上方形成一第一互連結構而且其會被電連接至該導體TSV與導體TMV；移除該暫時性載板；以及在該半導體晶粒與囊封劑的上方形成一第二互連結構，其會與該第一互連結構反向並且會被電連接至該導體TSV與導體TMV。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一載板；將一半導體晶粒鑲嵌在該載板的上方；將一囊封劑沉積在該半導體晶粒與載板的上方；在被鑲嵌至該載板時形成複數個第一穿孔，貫穿該半導體晶粒；在和該等第一穿孔相同的方向中形成複數個第二穿孔，貫穿該囊封劑；於該等第一穿孔中沉積導電材料用以形成多個第一導體穿孔並且於該等第二穿孔中沉積導電材料用以形成多個第二導體穿孔；在該囊封劑的上方形成一第一互連結構而且其會被電連接至該等第一導體穿孔與第二導體穿孔；移除該載板；以及在該囊封劑的上方形成一第二互連結構，其會與該第一互連結構反向並且會被電連接至該等第一導體穿孔與第二導體穿孔。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一載板；將一半導體晶粒鑲嵌在該載板的上方，該半導體晶粒的主動表面會朝向該載板；將一囊封劑沉積在該半導體晶粒與載板的上方；移除該載板；在該囊封劑及該半導體晶粒的主動表面的上方形成一第一互連結構；形成複數個第一穿孔，貫穿該半導體晶粒以及該第一互連結構的一部分；在和該等第一穿孔相同的方向中形成複數個第二穿孔，貫穿該囊封劑以及該第一互連結構的一部分；於該等第一穿孔中沉積導電材料用以形成多個第一導體穿孔並且於該等第二穿孔中沉積導電材料用以形成多個第二導體穿孔；以及在該囊封劑的上方形成一第二互連結構，其會與該第一互連結構反向並且會被電連接至該等第一導體穿孔與第二導體穿孔。
於另一實施例中，本發明係一種半導體裝置，其包括一半導體晶粒以及一被沉積在該半導體晶粒上方的囊封劑。一第一導體穿孔會被形成貫穿該半導體晶粒。一第二導體穿孔會在和該第一導體穿孔相同的方向中被形成貫穿該囊封劑。一第一互連結構會被形成在該囊封劑的上方並且會被電連接至該第一導體穿孔與第二導體穿孔。一第二互連結構會被形成在該囊封劑的上方，其會與該第一互連結構反向並且會被電連接至該第一導體穿孔與第二導體穿孔。
在下面的說明中會參考圖式於一或多個實施例中來說明本發明，於該等圖式中，相同的符號代表相同或雷同的元件。雖然本文會以達成本發明目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效範圍所定義的本發明的精神與範疇內可能併入的替代例、修正例以及等效例。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電組件和被動式電組件，它們會被電連接而形成功能性電路。主動式電組件(例如電晶體與二極體)能夠控制電流的流動。被動式電組件(例如電容器、電感器、電阻器以及變壓器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會修正主動式裝置中半導體材料的導電性，將該半導體材料轉換成絕緣體、導體，或是響應於電場或基礎電流來動態改變半導體材料傳導性。電晶體含有不同類型和摻雜程度的多個區域，它們會在必要時被排列成用以在施加一電場或基礎電流時讓該電晶體會提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料構成。該等層能夠藉由各式各樣的沉積技術來形成，其部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件、或是組件之間的電連接線的一部分。
該等層能夠利用光微影術來圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一已圖樣化層。或者，某些類型的材料被圖樣化的方式係利用無電極電鍍以及電解質電鍍之類的技術，藉由將該材料直接沉積至先前沉積及/或蝕刻製程所形成的區域或空隙(void)之中。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。有磨蝕作用的材料以及腐蝕性的化學藥劑會在研磨期間被加到晶圓的表面。化學藥劑的磨蝕性作用及腐蝕性作用所組成的組合式機械作用會移除任何不規律的拓樸形狀，從而產生均勻平坦的表面。
後端製造係指將已完成的晶圓切割或單體化裁切成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為單體化裁切晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。該晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別晶粒便會被鑲嵌至包含接針或接觸觸墊的封裝基板，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸觸墊接著會被連接至該封裝裡面的接觸觸墊。該等電連接線可利用焊料凸塊、短柱凸塊、導電膏或是焊線來製成。一囊封劑或是其它模造材料會被沉積在該封裝的上方，用以提供物理性支撐和電隔離。接著，該已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖1圖解一電子裝置50，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)52，在其表面上鑲嵌著複數個半導體封裝。電子裝置50可能具有某一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋目的，圖1中便顯示該等不同類型的半導體封裝。
電子裝置50可能係一單機型系統，其會使用該等半導體封裝來實施一或多項電功能。或者，電子裝置50亦可能係一較大型系統中的一子組件。舉例來說，電子裝置50可能係一圖形卡、一網路介面卡或是能夠被插入在一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、RF電路、離散式裝置或是其它半導體晶粒或電組件。
在圖1中，PCB 52提供一通用基板，用以結構性支撐及電互連被鑲嵌在該PCB之上的半導體封裝。多條導體訊號線路54會利用下面製程被形成在PCB 52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程。訊號線路54會在該等半導體封裝、被鑲嵌的組件以及其它外部系統組件中的每一者之間提供電通訊。線路54還會提供連接至每一個該等半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載板的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載板附接至該PCB。於其它實施例中，一半導體裝置可能僅有該第一層封裝，其中，該晶粒會以機械方式及電氣方式直接被鑲嵌至該PCB。
為達解釋的目的，圖中在PCB 52之上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被鑲嵌在PCB 52之上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載板(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合的半導體封裝和其它電子組件所組成的任何組合皆能夠被連接至PCB 52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製造的組件併入電子裝置和系統之中。因為該等半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而讓消費者的成本會較低。
圖2a至2c所示的係示範性半導體封裝。圖2a所示的係被鑲嵌在PCB 52之上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74之主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路元件。接觸觸墊76係一或多層導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或是銀(Ag))，並且會被電連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂)被鑲嵌至一中間載板78。該封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與PCB 52之間提供電互連。囊封劑84會被沉積在該封裝的上方，防止濕氣和粒子進入該封裝並污染晶粒74或焊線82以達環境保護的目的。
圖2b所示的係被鑲嵌在PCB 52之上的BCC 62的進一步細節。半導體晶粒88會利用底層填充材料或環氧樹脂膠黏材料92被鑲嵌在載板90的上方。焊線94會在接觸觸墊96與98之間提供第一層封裝互連。模造化合物或囊封劑100會被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。多個接觸觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在PCB 52的一表面上方，用以防止氧化。接觸觸墊102會被電連接至PCB 52之中的一或多條導體訊號線路54。多個凸塊104會被形成在BCC 62的接觸觸墊98和PCB 52的接觸觸墊102之間。
在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載板106。半導體晶粒58的主動區108含有類比電路或數位電路，該等類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、導體層以及介電層。舉例來說，該電路可能包含被形成在主動區108裡面的一或多個電晶體、二極體、電感器、電容器、電阻器以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載板106。
BGA 60會以利用多個凸塊112的BGA樣式第二層封裝，以電氣方式及機械方式被連接至印刷電路板52。半導體晶粒58會經由凸塊110、訊號線114以及凸塊112被電連接至PCB 52之中的導體訊號線路54。一模造化合物或囊封劑116會被沉積在半導體晶粒58和載板106的上方，用以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置會從半導體晶粒58上的主動式裝置至PCB 52上的傳導軌提供一條短電傳導路徑，以便縮短訊號傳導距離、降低電容、並且改善整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接被連接至PCB 52，而沒有中間載板106。
圖3a至3j所示的係使用相同的載板在相同的製程期間於相同的方向中在WLCSP中形成TMV和TSV的製程。在圖3a中，一犧牲性或暫時性基板或載板120含有基礎材料，例如，矽、聚合物、高分子合成物、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、膠帶或是其它合宜的低成本剛性材料，用以達到結構性支撐的目的。一非必要的介面層122會被形成在載板120的上方，作為一暫時性雙面黏著膠帶或焊接膜或蝕刻阻止層。
在圖3b中，半導體晶粒或組件124會被鑲嵌至載板120，接觸觸墊126則以面朝下的方式位於該載板的上方。半導體晶粒124具有一主動區128，其含有類比電路或數位電路，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面128裡面的一或多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體或是其它訊號處理電路。半導體晶粒124可能還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。半導體晶粒124可能會一覆晶類型的裝置或焊線類型的裝置。於另一實施例中，一離散式組件可能會被鑲嵌在介面層122與載板120的上方。
圖3c所示的係一囊封劑或模造化合物130，其係利用焊膏印刷(paste printing)塗敷機、壓縮模造(compressive molding)塗敷機、轉印模造(transfer molding)塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機或是其它合宜的塗敷機被沉積在半導體晶粒124與載板120的上方。囊封劑130可能係高分子合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯或是具有適當填充劑的聚合物。囊封劑130係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。囊封劑130會被平坦化，以便露出半導體晶粒124中和主動表面128反向的背表面132。
在圖3d中，一絕緣層或鈍化層134會被形成在半導體晶粒124的背表面132以及囊封劑130的上方，其係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗或是熱氧化。該絕緣層134可能係由下面所製成的一或多層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)或是具有雷同絕緣特性及結構性特性的其它材料。
在圖3e中，當該半導體晶粒124被鑲嵌至載板120時，會利用雷射鑽鑿、機械鑽鑿或是深反應離子蝕刻(Deep Reactive Ion Etching，DRIE)製程形成複數個穿孔136，貫穿絕緣層134以及該晶粒。該等穿孔136係在沉積囊封劑130之後由絕緣層134及背側132所構成，半導體晶粒124的主動表面128會面朝下方。該等穿孔136會延伸穿過半導體晶粒124的矽質區抵達接觸觸墊126。相同地，在圖3f中，當該半導體晶粒124被鑲嵌至載板120時，會利用雷射鑽鑿、機械鑽鑿或是DRIE形成複數個穿孔138，貫穿絕緣層134以及囊封劑130。該等穿孔138係由和穿孔136相同的側所構成並且會延伸至介面層122。該等穿孔136與138係利用相同的載板120於相同的製程期間由相同側同時或陸續被形成。
一非必要的絕緣層或介電層140會利用PVD、CVD、或是熱氧化製程被形成在穿孔136與138的側壁之上。該絕緣層140可能係由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚亞醯胺、環苯丁烯(BCB)、聚苯并噁唑纖維(PBO)或是其它合宜的介電材料。其餘說明接續如上，不過，並沒有非必要的絕緣層140。
在圖3g中，該等穿孔138會利用電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、W、多晶矽或是其它合宜的導電材料填充，以便形成導體直通模具穿孔(TMV)142。該等穿孔136會利用電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶矽或是其它合宜的導電材料填充，以便形成導體直通矽晶穿孔(TSV)144。TSV 144會被連接至接觸觸墊126。
一導電層146會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在絕緣層134、TMV 142以及TSV 144的上方。導體層146可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層146中的個別部分會被電連接至TMV 142與TSV 144並且當作一重新分配層(ReDistribution Layer，RDL)，用以延伸該等TMV與TSV的導電性。
在圖3h中，一光阻層148會被沉積在絕緣層134與導體層146的上方並且會被圖樣化。一部分的光阻層148會被移除，用以露出導體層146。一非必要的導體層147會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程或是其它合宜的金屬沉積製程被形成在導體層146的上方。導體層147可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層147會形成一多層凸塊下層金屬(Under Bump Metallization，UBM)，其包含一屏障層以及膠黏層。於其中一實施例中，該屏障層含有Ni、鎢化鈦(TiW)、銅化鉻(CrCu)、釩化鎳(NiV)、鉑(Pt)或是鈀(Pd)。該膠黏層含有Al、鈦(Ti)、鉻(Cr)或是氮化鈦(TiN)。UBM 147會提供一低電阻互連，並且提供一防止Cu或焊料擴散的屏障。或者，多個可線焊的觸墊亦可能會被形成在導體層146的上方。導體層146、光阻層148、以及UBM 147會構成一增進互連結構149。
在圖3i中，載板120與介面層122會藉由下面方式被移除：化學性蝕刻、機械性剝離、CMP、機械性研磨、熱烘烤、雷射掃描或是濕式剝除。一增進互連結構150會被形成在主動表面128和囊封劑130的上方。該增進互連結構150包含一絕緣層或鈍化層152，其係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗或是熱氧化。該絕緣層152可能係由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層152會藉由一蝕刻製程被移除，用以露出TMV 142與TSV 144。一導電層154會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程或是其它合宜的金屬沉積製程被形成在絕緣層152的已移除部分之中。導體層154可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層154中的個別部分會被電連接至TMV 142與TSV 144。
在圖3j中，該增進互連結構150還進一步包含一導電層156，其會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在絕緣層152以及導體層154的上方。導體層156可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層156中的個別部分會被電連接至TMV 142與TSV 144並且當作一RDL，用以延伸該等TMV與TSV的導電性。
一絕緣層或鈍化層158會利用下面方式被形成在絕緣層152與導體層156的上方：PVD、CVD、印刷、旋塗、噴塗或是熱氧化。該絕緣層158可能係由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層158會藉由一蝕刻製程被移除，用以露出導體層156。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程被沉積在導體層156的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層156。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊160。於某些應用中，凸塊160會被二次回焊，以便改善和導體層156的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層156。凸塊160代表能夠被形成在導體層156上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、導電膏、短柱凸塊、微凸塊或是其它電互連。
半導體晶粒124會利用鋸片或雷射裁切工具被單體化裁切成可堆疊的WLCSP 164。圖4所示的係經過單體化裁切之後的WLCSP 164。增進互連結構149會經由導體TMV 142與TSV 144被電連接至半導體晶粒124的接觸觸墊126以及增進互連結構150的導體層154與156。TMV 142與TSV 144係在沉積囊封劑130之後於相同的製程期間由相同側所構成。因為TSV 144係在囊封之後才被形成，所以，可以使用相同的載板120來形成TMV 142與TSV 144兩者；從而不再需要先前技術中所提及的不同製程以及不同的載板。此外，亦可以避免先前技術中所規定的在該等TSV上方的鈍化層之中形成穿孔。用來形成TSV 144的該等穿孔136會延伸貫穿鈍化層134，從而省略先前技術中所需要的一製程步驟。TMV 142與TSV 144的連續性結構會降低接觸阻值、提高導電性並且改善訊號完整性。據此，使用相同的載板120於相同的製程期間由相同側來形成TMV 142與TSV 144會簡化製造、降低成本並且減少缺陷的風險。在將半導體晶粒124鑲嵌至載板120之後並且在沉積囊封劑130之後才形成TSV 144會減少因晶圓級中的TSV構成缺陷所導致的裝置故障。
圖5所示的係一和圖4雷同的實施例，其中，多個TSV 144會被電連接至主動表面128裡面的多個電路節點，用以提供額外的垂直(z方向)互連，以便增加上方堆疊半導體裝置的輸入/輸出(I/O)數量和密度。TSV 144還會被電連接至一部分的導體層154與導體層156。其它部分的導體層156與導體層154則會被電連接至接觸觸墊126。
圖6所示的係一和圖4雷同的實施例，其中，囊封劑130會覆蓋半導體晶粒124的背表面132。在圖3d中所述的絕緣層134會被省略，因為囊封劑130會提供電氣與結構性隔離效果。
圖7所示的係一接續圖3f的實施例，導體層166會使用圖樣化以及電解質電鍍、無電極電鍍製程或是其它合宜的金屬沉積製程被保形形成在穿孔136與138的側壁上，其並不會完全填充該等穿孔。導體層166可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。
一導電層168會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程或是其它合宜的金屬沉積製程被形成在絕緣層134的上方。導體層168可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層168會被電連接至被形成在穿孔136與138之中的導體層166並且當作一RDL，用以延伸該等TMV與TSV的導電性。
一光阻層或絕緣層170會被沉積在絕緣層134與導體層168的上方並且會被圖樣化。光阻170會填充導體層166上方穿孔136與138剩餘的區域。一部分的光阻層170會被移除，用以露出導體層168。一非必要的UBM 171會被形成在導體層168的上方。導體層168、光阻層170以及UBM 171會構成一增進互連結構173。該製程的剩餘部分則遵循圖3g至3j。
圖8所示的係一和圖4雷同的實施例，其中，在將半導體晶粒124鑲嵌至載板120之前，多個凸塊172會先被形成在接觸觸墊126之上且多個接觸觸墊174會被形成在載板120之上。具有凸塊172的半導體晶粒124會被鑲嵌至多個接觸觸墊174。接觸觸墊174會被電連接至導體層154。凸塊172會提供更細小的互連間距並且提高I/O密度。囊封劑130並不會完全填充半導體晶粒124。
圖9所示的係一和圖8雷同的實施例，其中，多個TSV 144會被電連接至主動表面128裡面的多個電路節點，用以提供額外的垂直(z方向)互連，以便增加上方堆疊半導體裝置的輸入/輸出(I/O)數量和密度。TSV 144會延伸穿過囊封劑130，以便電連接至一部分的導體層154與導體層156。其它部分的導體層156與導體層154則會被電連接至凸塊172以及接觸觸墊126與174。
圖10所示的係一和圖9雷同的實施例，其中，一底層填充材料176(例如，環氧樹脂)會被沉積在半導體晶粒124的下方。多個TSV 144會被電連接至主動表面128裡面的多個電路節點，用以提供額外的垂直(z方向)互連，以便增加上方堆疊半導體裝置的輸入/輸出(I/O)數量和密度。TSV 144會延伸穿過底層填充材料176，以便電連接至一部分的導體層154與導體層156。其它部分的導體層156與導體層154則會被電連接至接觸觸墊126。
圖11所示的係一接續圖3c的實施例，載板120與介面層122會藉由下面方式被移除：化學性蝕刻、機械性剝離、CMP、機械性研磨、熱烘烤、雷射掃描或是濕式剝除。一增進互連結構180會被形成在主動表面128和囊封劑130的上方。該增進互連結構180包含一絕緣層或鈍化層182，其係利用下面方法所形成：PVD、CVD、印刷、旋塗、噴塗或是熱氧化。該絕緣層182可能係由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層182會藉由一蝕刻製程被移除，用以露出接觸觸墊126。一導電層184會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程或是其它合宜的金屬沉積製程被形成在絕緣層182的已移除部分之中。導體層184可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層184會被電連接至接觸觸墊126。
一導電層186會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在絕緣層182的上方。導體層186可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層186的個別部分會當作一RDL，用以延伸導電性。
一絕緣層或鈍化層188會利用下面方式被形成在絕緣層182與導體層186的上方：PVD、CVD、印刷、旋塗、噴塗、或是熱氧化。該絕緣層188可能係由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層188會藉由一蝕刻製程被移除，用以露出導體層186。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程或是網印製程被沉積在導體層186的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層186。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊190。於某些應用中，凸塊190會被二次回焊，以便改善和導體層186的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層186。凸塊190代表能夠被形成在導體層186上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、導電膏、短柱凸塊、微凸塊或是其它電互連。
一絕緣層或鈍化層191會利用下面方式被形成在半導體晶粒124的背表面132與囊封劑130的上方：PVD、CVD、印刷、旋塗、噴塗、或是熱氧化製程。該絕緣層191可能係由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3或是具有雷同絕緣特性及結構性特性的其它材料。
複數個穿孔會利用雷射鑽鑿、機械鑽鑿或是DRIE被形成貫穿絕緣層191以及半導體晶粒124以及絕緣層182，和圖3e雷同。該等穿孔係在沉積囊封劑130之後才被形成，半導體晶粒124的主動表面128會面朝下方。該等穿孔會延伸貫穿絕緣層191以及半導體晶粒124的矽質區以及絕緣層182，抵達導體層186。同樣地，複數個穿孔會利用雷射鑽鑿、機械鑽鑿、或是DRIE被形成貫穿絕緣層191以及囊封劑130以及絕緣層182，和圖3f雷同。該等穿孔係由相同側所構成並且會延伸至導體層186。該等穿孔係利用相同的載板120於相同的製程期間由相同側同時或陸續被形成。
一非必要的絕緣層或介電層會利用PVD、CVD或是熱氧化製程被形成在該等穿孔的側壁之上。該絕緣層可能係由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚亞醯胺、BCB、PBO或是其它合宜的介電材料。
該等貫穿囊封劑130的穿孔會利用電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶矽或是其它合宜的導電材料填充，以便形成導體TMV 192。TMV 192會被電連接至導體層186中的多個部分。該等貫穿半導體晶粒124的穿孔會利用電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶矽或是其它合宜的導電材料填充，以便形成導體TSV 194。TSV 194會被電連接至導體層186中的其它部分。
一導電層196會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在絕緣層191、TMV 192以及TSV 194的上方。導體層196可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層196會被電連接至TMV 192與TSV 194並且當作一RDL，用以延伸該等TMV與TSV的導電性。
一光阻層198會被沉積在絕緣層191與導體層196的上方並且會被圖樣化。一部分的光阻層198會被移除，用以露出導體層196。一非必要的導體層200會使用圖樣化以及PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在導體層198的上方。導體層200可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag或是其它合宜的導電材料。導體層200會形成一多層UBM，其包含一屏障層以及膠黏層。於其中一實施例中，該屏障層含有Ni、TiW、CrCu、NiV、Pt或是Pd。該膠黏層含有Al、Ti、Cr或是TiN。UBM 200會提供一低電阻互連，並且提供一防止Cu或焊料擴散的屏障。或者，多個可線焊的觸墊亦可能會被形成在導體層196的上方。導體層196、光阻層198以及UBM 200會構成一增進互連結構202。
在WLCSP 204之中，增進互連結構202會經由導體TMV 192與TSV 194被電連接至半導體晶粒124的接觸觸墊126以及增進互連結構180的導體層184與186。TMV 192與TSV 194係在沉積囊封劑130之後於相同的製程期間由相同側所構成。因為TSV 194係在囊封之後才被形成，所以，可以使用相同的支撐結構，也就是，增進互連結構180，來形成TMV 192與TSV 194兩者；從而不再需要先前技術中所提及的不同製程以及不同的載板。此外，亦可以避免先前技術中所規定的在該等TSV上方的鈍化層之中形成穿孔。用來形成TSV 194的該等穿孔會延伸貫穿鈍化層191，從而省略先前技術中所需要的一製程步驟。TMV 192與TSV 194的連續性結構會降低接觸阻值、提高導電性、並且改善訊號完整性。據此，使用相同的支撐結構於相同的製程期間由相同側來形成TMV 192與TSV 194會簡化製造、降低成本、並且減少缺陷的風險。在將半導體晶粒124鑲嵌至載板120之後並且在沉積囊封劑130之後才形成TSV 194會減少因晶圓級中的TSV構成缺陷所導致的裝置故障。
圖12所示的係圖4中已藉由導體層146、UBM 147、TMV 142、TSV 144、凸塊160以及增進互連結構150的導體層154與156在z方向中電互連的堆疊WLCSP 164。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會明白，可以對該些實施例進行修正與改變，其並不會脫離後面申請專利範圍中所提出的本發明的範疇。
50．．．電子裝置
52．．．PCB
54．．．導體訊號線路
56．．．焊線封裝
58．．．覆晶
60．．．球柵陣列
62．．．凸塊晶片載板
64．．．雙直列封裝
66．．．平台格柵陣列
68．．．多晶片模組
70．．．方形扁平無導線封裝
72．．．方形扁平封裝
74．．．半導體晶粒
76．．．接觸觸墊
78．．．中間載板
80．．．導體導線
82．．．焊線
84．．．囊封劑
88．．．半導體晶粒
90．．．載板
92．．．底層填充或環氧樹脂膠黏材料
94．．．焊線
96．．．接觸觸墊
98．．．接觸觸墊
100．．．模造化合物或囊封劑
102．．．接觸觸墊
104．．．凸塊
106．．．中間載板
108．．．主動區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．模造化合物或囊封劑
120．．．基板或載板
122．．．非必要的介面層
124．．．半導體晶粒
126．．．接觸觸墊
128．．．主動表面
130．．．囊封劑或模造化合物
132．．．背表面
134．．．絕緣層或鈍化層
136．．．穿孔
138．．．穿孔
140．．．絕緣層或介電層
142．．．TMV
144．．．TSV
146．．．導電層
147．．．非必要的導體層
148．．．光阻層
149．．．增進互連結構
150．．．增進互連結構
152．．．絕緣層或鈍化層
154．．．導體層
156．．．導電層
158．．．絕緣層或鈍化層
160．．．凸塊
162．．．鋸片或雷射切割工具
164．．．WLCSP
166．．．導體層
168．．．導體層
170．．．光阻層
171．．．UBM
172．．．凸塊
173．．．增進互連結構
174．．．接觸觸墊
176．．．底層填充材料
180．．．增進互連結構
182．．．絕緣層
184．．．導電層
186．．．導電層
188．．．絕緣層或鈍化層
190．．．凸塊
191．．．絕緣層
192．．．TMV
194．．．TSV
196．．．導電層
198．．．光阻層
200．．．非必要的導體層
202．．．增進互連結構
204．．．WLCSP
圖1所示的係一PCB，在其表面上鑲嵌著不同類型的封裝；
圖2a至2c所示的係被鑲嵌至該PCB的代表性半導體封裝的進一步細節；
圖3a至3j所示的係使用相同的載板在相同的製程期間於相同的方向中在WLCSP中形成TMV和TSV的製程；
圖4所示的係具有多個TMV和多個TSV的可堆疊WLCSP；
圖5所示的係被電連接至晶粒之主動表面的TSV；
圖6所示的係用以覆蓋半導體晶粒之背表面的囊封劑；
圖7所示的係被保形形成在該等穿孔之中並且接著被光阻材料填充的TMV和TSV；
圖8所示的係被鑲嵌至載板上的接觸觸墊的有凸塊的半導體晶粒；
圖9所示的係被鑲嵌至載板上的接觸觸墊的有凸塊的半導體晶粒以及被電連接至該晶粒之主動表面的TSV；
圖10所示的係利用底層填充材料被鑲嵌至載板上的接觸觸墊的有凸塊的半導體晶粒；
圖11所示的係使用下方增進互連結構作為支撐於相同的方向中在相同的製程期間形成TMV和TSV；以及
圖12所示的係已藉由該等TMV、TSV以及互連結構互連的堆疊WLCSP。
124．．．半導體晶粒
126．．．接觸觸墊
128．．．主動表面
130．．．囊封劑或模造化合物
132．．．背表面
134．．．絕緣層或鈍化層
142．．．TMV
144．．．TSV
146．．．導電層
147．．．非必要的導體層
148．．．光阻層
149．．．增進互連結構
150．．．增進互連結構
152．．．絕緣層或鈍化層
154．．．導體層
156．．．導電層
158．．．絕緣層或鈍化層
160．．．凸塊
162．．．鋸片或雷射切割工具
164．．．WLCSP

Claims (15)

  1. 一種製造半導體裝置的方法，其包括：提供一載板；將一半導體晶粒鑲嵌在該載板的上方；將一囊封劑沉積在該半導體晶粒與該載板的上方；在該半導體晶粒與該囊封劑的上方形成一第一絕緣層；在被鑲嵌至該載板時形成複數個第一穿孔，延伸貫穿該第一絕緣層與該半導體晶粒；在該半導體晶粒被鑲嵌至該載板時形成複數個第二穿孔，延伸貫穿該第一絕緣層與該囊封劑；於延伸貫穿該第一絕緣層與該半導體晶粒的該第一穿孔中沉積一導電材料，用以形成複數個導體直通矽晶穿孔(TSV)，其具有延伸貫穿該絕緣層與該半導體晶粒的一連續側壁；於該第二穿孔中沉積一導電材料，用以形成複數個導體直通模具穿孔(TMV)，其具有延伸貫穿該絕緣層與該囊封劑的一連續側壁；在該第一絕緣層的上方形成一第一互連結構而且其會被電連接至該導體TSV與該導體TMV；以及在該半導體晶粒與該囊封劑的上方形成一第二互連結構，其會與該第一互連結構反向並且會被電連接至該導體TSV與該導體TMV。
  2. 如申請專利範圍第1項的方法，其中，該導體TSV 會被電連接至該半導體晶粒上的複數個接觸觸墊或是該半導體晶粒的一表面。
  3. 如申請專利範圍第1項的方法，其進一步包含在該導體TSV上方沉積一第二絕緣材料。
  4. 如申請專利範圍第1項的方法，其進一步包含在該半導體晶粒下方且在形成於該半導體晶粒上的複數個凸塊附近沉積該囊封劑或一底層填充材料。
  5. 如申請專利範圍第1項的方法，其進一步包含沉積一第二絕緣材料於該導體TSV或該導體TMV的側壁上方。
  6. 一種製造半導體裝置的方法，其包括：提供一半導體晶粒；將一囊封劑沉積在該半導體晶粒的上方；在該半導體晶粒與該囊封劑的上方形成一絕緣層；形成貫穿該絕緣層與該半導體晶粒的複數個第一穿孔；形成貫穿該絕緣層和該囊封劑的複數個第二穿孔；於該第一穿孔中沉積一導電材料用以形成複數個第一導體穿孔，貫穿該絕緣層與該半導體晶粒；於該第二穿孔中沉積一導電材料用以形成複數個第二導體穿孔，貫穿該絕緣層與該囊封劑；在該囊封劑的上方形成一第一互連結構而且其會被電連接至該第一導體穿孔與該第二導體穿孔；以及在該囊封劑的上方形成一第二互連結構，其會與該第一互連結構反向並且會被電連接至該第一導體穿孔與該第 二導體穿孔。
  7. 如申請專利範圍第6項的方法，其進一步包含：在形成該第一互連結構之前平坦化該囊封劑和該半導體晶粒的一表面。
  8. 如申請專利範圍第6項的方法，其進一步包含在該第一導體穿孔上方沉積一絕緣材料。
  9. 如申請專利範圍第6項的方法，其進一步包含在該半導體晶粒的複數個接觸觸墊之上形成複數個凸塊。
  10. 如申請專利範圍第9項的方法，其進一步包含於該凸塊附近與在該半導體晶粒下方沉積該囊封劑或一底層填充材料。
  11. 如申請專利範圍第6項的方法，其進一步包含：堆疊複數個該半導體裝置；以及經由該第一互連結構與該第二互連結構以及該第一導體穿孔與該第二導體穿孔來電連接已堆疊的該半導體裝置。
  12. 一種半導體裝置，其包括：一半導體晶粒；一囊封劑，其被沉積在該半導體晶粒上方；一絕緣層，其形成在該半導體晶粒與該囊封劑上方；一第一互連結構，其形成在該囊封劑和該半導體晶粒上方；一第一導體穿孔，其會被形成以延伸貫穿該絕緣層與該半導體晶粒且進入該第一互連結構； 一第二導體穿孔，其會被形成以延伸貫穿該絕緣層與該囊封劑且進入該第一互連結構；以及一第二互連結構，其會被形成在該囊封劑的上方，其會與該第一互連結構反向並且會被電連接至該第一導體穿孔與該第二導體穿孔。
  13. 如申請專利範圍第12項的半導體裝置，其進一步包含被沉積在該半導體晶粒下方且在形成於該半導體晶粒上的複數個凸塊附近的一底層填充材料或該囊封劑。
  14. 如申請專利範圍第12項的半導體裝置，其進一步包含沉積在該第一導體穿孔或該第二導體穿孔的一側壁上方的一絕緣材料。
  15. 如申請專利範圍第12項的半導體裝置，其進一步包含經由該第一互連結構與該第二互連結構以及該第一導體穿孔與該第二導體穿孔被電連接的複數個堆疊半導體裝置。
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