TWI496271B - 晶圓級模封接合結構及其製造方法 - Google Patents

晶圓級模封接合結構及其製造方法 Download PDF

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Publication number
TWI496271B
TWI496271B TW099146766A TW99146766A TWI496271B TW I496271 B TWI496271 B TW I496271B TW 099146766 A TW099146766 A TW 099146766A TW 99146766 A TW99146766 A TW 99146766A TW I496271 B TWI496271 B TW I496271B
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Taiwan
Prior art keywords
wafer
crystal
layer
patterned conductive
conductive layer
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TW099146766A
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English (en)
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TW201227915A (en
Inventor
Su Tsai Lu
Jing Ye Juang
Yu Min Lin
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Ind Tech Res Inst
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Priority to TW099146766A priority Critical patent/TWI496271B/zh
Priority to US12/981,475 priority patent/US8384215B2/en
Priority to CN2011100342880A priority patent/CN102543969A/zh
Publication of TW201227915A publication Critical patent/TW201227915A/zh
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Publication of TWI496271B publication Critical patent/TWI496271B/zh

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    • H01L23/293—Organic, e.g. plastic
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Description

晶圓級模封接合結構及其製造方法
本發明是有關於一種晶圓級模封接合結構及其製造方法。
利用三維(Three Dimension，3D)積體電路(IC)整合技術提供高密度晶片構裝技術並達成高效率及低秏能，為目前最有希望解決未來大型晶片運作之方案之一。尤其在中央處理器(CPU)、快取記憶體、以及記憶卡應用中的快閃記憶體(Flash)與控制器(Controller)間資料的傳輸上，更能突顯矽晶片穿孔內部互連(through-silicon-via,TSV)的短距離內部接合路徑所帶來的效能優勢。
因此，在強調多功能、小尺寸的可攜式電子產品領域，如固態硬碟(Solid State Disk，SSD)和動態隨機存取記憶體(DRAM)等等新設計的堆疊結構，除可強化應用所強調的高速效能表現，亦可對晶片功耗的部份有所助益。在同樣的輸入/輸出(I/O)數目下，可以降低驅動所需的功粍，同步解決容量、效能與I/O提高的需求。此外，3D晶片的小型化特性更是市場導入的首要因素，現今3D晶片整合技術的主軸技術包含矽晶片穿孔內部互連(Through-silicon-via,TSV)、微凸塊(Micro Bump)接點製作、晶圓薄化(Wafer Thinning)、對準(Alignment)、接合(Bonding)及點膠製程的建立。
由於晶圓/晶圓對接技術(wafer-on-wafer,WOW)仍有晶片良率(known good dies,KGD)不足的問題，導致整體構裝之良率無法改善。因此，採用晶片/晶片接合技術(Chip-to-Chip，COC)及晶片/晶圓接合技術(Chip-to-Wafer，COW)以解決此問題，如何在COC及COW製程技術上大量的組裝並堆疊KGDs，確認接點良率及降低成本將是考慮的因素。
在目前3D晶片整合技術中，目前堆疊技術朝向10微米(Micrometer，μm)級的間距(Pitch)，以及50微米(μm)厚度以下等級的薄型晶片，為了提高產能與良率，接合技術亦由晶片/晶片接合技術(COC)逐漸轉向晶片/晶圓接合(COW)構裝技術，唯如何提高接合良率及降低成本的結構仍屬重要議題。
如圖1所示，為習知一種使用底膠填充的晶片/晶圓接合(COW)構裝技術的結構示意圖。晶圓120位於載體(Carrier)100上，並具有一緩衝層110位於其間。而多個具有堆疊的晶片結構112包含三層晶片130、140與150堆疊，並與晶圓120透過銅凸塊(Cu Bump)或是銅/錫銀微凸塊(Cu/SnAg Micro Bump)電性接合。而後進行底膠(Underfill)填充和模封(Molding)製程，完成底膠(Underfill)層160與模封(Molding)層170。由於堆疊技術朝向10微米(μm)級的間距(Pitch)以及50微米(μm)厚度以下等級的薄型晶片，造成在進行底膠填充後，會產生溢膠的問題，影響晶片/晶圓接合(COW)構裝技術的良率。
由於必須採用堆疊(Stacking)、填充底膠以及模封(Molding)三個步驟，在製程上需要花費較多的時間，增加製造的成本。而底膠填充和模封製程需要使用不同的材料，也使成本上增加。另外，由於採用這樣堆疊的晶片結構，是透過金屬熔接(Metal Joint)以電性連接，在熱膨脹的不一致(Thermal Expansion Mismatch)，也會造成良率上的問題。
如圖2所示，為習知另一種使用非流動性底膠(Non-flow Underfill，NFU)製程的晶片/晶圓接合(COW)構裝技術的結構示意圖。晶圓220位於載體(Carrier)200上，並具有一緩衝層210位於其間。多個具有堆疊的晶片結構222包含三層晶片230、240與250。此三層晶片230、240與250在完成堆疊結構之前，預先黏貼一層非流動性底膠(NFU)232、242、252，並與晶圓220透過銅凸塊(Cu Bump)或是銅/錫銀微凸塊(Cu/SnAg Micro Bump)電性接合。而後進行模封(Molding)製程，完成模封(Molding)層270。
由於必須採用NFU製程在晶片上黏貼NFU材料，而後進行堆疊(Stacking)以及模封(Molding)等三個步驟，在製程上需要花費較多的時間，增加製造的成本。而非流動性底膠(NFU)的黏貼與模封製程需要使用不同的材料，也使成本上增加。另外，由於採用這樣堆疊的晶片結構，是透過金屬熔接(Metal Joint)以電性連接，在熱膨脹的不一致，也會造成良率上的問題。
本發明提供一種晶圓級模封接合結構及其製造方法。
在一實施例中，提出一種模封接合結構，包含一第一晶片、一第二晶片、多個貫穿電極以及一黏著材料。此第一晶片包含一第一晶背、一第一晶面和多個第一晶側，而該第一晶面上有多個第一晶面凸塊。第二晶片包含第二晶背及第二晶面，其中該第二晶背上包含多個第二晶背凸塊，該第二晶面上包含多個第二晶面凸塊。該些貫穿電極位於該第二晶片中，分別電性導通該第二晶背凸塊和該第二晶面凸塊。該黏著材料置於第一晶片和第二晶片之間，且完全包覆第一晶片之第一晶側。
在一實施例中，提出一種晶圓級晶片之封裝方法，包含提供一基板，包含一主動面，其中一第一圖案化導電層位於主動面。將基板之主動面覆蓋一第一黏著層。提供第一晶片，包含一第一表面與一第二表面，其中一第二圖案化導電層位於第一表面。將一緩衝材料層附著於第一晶片，其中第一晶片之第二表面與緩衝材料層接合。將附著有緩衝材料層之第一晶片連接至基板，使第一晶片之第二圖案化導電層與基板之第一圖案化導電層電性連接。使用附著有緩衝材料層之第一晶片與基板進行一第一壓合過程，其中緩衝材料層之面積大於第一晶片之第二表面之面積。第一黏著層完全包覆第一晶片之晶側。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
為解決晶片/晶圓接合技術(COW)堆疊架構時，底膠(Underfill)填充和模封(Molding)所遭遇的困難，本案提出一創新解決方案，同時完成細間距底膠填充和晶圓級模封。
如圖3A所示，為本揭露內容所提出晶圓級的模封接合結構，在多個實施例其中的一個結構示意圖。晶圓310位於載體(Carrier)300上，並具有一緩衝層302位於其間。晶圓級模封接合結構304位於晶圓310上，在此實施例中包含三層晶片320、330與340。在此實施例中以三層結構說明，但並非以此為限制。而晶片320、330、340的厚度，在一實施例中，可以小於或等於100微米(um)而大於5微米。
晶圓310包含晶背及晶面，其上面分別包含多個晶背凸塊和晶面凸塊，如圖所示的晶背凸塊316和晶面凸塊312，而更包含多個貫穿電極，分別電性導通所述的晶背凸塊和晶面凸塊，如圖所示的貫穿電極314。
晶片320、330與340則分別包含晶背、晶面和多個晶側，晶面與晶背分別具有多個晶面凸塊，在一選擇實施例中，還包含晶背凸塊以及電性連接所述凸塊的貫穿電極。例如如圖所示，晶片320表面包含晶面凸塊322、貫穿電極324與晶背凸塊326，晶片330表面包含晶面凸塊332、貫穿電極334與晶背凸塊336，晶片340表面上包含晶面凸塊342。上述的凸塊可以為銅凸塊(Cu Bump)或是銅/錫銀微凸塊(Cu/SnAg Micro Bump)等等結構。
黏著材料350可為高分子膠材，其中包含多個導電顆粒351及/或多個非導電顆粒353，置於晶圓310與晶片320、330與340之間，並同時完全包覆這些晶片320、330與340的晶側。當黏著材料350包含導電顆粒353時，晶面凸塊322、332、342透過導電顆粒353分別電性連接至晶背凸塊316、326、336。當黏著材料350無包含導電顆粒353時，晶面凸塊322、332、342分別以接觸方式電性連接至晶背凸塊316、326、336。包含導電顆粒353之黏著材料350可以為異方性導電膠(Anisotropic Conductive Adhesive，ACA)，不包含導電顆粒353之黏著材料350可以為非導電膠(Non-conductive Adhesive，NCA)。
在整個模封接合結構304中，堆疊結構中的最上層，例如晶片340，其晶片的晶背表面是可以裸露，而整個模封接合結構304中，晶片340的晶背表面與黏著材料350的表面是可以實質上等高，而形成此模封接合結構304的模封結構。
圖3B是說明本揭露內容所提出晶圓級的模封接合結構製程示意圖，以形成例如圖3A的模封接合結構。
首先，提供一晶圓310，此晶圓310包含晶面311與晶背313，而在晶面311與晶背313上分別包含多個晶背凸塊和晶面凸塊，如圖所示的晶背凸塊312、322、332、342和晶面凸塊316、326、336。而在晶圓310內包含多個貫穿電極，如圖所示的貫穿電極314，用以電性導通所述的晶背凸塊316與晶面凸塊312。而在晶圓310的晶背313表面上，塗上一層黏著材料352。此黏著材料352包含多個導電顆粒351及非導電顆粒353。值得注意的是，以下實施例雖以包含導電顆粒351之黏著材料352為例示，但實際之接合方式，亦可使用如前段所述之方法，故並不以此為限。
而後，提供欲形成晶片/晶圓接合(COW)堆疊架構的多個晶片，例如圖中標示的晶片320、330與340。在此實施例中僅說明部分晶片，但在整個晶圓上，可在同一層包含多個晶片以形成堆疊架構，在此不再說明。
晶片320包含晶面321、晶背323和多個晶側325。在晶面321上具有多個凸塊，例如圖示的晶面凸塊322，而在晶背323上也可選擇性地具有多個凸塊，例如圖示的晶背凸塊326。而晶片320的部分的晶面凸塊與晶背凸塊之間，具有貫穿電極用以電性連接，例如圖示的晶面凸塊322與晶背凸塊326，包含一貫穿電極324做電性連接。
而在整個晶圓級接合堆疊架構中，與晶片320同一層的晶背表面上，塗上一層黏著材料354，例如進行晶圓級的異方性導電膠貼合(Wafer level ACA Lamination)。
而晶片330包含晶面331、晶背333和多個晶側335。在晶面331上具有多個凸塊，例如圖示的晶面凸塊332，而在晶背333上也可選擇性地具有多個凸塊，例如圖示的晶背凸塊336。而晶片330的部分的晶面凸塊與晶背凸塊之間，具有貫穿電極用以電性連接，例如圖示的晶面凸塊332與晶背凸塊336，包含一貫穿電極334做電性連接。而在整個晶圓級接合堆疊架構中，與晶片330同一層的晶背表面上，塗上一層黏著材料356，例如異方性導電膠(ACA)。
而晶片/晶圓接合(COW)堆疊架構的最上層，例如是晶片340，包含晶面341、晶背343和多個晶側345。在晶面341上具有多個凸塊，例如圖示的晶面凸塊342。
對準上述晶片320、330與340和晶圓310進行堆疊接合。並藉由黏著材料，例如異方性導電膠，接合上述晶片320、330與340及晶圓310，達成電性導通上述晶面凸塊與晶背凸塊，並同時完全包覆之上述晶片320、330與340的晶側325、335與345。
圖3B所提出晶圓級的模封接合模封接合結構製程，例如以晶片320與晶圓310分別為第一晶片以及第二晶片為例說明。此第一晶片(晶片320)，包含第一晶背(晶背凸塊326)、第一晶面(晶面321)和多個第一晶側(晶側325)，此第一晶面上有多個電極(晶面凸塊322)。而第二晶片(例如晶圓310)，包含第二晶背(晶背313)及第二晶面(晶面311)，其中此第二晶背上包含多個晶背凸塊(晶背凸塊316)，此第二晶面上包含多個晶面凸塊(晶面凸塊312)。而多個貫穿電極(如貫穿電極314)，位於第二晶片中，分別電性導通上述的晶背凸塊和晶面凸塊。而黏著材料(黏著材料350)，置於第一晶片和第二晶片之間，且完全包覆第一晶片之第一晶側。
圖3B所說明的晶圓級模封接合結構製程示意圖，僅需經由晶圓級的異方性導電膠貼合(Wafer level ACA Lamination)與堆疊(Stacking)兩個步驟，在製程上相較於傳統需採用如圖1的堆疊、填充底膠以及模封三個步驟，或是如圖2的黏貼NFU材料、堆疊以及模封三個步驟，在製程上需要花費較少的時間，可以有效降低製造的成本。而對於底膠填充和模封製程，只需使用相同，可使成本降低。另外，由於採用這樣堆疊的晶片結構，是透過異方性導電膠(ACA)的導電顆粒電性連接，因此，在面對熱膨脹的不一致(Thermal Expansion Mismatch)的情況，也不會造成影響良率的問題。
本揭露內容所提出晶圓級的模封接合結構，可運用在多個實施例中，其中一部份實施例的晶片堆疊結構，則如圖4A～4G的實施例所示。
如圖4A所示，本揭露內容提出一種晶圓級的模封接合結構，包含至少上晶片410與下晶片420A堆疊電性連接。上晶片410與下晶片420A的厚度，在一實施例中，可以小於100微米(um)而大於5微米。
上晶片410包含基底層412與圖案化導電層414，此圖案化導電層414為進行後段製程(Back-end-of-line，BEOL)時，已經形成於基底層412上的各種元件佈局，而晶面上具有多個電極418。貫穿電極416則是形成於上晶片410內，並連接到電極418。
下晶片420A包含晶面與晶背，在晶面上有多個晶面凸塊425。而此實施例中，下晶片420的晶背上，加上一絕緣層422，例如一介電層(Dielectric layer)。而在絕緣層422上，則可形成多個電鍍金屬凸塊(Electroplating Metal Bump)421A。而多個貫穿電極423，則是分別電性導通上述晶面凸塊425與電鍍金屬凸塊421A。
圖4B則是本揭露內容提出一種晶圓級的模封接合結構之另一實施例。與圖4A相同部分則不再冗述，而差異則是在於下晶片420A晶背的絕緣層422上，形成多個無電鍍金屬凸塊(Electroless Metal Bump)421B。而後在絕緣層422上形成晶圓級的異方性導電膠(ACA)428。經由異方性導電膠的接合(ACA Joint)，上晶片410的電極418可與下晶片420B的無電鍍金屬凸塊421B堆疊而電性連接。
圖4C則是本揭露內容提出一種晶圓級的模封接合結構之另一實施例。與圖4A相同部分則不再冗述，而差異則是在於下晶片420C晶背的絕緣層422上，形成多個晶背金屬薄膜(Back side Metal Thin Film)421C。而後在絕緣層422上形成晶圓級的異方性導電膠(ACA)428。經由異方性導電膠的接合(ACA Joint)，上晶片410的電極418可與下晶片420C的晶背金屬薄膜421C堆疊而電性連接。
圖4D則是本揭露內容提出一種晶圓級的模封接合結構之另一實施例。與圖4A相同部分則不再冗述，而差異則是在於下晶片420D晶背的絕緣層422上，形成重佈局層(Redistribution Layer，RDL)421D。此重佈局層(RDL)421D例如包含鋁(Al)、銅或其合金材質。而後在絕緣層422上形成晶圓級的異方性導電膠(ACA)428。經由異方性導電膠的接合(ACA Joint)，上晶片410的電極418可與下晶片420D的重佈局層(RDL)421D堆疊而電性連接。此架構可減少對準的問題。
圖4E則是本揭露內容提出一種晶圓級的模封接合結構之另一實施例。與圖4A相同部分則不再冗述。此實施例適用於矽晶片穿孔內部互連(through-silicon-via，TSV)的結構。而與圖4A差異則是在於下晶片420E晶背上，直接利用矽晶片穿孔內部互連(TSV)423與異方性導電膠(ACA)428，與上晶片410的電極418進行電性連接。
圖4F則是本揭露內容提出一種晶圓級的模封接合結構之另一實施例。與圖4A相同部分則不再冗述，而差異則是在於上晶片410晶面的柱狀電極418F。而下晶片420F晶背的絕緣層422上，形成多個晶背金屬薄膜洞(Back side Metal Thin Film Cavity)429。而後在絕緣層422上形成晶圓級的異方性導電膠(ACA)428。經由異方性導電膠的接合(ACA Joint)，上晶片410的柱狀電極418F可透過在下晶片420B的晶背金屬薄膜洞429內的異方性導電膠(ACA)428導體，與下晶片420F的貫穿電極423，或是矽晶片穿孔內部互連(TSV)堆疊而電性連接。
圖4G則是本揭露內容提出一種晶圓級的模封接合結構之另一實施例，與圖4E具有類似的結構。與圖4A相同部分則不再冗述。此實施例適用於矽晶片穿孔內部互連(TSV)的結構。而與圖4A差異則是在於下晶片420E晶背上，直接利用矽晶片穿孔內部互連(TSV)423與異方性導電膠(ACA)428，與上晶片410的電極418進行電性連接。而與圖4E的差異在於，在下晶片420E晶背上具有多個凹槽427，可防止接合結構滑移的情況。
圖5是說明本揭露內容所提出晶圓級的模封接合結構製程示意圖。
首先，提供一晶圓510，此晶圓510包含晶面與晶背，並在晶圓510的晶背表面上，形成一層黏著材料520，例如異方性導電膠(ACA)。此黏著材料520包含多個導電顆粒及高分子膠材。而形成方式可以為黏貼或是塗上等方式。
而後，進行晶片/晶圓接合(COW)堆疊的製程，經過預先凸塊形成製程(Pre-bond process)在晶片的晶面及/或晶背上形成多個凸塊。並接著在晶片上形成黏著材料，例如進行晶圓級的異方性導電膠貼合(Wafer level ACA Lamination)，而形成多個晶片堆疊結構530。而後，對整個晶圓進行接合的製程，並隨後使用切割滾輪540進行切割製程(Dicing Process)，形成多個模封接合結構550。
在本揭露所提出一種晶圓級的模封接合結構的其中一個實施例的接合架構，不但可達成高密度的電極接合，降低製程溫度的接合界面溫度可低於或等於200攝氏溫度(200℃)，但最好大於80° C，並且能縮短製程的時間到可小於或等於2秒，但最好大於0.5秒鐘，並同步完成晶圓級模封架構。
本揭露內容提出一種晶圓級模封接合結構的製程方法，可有效的降低製程步驟、降低成本(點膠和模封一步完成)，並藉由導電顆粒或非導電顆粒填充於模封材料間以降低其熱阻，以增加晶圓級模封架構的可靠性。
本揭露內容提出一種晶圓級模封接合結構，在一實施例中，可對晶圓級模封架構進行延伸，因此，運用不同晶片堆疊之架構亦屬本揭露內容所屬之範疇。
請參照圖6a~6e，是說明本揭露內容所提出晶圓級模封接合結構的製程方法中，晶片貼合的方法實施例流程圖。請參照圖6a，提供一基板610，包含一主動面612，其中一第一圖案化導電層620位於此主動面612上。將此基板610之主動面612覆蓋一第一黏著層630。
而後如圖6b，提供一第一晶片640，包含一第一表面642與一第二表面644，其中一第二圖案化導電層640位於第一表面642。並接著提供一緩衝材料層660，而將緩衝材料層660附著於第一晶片640，其中第一晶片640之第二表面644與此緩衝材料層660接合。上述緩衝材料層660之面積大於第一晶片640之第二表面644面積，而緩衝材料層660例如為矽膠(silicon rubber)。第一晶片640的厚度小於100 μm，在一實施例中，為50微米(μm)等級的薄型晶片。
接著如圖6c，將附著有緩衝材料層660之第一晶片640連接至基板610，使第一晶片640之第二圖案化導電層650與基板610之第一圖案化導電層620電性連接。使用附著有緩衝材料層660之第一晶片640與基板610進行一第一壓合過程。此第一壓合過程之時間長度可小於或等於10秒鐘，最好大於0.5秒鐘，而操作的接合界面溫度可低於或等於200° C，但最好大於80° C。
上述基板610之第一圖案化導電層620與第一晶片640之第二圖案化導電層650的接合，在一選擇實施例中，可以透過例如金屬熔接(metal joint)以電性連接。在另一選擇實施例中，第一黏著層630更包含多個導電微粒，第一晶片640之第二圖案化導電層650透過這些導電微粒以電性連接至基板610之第一圖案化導電層620。在經過壓合過程後，如圖6d所示，第一黏著層630相對於基板610之主動面612的表面632，其相對於基板610的主動面612的垂直高度，實質上等於第一晶片640之第二表面644相對於基板610之主動面612的垂直高度。在移除緩衝材料層660後，第一晶片640的第二表面644與第一黏著層630與第二表面實值上等高的暴露平面632上，可形成一保護層670。
請參照圖7a~7e，是說明本揭露內容所提出晶圓級模封接合結構的製程方法中，晶片貼合方法另一實施例流程圖。請參照圖7a，提供一基板710，包含一主動面712，其中一第一圖案化導電層720位於此主動面712上。將此基板710之主動面712覆蓋一第一黏著層730，其中黏著層730更包含多個導電微粒732。
而後如圖7b，提供一第一晶片740，包含一第一表面742與一第二表面744，其中一第二圖案化導電層750位於第一表面742。並接著提供一緩衝材料層760，而將緩衝材料層760附著於第一晶片740，其中第一晶片740之第二表面744與此緩衝材料層760接合。上述緩衝材料層760之面積大於第一晶片740之第二表面744面積，而緩衝材料層760例如為矽膠(silicon rubber)。第一晶片740的厚度小於100 μm，在一實施例中，為50微米(μm)等級的薄型晶片。
接著如圖7c，將附著有緩衝材料層760之第一晶片740連接至基板710，使第一晶片740之第二圖案化導電層750與基板710之第一圖案化導電層720電性連接。使用附著有緩衝材料層760之第一晶片740與基板710進行一第一壓合過程。此第一壓合過程之時間長度可小於或等於10秒鐘，最好大於0.5秒鐘，而操作的接合界面溫度可低於或等於200° C，但最好大於80° C。
上述基板710之第一圖案化導電層720與第一晶片740之第二圖案化導電層750的接合，在此實施例中，第一晶片740之第二圖案化導電層750透過這些導電微粒732以電性連接至基板710之第一圖案化導電層720。在經過壓合過程後，如圖7d所示，第一黏著層730相對於基板710之主動面712的表面732，其相對於基板710的主動面712的垂直高度，實質上等於第一晶片740之第二表面744相對於基板710之主動面712的垂直高度。如圖7e所示，在移除緩衝材料層760後，第一晶片740的第二表面744與第一黏著層730與第二表面實值上等高的暴露平面732上，可形成一保護層770。
請參照圖8a~8e，是說明本揭露內容所提出晶圓級模封接合結構的製程方法另一實施例流程圖。請參照圖8a，提供一基板810，包含一主動面812，其中一第一圖案化導電層820位於此主動面812上。將此基板810之主動面812覆蓋一第一黏著層831。第一黏著層831的材料可以為異方性導電膠(Anisotropic Conductive Adhesive，ACA)，或是由高分子膠材所組成，包含例如多個導電顆粒及/或多個非導電顆粒。藉由導電顆粒或非導電顆粒填充於模封材料間以降低其熱阻，以增加晶圓級模封架構的可靠性。
而後如圖8b，提供一第一晶片840，包含一第一表面842與一第二表面844，其中第一晶片840包含在第一表面842包含多個凸塊852，在第二表面844包含多個凸塊856，而每個凸塊852與對應的凸塊856之間包含一內連線結構854。此內連線結構854為矽晶片穿孔內部互連(through-silicon-via，TSV)結構。而凸塊852與凸塊856可為金屬或導電材料。
接著提供一緩衝材料層860，而將緩衝材料層860附著於第一晶片840，其中第一晶片840之第二表面844與此緩衝材料層860接合。上述緩衝材料層860之面積大於第一晶片840之第二表面844面積，而緩衝材料層860例如為矽膠(silicon rubber)。第一晶片840的厚度小於100 μm，在一實施例中，為50微米(μm)等級的薄型晶片。
接著如圖8c，將附著有緩衝材料層860之第一晶片840連接至基板810，使第一晶片840的凸塊852與基板810之第一圖案化導電層820電性連接。使用附著有緩衝材料層860之第一晶片840與基板810進行一第一壓合過程。此第一壓合過程之時間長度可小於或等於10秒鐘，最好大於0.5秒鐘，而操作的接合界面溫度可低於或等於200° C，但最好大於80° C。
上述基板810之第一圖案化導電層820與第一晶片840的凸塊852接合，在一選擇實施例中，可以透過例如金屬熔接(metal joint)以電性連接。在另一選擇實施例中，第一黏著層831更包含多個導電微粒，第一晶片840之第二圖案化導電層850透過這些導電微粒以電性連接至基板810之第一圖案化導電層820。在經過壓合過程後，如圖8d所示，第一黏著層831相對於基板810之主動面812的表面832，其相對於基板810的主動面812的垂直高度，實質上等於第一晶片840之第二表面844相對於基板810之主動面812的垂直高度。
如圖8d所示，在移除緩衝材料層860後，將第一晶片840之第二表面844上，以及第一黏著層831的表面832上，覆蓋一第二黏著層833。而後提供一第二晶片870，包含一第三表面872與一第四表面874，其中在第三表面872包含例如第二圖案化導電層880。接著提供如前述的緩衝材料層860附著於第二晶片870，並與第二晶片之的第四表面874接合。
接著如圖8e，將附著有緩衝材料層860之第二晶片870連接至第一晶片840的第二表面844，使第二晶片870之第二圖案化導電層880與第一晶片840的第二表面844上的凸塊856電性連接。使用附著有緩衝材料層860之第二晶片870與第一晶片840進行一第二壓合過程。此第二壓合過程之時間長度小於10秒鐘，而操作的接合界面溫度低於200° C。
上述第一晶片840的凸塊856與第二晶片870之第二圖案化導電層880的接合，在一選擇實施例中，可以透過例如金屬熔接(metal joint)以電性連接。在另一選擇實施例中，第二黏著層833更包含多個導電微粒，第二晶片870之第二圖案化導電層88透過這些導電微粒，電性連接至第一晶片840的凸塊856。
在經過壓合過程後，如圖8f所示，第二黏著層833暴露的表面834，其相對於第一晶片840的第二表面844的垂直高度，實質上等於第二晶片870之第二表面874相對於第一晶片840的第二表面844的垂直高度。在移除緩衝材料層860後，第二晶片870的第二表面874上，可形成一保護層，或是採用前述的方法，堆疊第三晶片等等。而此時，第二晶片870亦可為具有矽晶片穿孔內部互連(through-silicon-via，TSV)結構的晶片。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．載體(Carrier)
110．．．緩衝層
112．．．晶片堆疊結構
120．．．晶圓
130、140與150．．．晶片
160．．．底膠(Underfill)層
170．．．模封(Molding)層
200．．．載體(Carrier)
210．．．緩衝層
220．．．晶圓
222．．．堆疊的晶片結構
230、240與250．．．晶片
232、242、252．．．非流動性底膠(NFU)
270．．．模封(Molding)層
300．．．載體(Carrier)
302．．．緩衝層
304．．．晶圓級模封接合結構
310．．．晶圓
312．．．晶面凸塊
316．．．晶背凸塊
320、330與340．．．晶片
322、332、342．．．晶面凸塊
324、334、344．．．貫穿電極
326、336、346．．．晶背凸塊
350．．．黏著材料
351．．．導電顆粒
353．．．非導電顆粒
321、331、341．．．晶面
323、333、343．．．晶背
325、335、345．．．晶側
410．．．上晶片
420A～420G．．．下晶片
412．．．基底層
414．．．圖案化導電層
418．．．電極
418F．．．柱狀電極
416．．．貫穿電極
422．．．絕緣層
421A．．．電鍍金屬凸塊(Electroplating Metal Bump)
421B．．．無電鍍金屬凸塊(Electroless Metal Bump)
421C．．．晶背金屬薄膜(Back side Metal Thin Film)
421D．．．重佈局層(Redistribution Layer，RDL)
423．．．貫穿電極
425．．．晶面凸塊
428．．．異方性導電膠(ACA)
429．．．晶背金屬薄膜洞(Back side Metal Thin Film Cavity)
427．．．凹槽
510．．．晶圓
520．．．黏著材料
530．．．晶片堆疊結構
540．．．切割滾輪
550．．．模封接合結構
610．．．基板
612．．．主動面
620．．．第一圖案化導電層
630．．．第一黏著層630
640．．．第一晶片
642．．．第一表面
644．．．第二表面
660．．．緩衝材料層
670．．．保護層
710．．．基板
712．．．主動面
720．．．第一圖案化導電層
730．．．第一黏著層
732．．．導電微粒
740．．．第一晶片
742．．．第一表面
744．．．第二表面
750．．．第二圖案化導電層
760．．．緩衝材料層760
770．．．保護層
810．．．基板
812．．．主動面
820．．．第一圖案化導電層
831、833．．．黏著層
840．．．第一晶片
842．．．第一表面
844．．．第二表面
852、856．．．凸塊
854．．．內連線結構
860．．．緩衝材料層
870．．．第二晶片
872．．．第三表面
874．．．第四表面
880．．．第二圖案化導電層
圖1是說明習知一種使用底膠填充的晶片/晶圓接合(COW)構裝技術的結構示意圖。
圖2是說明習知另一種使用非流動性底膠(Non-flow Underfill，NFU)製程的晶片/晶圓接合(COW)構裝技術的結構示意圖。
圖3A是說明本揭露內容所提出晶圓級的模封接合結構，在多個實施例其中的一個結構示意圖。
圖3B是說明本揭露內容所提出晶圓級的模封接合結構製程示意圖，以形成例如圖3A的模封接合結構。
圖4A～4G是說明本揭露內容所提出晶圓級的模封接合結構不同實施例示意圖。
圖5是說明本揭露內容所提出晶圓級的模封接合結構製程示意圖。
圖6a~6e是說明本揭露內容所提出晶圓級模封接合結構的製程方法其中一實施例流程圖。
圖7a~7e是說明本揭露內容所提出晶圓級模封接合結構的製程方法其中另一實施例流程圖。
圖8a~8f是說明本揭露內容所提出晶圓級模封接合結構的製程方法其中另一實施例流程圖。
300．．．載體(Carrier)
302．．．緩衝層
304．．．晶圓級模封接合結構
310．．．晶圓
312．．．晶面凸塊
316．．．晶背凸塊
320、330與340．．．晶片
322、332、342．．．晶面凸塊
324、334．．．貫穿電極
326、336．．．晶背凸塊
351．．．導電顆粒
353．．．非導電顆粒

Claims (40)

  1. 一種模封接合結構，包含：一第一晶片，包含一第一晶背、一第一晶面和多個第一晶側，該第一晶面上有多個第一晶面凸塊；一第二晶片，包含一第二晶背及一第二晶面，其中該第二晶背上包含多個第二晶背凸塊，該第二晶面上包含多個第二晶面凸塊；多個貫穿電極，位於該第二晶片中，分別電性導通該些第二晶背凸塊和該些第一晶面凸塊；以及一黏著材料，置於該第一晶片和該第二晶片之間，並同時完全包覆該第一晶片之該些第一晶側，且該黏著材料包括多個導電顆粒；其中該第一晶片中之該第一晶面凸塊電性連接至該第二晶片中之該第二晶背凸塊。
  2. 如申請專利範圍第1項所述之模封接合結構，其中該第一晶片更包含多個第二貫穿電極，該第一晶背更包含多個第一晶背凸塊，該些第二貫穿電極位於該第一晶片中，分別電性導通該些第一晶面凸塊與該些第一晶背凸塊。
  3. 如申請專利範圍第1項所述之模封接合結構，其中該些晶面凸塊與晶背凸塊為電鍍金屬或無電鍍金屬其中之一。
  4. 如申請專利範圍第1項所述之模封接合結構，其中在該些第一晶背凸塊與該第二晶片之第二晶面之間更包含一絕緣層(dielectric layer)。
  5. 如申請專利範圍第1項所述之模封接合結構，其中該黏著材料在該些晶側具有相同厚度。
  6. 如申請專利範圍第1項所述之模封接合結構，其中該第一晶片厚度小於或等於100微米(um)但大於5微米。
  7. 如申請專利範圍第1項所述之模封接合結構，其中該第一晶片之第一晶面凸塊透過該些導電顆粒電性連接至該第二晶片之該第二晶背凸塊。
  8. 如申請專利範圍第7項所述之模封接合結構，其中該黏著材料中更包含高分子膠材，且該高分子膠材中包含多個非導電顆粒。
  9. 一種晶圓級模封接合結構，包含：一晶圓，包含一第一晶背及一第一晶面，其中該第一晶背上包含多個晶背凸塊，該第一晶面上包含多個晶面凸塊，該晶圓更包含多個第一貫穿電極，分別電性導通該些晶背凸塊和該些晶面凸塊；以及多個堆疊結構，其中每一該堆疊結構包含一第一晶片，包含一第二晶背、第二晶面和多個第二晶側，該第二晶面上有多個第一電極；以及一黏著材料，置於該第一晶片和該晶圓之間，並同時完全包覆該第一晶片之該些第一晶側，且該黏著材料包括多個導電顆粒。
  10. 如申請專利範圍第9項所述之晶圓級模封接合結構，中該第一晶片更包含多個第二貫穿電極，位於該第一 晶片中，分別電性導通該些第一電極。
  11. 如申請專利範圍第10項所述之晶圓級模封接合結構，其中該第一晶片之第二晶背更包含多個晶背電極，以電性導通該些第二貫穿電極。
  12. 如申請專利範圍第11項所述之晶圓級模封接合結構，其中每一該堆疊結構更包含一第二晶片，該第二晶片包含一第三晶背、第三晶面和多個第三晶側，該第三晶面上有多個第二電極，其中，該些第二電極電性連接至該第一晶片的該些晶背電極，且該黏著材料完全包覆該第二晶片之該些第三晶側。
  13. 如申請專利範圍第9項所述之晶圓級模封接合結構，其中該些晶面凸塊為電鍍金屬或無電鍍金屬其中之一。
  14. 如申請專利範圍第9項所述之晶圓級模封接合結構，其中在該些晶背凸塊與該第一晶片的該第二晶背之間更包含一絕緣層(dielectric layer)。
  15. 如申請專利範圍第9項所述之晶圓級模封接合結構，其中該黏著材料在該些晶側具有相同厚度。
  16. 如申請專利範圍第9項所述之晶圓級模封接合結構，其中該晶圓之晶背凸塊透過該些導電顆粒電性連接至該第一晶片之該第一電極。
  17. 如申請專利範圍第16項所述之晶圓級模封接合結構，其中該黏著材料包含高分子膠材，且該高分子膠材包含多個非導電顆粒。
  18. 一種晶圓級晶片之封裝方法，包含： 提供一基板，包含一主動面，其中一第一圖案化導電層位於該主動面；將該基板之該主動面覆蓋一第一黏著層；提供一第一晶片，包含一第一表面與一第二表面，其中一第二圖案化導電層位於該第一表面；提供一緩衝材料層；將該緩衝材料層附著於該第一晶片，其中該第一晶片之該第二表面與該緩衝材料層接合；將附著有該緩衝材料層之該第一晶片連接至該基板，使該第一晶片之該第二圖案化導電層與該基板之該第一圖案化導電層電性連接；以及使用附著有該緩衝材料層之該第一晶片與該基板進行一第一壓合過程，其中該緩衝材料層之面積大於該第一晶片之該第二表面之面積。
  19. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該第一黏著層相對於該基板之該主動面之垂直高度等於該第一晶片之該第二表面相對於該基板之該主動面之垂直高度。
  20. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該緩衝材料層為矽膠(silicon rubber)。
  21. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該第一晶片之該第二圖案化導電層與該基板之該第一圖案化導電層透過金屬熔接(metal joint)以電性連接。
  22. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該第一黏著層中更包含複數個導電微粒，該第一晶片之該第二圖案化導電層透過該複數個導電微粒以電性連接至該基板之該第一圖案化導電層。
  23. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該第一晶片之厚度小於或等於100微米(μm)但大於5微米。
  24. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該第一壓合過程之時間長度小於或等於10秒鐘，但大於0.5秒鐘。
  25. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該第一壓合過程之接合界面溫度低於或等於200℃，但大於80℃。
  26. 如申請專利範圍第18項所述之晶圓級晶片之封裝方法，其中該第一晶片更包含一內連線結構與一第三圖案化導電層；其中該第三圖案化導電層位於該第二表面，該第三圖案化導電層透過該內連線結構以電性連接至該該第一表面之該第二圖案化導電層。
  27. 如申請專利範圍第26項所述之晶圓級晶片之封裝方法，其中該內連線結構為直通矽晶穿孔(Through-Silicon Via)。
  28. 如申請專利範圍第26項所述之晶圓級晶片之封裝方法，在該第一壓合過程後更包含：移除該緩衝材料層； 將該第一晶片之該第二表面覆蓋一第二黏著層；提供一第二晶片，包含一第三表面與一第四表面，其中一第四圖案化導電層位於該第三表面；將該緩衝材料層附著於該第二晶片，其中該第二晶片之該第四表面與該緩衝材料層接合；將附著有該緩衝材料層之該第二晶片連接至該第一晶片，使該第二晶片之該第四圖案化導電層與該第一晶片之該第三圖案化導電層電性連接；以及使用附著有緩衝材料層之該第二晶片與該基板進行一第二壓合過程。
  29. 如申請專利範圍第28項所述之晶圓級晶片之封裝方法，其中該第二黏著層與該第一黏著層材料相同。
  30. 如申請專利範圍第28項所述之晶圓級晶片之封裝方法，其中該第一壓合過程之時間長度小於2秒鐘；其中該第二壓合過程之時間長度小於10秒鐘。
  31. 如申請專利範圍第28項所述之晶圓級晶片之封裝方法，其中該第二壓合過程之接合界面溫度低於或等於200℃，但大於80℃。
  32. 一種晶圓級晶片之封裝結構，包含：一基板，包含一主動面，其中一第一圖案化導電層位於該主動面；一第一晶片，連接至該基板，包含一第一表面與一第二表面，其中該第一表面相鄰於該主動面，其中一第二圖案化導電層位於該第一表面，且該第二圖案化導電層電性 連接至該基板之該第一圖案化導電層；以及一第一黏著層，填充於該第一晶片與該基板之間，並覆蓋該基板之該主動面、以及該第一晶片除該第二表面外之所有表面；其中該第一黏著層相對於該基板之該主動面之垂直高度等於該第一晶片之該第二表面相對於該基板之該主動面之垂直高度。
  33. 如申請專利範圍第32項所述之晶圓級晶片之封裝結構，其中該第一晶片之該第二圖案化導電層與該基板之該第一圖案化導電層透過金屬熔接(metal joint)以電性連接。
  34. 如申請專利範圍第32項所述之晶圓級晶片之封裝結構，其中該第一黏著層中更包含複數個導電微粒，該第一晶片之該第二圖案化導電層透過該複數個導電微粒電性連接至該基板之該第一圖案化導電層。
  35. 如申請專利範圍第32項所述之晶圓級晶片之封裝結構，其中該第一晶片之厚度小於或等於100微米(μm)，μm但大於5微米。
  36. 如申請專利範圍第32項所述之晶圓級晶片之封裝結構，其中該第一晶片更包含一內連線結構與一第三圖案化導電層；其中該第三圖案化導電層位於該第四表面，該第三圖案化導電層透過該內連線結構電性連接至該第一表面之該第二圖案化導電層。
  37. 申請專利範圍第36項所述之晶圓級晶片之封裝結 構，其中該內連線結構為直通矽晶穿孔(Through-Silicon Via)。
  38. 如申請專利範圍第36項所述之晶圓級晶片之封裝結構，其中更包含一第二晶片，連接至該第一晶片，包含一第三表面與一第四表面，其中該第三表面接鄰於該第一晶片之該第二表面；其中更包含一第四圖案化導電層位於該第三表面，該第四圖案化導電層電性連接至該第一晶片之該第三圖案化導電層。
  39. 如申請專利範圍第36項所述之晶圓級晶片之封裝結構，其中更包含一第二黏著層，充填於該第一晶片與該第二晶片之間，且該第二黏著層相對於該基板之垂直高度等於該第二晶片之該第四表面相對於該基板之該主動面之垂直高度；其中該第二黏著層覆蓋該第一晶片除該第二表面外之所有表面。
  40. 如申請專利範圍第39項所述之晶圓級晶片之封裝結構，其中該第二黏著層與該第一黏著層材料相同。
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