TWI415244B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI415244B
TWI415244B TW099131598A TW99131598A TWI415244B TW I415244 B TWI415244 B TW I415244B TW 099131598 A TW099131598 A TW 099131598A TW 99131598 A TW99131598 A TW 99131598A TW I415244 B TWI415244 B TW I415244B
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wafer
substrate
interposer
recess
semiconductor device
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TW201130102A (en
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Shin Puu Jeng
Kim Hong Chen
Shang Yun Hou
Chao Wen Shih
Cheng Chieh Hsieh
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置，特別是有關於一種使用轉接板(interposer)的三維半導體封裝。
自積體電路的發明創造以來，由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續的改進，使半導體業持續不斷的快速成長發展。主要來說，集積度的改進來自於最小特徵尺寸(minimum feature size)不斷縮小而容許更多的部件整合至既有的晶片面積內。
這些集積度的改進實質上是朝二維(two-dimensional,2D)方面的，因為積體部件所佔的體積實際上位於半導體晶圓的表面。儘管微影(lithography)技術的精進為2D積體電路製作帶來相當大的助益，二維空間所能擁有的密度還是有其物理限制。這些限制之一在於製作這些部件所需的最小尺寸。再者，當更多的裝置放入一晶片中，需具有更複雜的電路設計。
為了進一步增加積體電路密度，已開始研究三維(3D)積體電路(three-dimensional integrated circuit,3DIC)。在典型的3DIC製程中，二個晶片彼此接合，且在每一晶片與基底上的接觸墊之間形成電性連接。例如，在彼此上方接合二個晶片。疊置的晶片接著與一承載基底(carrier substrate)接合，而接線將每一晶片上的 接觸墊電性耦接至承載基底上的接觸墊。
另一種3D封裝使用了疊層封裝(packaging-on-packaging,PoP)或轉接板技術來疊置晶片，以降低形狀因素(form factor)。PoP通常包括一封裝後的晶片，其放至於另一封裝後的晶片，其中晶片透過焊料凸塊(solder bump)而電性耦接。底下的晶片接著電性耦接至一封裝基底。然而，PoP封裝難以降低形狀因素。另外，使用轉接板的封裝受限於基底上的引腳(pin)數量。
在本發明一實施例中，一種半導體裝置，包括：一第一晶片；一第二晶片；一轉接板，第一晶片電性耦接至轉接板的一第一側，而第二晶片電性耦接至轉接板的一第二側；以及一基底，基底電性耦接至轉接板的第二側，其中基底包括一凹口，且第二晶片位於凹口內。
本發明另一實施例中，一種半導體裝置，包括：一轉接板，具有複數接墊位於一第一側及一第二側上；一第一晶片透過第一複數導電凸塊而貼附至位於轉接板的第一側上的接墊；一第二晶片透過第二複數導電凸塊而貼附至位於轉接板的第二側上的接墊；以及一基底，基底透過第三複數導電凸塊貼附至位於轉接板的第二側上的接墊，其中基底具有一凹口，而第二晶片位於凹口內。
本發明又一實施例中，一種半導體裝置之製造方法，包括：提供一或多個第一晶片；提供一或多個第二晶片；提供一轉接板，其具有複數接墊位於一第一側及 一第二側上；利用複數第一導電凸塊將第一晶片貼附至位於轉接板的第一側上；利用複數第二導電凸塊將第二晶片貼附至位於轉接板的第二側上；以及將轉接板貼附至一基底，使至少一個第二晶片位於基底的一凹口內。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
請參照第1a圖，其繪示出根據一實施例之一轉接板102具有透過第一組導電凸塊106而貼附至轉接板102的第一側的第一積體電路晶片104以及透過第二組導電凸塊110而貼附至轉接板102的第二側的第二積體電路晶片108。第一組導電凸塊106及第二組導電凸塊110可包括直徑約5至50微米範圍的微凸塊(microbump)。
轉接板102進一步貼附至一基底112，該基底112可為封裝基底、另一晶片/晶圓、印刷電路板、或高密度內連線等等。轉接板102內的基底通孔電極(through-substrate via,TSV)114提供第一積體電路晶片104與第二積體電路晶片108之間的電性連接以及透過第三組導電凸塊116作為基底112與第一積體電路晶片104及/或第二積體電路晶片108之間的電性連接。轉接板102內的基底通孔電極(TSV)118提供第三組導電 凸塊116與一組導電球120(其可連接至另一基底(未繪示))之間的電性連接。
基底112可為任何適當的基底，例如1/2/1層壓基底或4層層壓基底等等。重佈局線(redistribution line,RDL)以線條122表示之，其位於基底112內，而容許有不同的引腳(pin)配置和較大的導電球120。
基底112也包括一凹口(cavity)224，使第二積體電路晶片108延伸進入形成於下方基底112內的凹口224。凹口224導致第三組導電凸塊116的尺寸小於使用沒有凹口的基底的情形。這是因為第三組導電凸塊116的尺寸不再需要大於第二積體電路晶片108的厚度。需注意的是由於第三組導電凸塊116的尺寸較小，因此可在相同尺寸的轉接板102情形下增加引腳數量。如此一來，可使整體封裝變薄。
第一積體電路晶片104及第二積體電路晶片108可為特定應用中的任何適當的積體電路晶片。舉例來說，第一積體電路晶片104及第二積體電路晶片108其中之一為記憶體晶片，例如DRAM、SRAM及/或NVRAM等等，而另一晶片可為邏輯電路。在一實施例中，例如本範例，第二積體電路晶片108可包括一DRAM晶片，其厚度約100微米。第三組導電凸塊116的厚度約80微米(約60微米塌陷)。若使用凹口的基底，第三組導電凸塊116需要較大的尺寸，例如150微米，其塌陷後的厚度約120微米。較大的導電球120的直徑約250微米。因此，凹口224導致封裝體的總高度H(從導電球120 至第一積體電路晶片104的上表面)約0.87毫米(mm)，而當使用無凹口的基底，總高度約0.93毫米。
凹口224內可選擇性填入導熱墊片226或填洞材料。導熱墊片226可為一順應性材料，適於填入第二積體電路晶片108與基底112之間的空隙。導熱墊片226可為導熱材料，以將熱從第二積體電路晶片108導出。在一實施例中，導熱墊片226由Therm-A-GapTM Gels或Interface Materials(固美麗(Chomerics,div.of Parker Hannifin Corp.)公司製造)所構成。這些材料可包括具有金屬填充物的彈性體。也可使用其他材料，例如熱介面材料或高分子材料。
第1a圖也繪示出一非必要的導熱層228，其位於基底112內。導熱層228可為一銅接墊。導熱層228的厚度取決於特定裝置及額外熱消散的需求。舉例來說，第1a圖繪示出的實施例中，導熱層228佔了第二積體電路晶片108下方基底體積的30%。第1b及1c圖繪示出的實施例中，導熱層228佔了較大的量，其分別佔了60%及100%。需注意的是取決於導熱層228的尺寸，沿者基底112底側的重佈局線(RDL)122並未延伸至第二積體電路晶片108的下方。舉例來說，比較第1a圖的實施例(重佈局線122延伸於凹口224與基底112的底部之間)與第1c圖的實施例(由於導熱層228的尺寸，凹口224與基底112的底部之間沒有重佈局線122)。
在另一實施例中，可使用熱導孔(thermal via)230，如第1d圖所示。在一些實施例中，熱導孔230(如第1d 圖所示)的效能特性相似於佔100%的導熱層，但是導熱材料(例如，銅)含量較少，因此更加省成本。
第1a至1d圖也繪示出底膠(underfill)材料124，其設置於不同部件之間，例如，第一積體電路晶片104、第二積體電路晶片108、轉接板102及基底112。封膠(encapsulant)或外模(overmold)126可覆蓋部件可防止來自環境或外部汙染源。
第2至9圖係繪示出形成半導體裝置(如，第1a至1d圖所示)的方法。需注意的是第2至9圖係繪示出先將一第一晶片連接至轉接板的第一側，接著在轉接板的第二側形成導電凸塊，再將第二晶片放置於轉接板的第二側，最後將轉接板貼附至內部具有凹口的基底。可以理解的是上述順序僅為範例說明，且可使用其他順序。需注意的是以下的實施例係假設多重晶片放置於轉接板的每一側，接著切割(singulate)轉接板，以放置於基底上。也可使用其他製程步驟，包括在放置第一晶片及/或第二晶片之前切割轉接板。
請參照第2圖，其繪示出根據一實施例之轉接板202。在一實施例中，轉接板202包括一基底206、一或多層介電層208、內連線210、接觸墊212及基底通孔電極214。一般而言，基底206近似用於形成積體電路晶片的摻雜的矽基底。雖然基底206也可由其他材料所構成，但是相信使用矽基底作為轉接板可降低應力，這是因為矽基底與用於晶片的矽之間熱膨脹係數(CTE)不相稱程度低於由不同材料所構成的基底。
介電層208可為氧化介電層或其他介電材料，其中內連線210可由導電材料所構成，例如鋁及銅。內連線210可包括多層重佈局線以及內連接相鄰的重佈局線的介層窗(via)。內連線可由銅、鎳、鋁、鎢、鈦及其組合等等所構成。
當完成後續製程步驟，基底通孔電極214透過內連線210，提供轉接板202的第一側上的接觸墊212與轉接板202的第二側的導電路徑。基底通孔電極214可由任何適當的方法所構成。舉例來說，可透過一或多道蝕刻製程、研磨(milling)及雷射技術等等，形成延伸進入基底206的開口。可在開口內順應性形成擴散阻障層、黏著層及隔離層等等並填入導電材料。擴散阻障層可包括一或多層的TaN、Ta、TiN、Ti、CoW等等。導電材料可包括銅、鎢、鋁、銀及其組合等等並透過電化學電鍍而形成，藉以形成基底通孔電極214。
需注意的是所繪示的轉接板202為切割形成分離封裝體之前的轉接板。在第2圖中，線216為轉接板202完成切割的邊界，例如切割線(scribe line)。需注意的是圖式中每一封裝體具有二個接觸墊212及二個基底通孔電極214僅為範例說明，真實的裝置可具有多或更少的接觸墊212及基底通孔電極214。
第3圖係繪示出在轉接板202上放置第一晶片318的一實施例。第一晶片318可包括特定應用中任何適當的電路。在一實施例中，第一晶片318以覆晶(flip-chip)配置方式電性耦接至轉接板202，使接觸墊位於第一晶片 318上而面向轉接板202。第一晶片318的接觸墊透過導電凸塊320(其可由無鉛焊料、共晶鉛(eutectic lead)等所構成)而電性耦接至轉接板202上的接觸墊。
非必要的底膠材料322可注入或以其他方式形成於第一晶片318與轉接板202之間的空間。底膠材料322可包括液態環氧化物、變形膠、矽橡膠等等，位於第一晶片318與轉接板202之間，接著進行固化使其硬化。此外，底膠材料322還可減少導電凸塊320內的裂縫，並防止接點受到汙染。
第4圖係繪示出貼附承載基底424及轉接板202背側薄化的一實施例。可使用黏著材料426來貼附承載基底424。一般而言，承載基底424在進行後續製程步驟期間提供了臨時的機械性及結構性支撐。此方式可降低或防止轉接板202的損害。承載基底424可包括玻璃、氧化矽、氧化鋁等等。黏著材料426可為任何適當的黏著劑，例如紫外光(UV)膠，其在照射紫外光後失去黏性。
在將承載基底424貼附至轉接板202之後，對轉接板202的背側進行薄化製程而露出基底通孔電極214。薄化製成可利用蝕刻製程及/或平坦化製程(例如，化學機械研磨(chemical mechanical polishing,CMP))來進行。舉例來說，一開始可進行平坦化製程，例如CMP，以初步露出基底通孔電極214的襯層(liner)。之後，可進行一或多道的蝕刻製程，其對於襯層材料與轉接板之間具有高蝕刻選擇比，以留下突出於轉接板202背側的基底通孔電極214，如第4圖所示。在一些實施例中，轉接 板202包括矽，而蝕刻製程可為乾蝕刻製程，其利用了HBr/O2 、HBr/Cl2 /O2 、SF6 /Cl2 、SF6 等電漿。
在向下凹陷轉接板202背側之後，形成一保護層428，例如旋塗玻璃(spin-on glass,SOG)層。之後，可進行一或多道蝕刻製程，以保護層428向下凹陷並去除襯層。蝕刻製程對於保護層428/襯層材料與基底通孔電極214材料之間具有高蝕刻選擇比。然而，需注意的是在其他實施例中，基底通孔電極214並未突出於轉接板202背側，因而可使用任何適當的基底通孔電極214與相關的內連線配置。
第5圖係繪示出製做應力緩衝層530與背側重佈局線532的一實施例。應力緩衝層530可由經過沉積及回蝕刻而露出基底通孔電極214的阻焊材料或低溫聚醯亞胺(polyimide)所構成。之後可製做背側重佈局線532。背側重佈局線532可由任何適當的導電材料所構成，例如銅、銅合金、鋁、銀、金及其組合等等並利用任何適當的技術而形成，例如電化學電鍍(electro-chemical plating,ECP)、無電電鍍(electroless plating)、或其他沉積技術，例如濺鍍(sputtering)、印刷、及化學氣相沉積(chemical vapor deposition,CVD)等等。也可使用一罩幕層(未繪示)。
接下來，如第6圖所示，毯覆性形成一鈍化保護(passivation)層634並圖案化，以形成開口，其內形成了凸塊底層金屬(under bump metallization,UBM)結構636及預焊料(presolder)638。鈍化保護層634可由氮 化物、氧化物、聚醯亞胺等所構成。鈍化保護層634內的開口可透過微影技術而形成，使開口露出部分的背側重佈局線532。凸塊底層金屬結構636可由一或多層的導電材料所構成，且提供了背側重佈局線532與後續製程步驟所形成的焊料凸塊之間的電性連接。凸塊底層金屬結構636可由一或多層的鉻、鉻銅合金、銅、金、鈦、鉭、鎢、鎳及其組合等所構成。完成之後，將預焊料形成於凸塊底層金屬結構636上。
第7圖係繪示出將導電凸塊740放置於選定的凸塊底層金屬結構636上的一實施例。導電凸塊740可由共晶焊料、無鉛焊料等所構成。以下將詳述更細節的部分。晶片將貼附至未放置導電凸塊740的凸塊底層金屬結構636。為了提供晶片的位置，導電凸塊740可略大於晶片，當晶片未貼附至轉接板202的兩側。儘管如以上所述，使用具有凹口的下方基底可降低或排除需要較大凸塊尺寸的問題。相較於貼附至後續製程步驟中的晶片的凸塊底層金屬結構636而言，耦接至導電凸塊740的凸塊底層金屬結構636的尺寸可大一些，以容納較大尺寸的導電凸塊740。
第8圖係繪示出在導電凸塊740之間放置第二晶片842的一實施例。第二晶片842可包括特定應用中任何適當的電路。在一實施例中，第二晶片842以覆晶配置方式電性耦接至轉接板202，使接觸墊位於第二晶片842上而面向轉接板202。第二晶片842的接觸墊透過導電凸塊844(其可由無鉛焊料、共晶鉛等所構成)而電性耦接至 轉接板202上的接觸墊。
非必要的底膠材料846可注入或以其他方式形成於第二晶片842與轉接板202之間的空間。相似於使用於第一晶片318與轉接板202之間的底膠材料322，底膠材料846可減少導電凸塊740內的裂縫，並防止接點受到汙染。底膠材料846可包括液態環氧化物、變形膠、矽橡膠等等，位於第二晶片842與轉接板202之間，接著進行固化使其硬化。
第9圖係繪示出切割第8圖中轉接板202並貼附至具有凹口954形成於內的基底952(例如，第1a至1d圖所述的基底)之後的結構。在本實施例中，把第二晶片放置於適當位置，使第二晶片842延伸進入凹口954內。如以上所述，使用具有凹口的基底可容許使用較小的導電凸塊740，因而可得到較小的封裝尺寸。
第9圖也繪示出非必要的散熱層956，其幫助第二晶片842散熱。散熱層956可包括導熱墊片226、導熱層228及/或熱導孔230。基底952可透過任何適當方法所形成。
上述實施例中已發現可降低晶片與基底之間的應力。相信部分的原因在於第一晶片318、第二晶片842及轉接板202之間CTE的不相稱接近於零，特別是在使用矽轉接板的時候。此種類型的配置使其從基底952處熱隔離了第一晶片318及第二晶片842。再者，基底952與轉接板202之間的連接是透過導電凸塊740(其通常較大)。由於有較大的尺寸，應力可散佈於較大的區域， 因而形成更堅固的接點。
上述實施例中已發現可降低半導體裝置的操作溫度，特別是在使用導熱墊片與散熱片的時候。舉例來說，第10圖係繪示出此處敘述的實施例所得到的結果。如第10圖所示，結構(其中第一晶片為邏輯晶片且操作於2.0W，而第二晶片為DRAM晶片且操作於0.4W)的操作溫度可從64℃降至58℃以下。可以理解的是由於操作溫度降低，電力消耗也會跟著降低。
第11a及11b圖係繪示出具有與不具有轉接板的疊置晶片配置之比較，其中模擬情況是使用221℃至25℃之間熱循環、約20微米的微凸塊及無鉛焊料(例如，SnAg)。特別的是第11a圖係繪示出第一晶片1102貼附至基底1104(例如，1/2/1層壓基底)以及第二晶片1106直接放置於第一晶片1102的配置的應力分佈。如圖所示，顯著的應力存在於第一晶片1102與第二晶片1106之間的連接。而顯著的應力也存在於基底1104與第一晶片1102之間的連接。
相較之下，第11b圖係繪示出第1圖所述實施例的應力分佈。在此情形中，第一晶片1102與第二晶片1106連接至轉接板1108的兩相對側。此類型的配置導致第11a圖的範例中最大應力降至0.845 a.u.。相較於最大應力為2.5 a.u.的情形，最大應力降低了66%。上述應力降低相信部分的原因在於第一晶片1102、第二晶片1106及轉接板1108之間CTE的不相稱接近於零，特別是在使用矽轉接板的時候。此種類型的配置使其從基底1104處熱隔離 了第一晶片1102及第二晶片1106。
雖然上述結果並未採用第1a至1d圖所述的凹口，然而可以預期的是使用具有凹口的基底也會有相似的應力特徵，且具有更小的封裝尺寸。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
102、202、1108‧‧‧轉接板
104‧‧‧第一積體電路晶片
106‧‧‧第一組導電凸塊
108‧‧‧第二積體電路晶片
110‧‧‧第二組導電凸塊
112、206、952、1104‧‧‧基底
114、118、214‧‧‧基底通孔電極
116‧‧‧第三組導電凸塊
120‧‧‧導電球
122‧‧‧重佈局線
124、322、846‧‧‧底膠材料
126‧‧‧外模
208‧‧‧介電層
210‧‧‧內連線
212‧‧‧接觸墊
216‧‧‧線
224、954‧‧‧凹口
226‧‧‧導熱墊片
228‧‧‧導熱層
230‧‧‧熱導孔
318、1102‧‧‧第一晶片
320、740、844‧‧‧導電凸塊
424‧‧‧承載基底
426‧‧‧黏著材料
428‧‧‧保護層
530‧‧‧應力緩衝層
532‧‧‧背側重佈局線
634‧‧‧鈍化保護層
636‧‧‧凸塊底層金屬結構
638‧‧‧預焊料
842、1106‧‧‧第二晶片
956‧‧‧散熱層
H‧‧‧總高度
第1a至1d圖係繪示出各個實施例的特徵及特性。
第2至9圖係繪示出根據一實施例之半導體裝置製造方法中各個階段的剖面示意圖。
第10圖係繪示出不同實施例的熱特徵曲線關係圖。
第11a及11b圖係繪示出具有與不具有轉接板的疊置晶片中的應力特徵比較。
202‧‧‧轉接板
206‧‧‧基底
208‧‧‧介電層
210‧‧‧內連線
212‧‧‧接觸墊
214‧‧‧基底通孔電極
322、846‧‧‧底膠材料
954‧‧‧凹口
318‧‧‧第一晶片
320、740、844‧‧‧導電凸塊
428‧‧‧保護層
530‧‧‧應力緩衝層
532‧‧‧背側重佈局線
634‧‧‧鈍化保護層
636‧‧‧凸塊底層金屬結構
638‧‧‧預焊料
842‧‧‧第二晶片
956‧‧‧散熱層

Claims (10)

  1. 一種半導體裝置，包括：一第一晶片；一第二晶片；一轉接板，該第一晶片電性耦接至該轉接板的一第一側，而該第二晶片電性耦接至該轉接板的一第二側；以及一基底，該基底電性耦接至該轉接板的該第二側，其中該基底包括一凹口，且該第二晶片位於該凹口內。
  2. 如申請專利範圍第1所述之半導體裝置，更包括一導熱墊片，其沿著該凹口的一底部。
  3. 如申請專利範圍第1所述之半導體裝置，其中該基底更包括一導熱層，位於該凹口下方且該導熱層自該凹口的一表面延伸至該基底的一相對側。
  4. 如申請專利範圍第1之半導體裝置，其中該轉接板為矽轉接板且該基底為1/2/1層壓基底。
  5. 一種半導體裝置，包括：一轉接板，具有複數接墊位於一第一側及一第二側上；一第一晶片透過第一複數導電凸塊而貼附至位於該轉接板的該第一側上的該等接墊；一第二晶片透過第二複數導電凸塊而貼附至位於該轉接板的該第二側上的該等接墊；以及一基底，該基底透過第三複數導電凸塊貼附至位於該轉接板的該第二側上的該等接墊，其中該基底具有一 凹口，而該第二晶片位於該凹口內。
  6. 如申請專利範圍第5所述之半導體裝置，更包括一熱填洞材料，位於該第二晶片與該基底之間的該凹口內。
  7. 如申請專利範圍第5所述之半導體裝置，其中該基底更包括一導熱層，位於該凹口下方且該導熱層自該凹口的一表面延伸至該基底的一相對側。
  8. 一種半導體裝置之製造方法，包括：提供一或多個第一晶片；提供一或多個第二晶片；提供一轉接板，其具有複數接墊位於一第一側及一第二側上；利用複數第一導電凸塊將上述第一晶片貼附至位於該轉接板的該第一側上；利用複數第二導電凸塊將上述第二晶片貼附至位於該轉接板的該第二側上；以及將該轉接板貼附至一基底，使至少一個第二晶片位於該基底的一凹口內。
  9. 如申請專利範圍第8項所述之半導體裝置的製造方法，更包括在該凹口內形成一導熱墊片。
  10. 如申請專利範圍第8項所述之半導體裝置的製造方法，其中該基底包括一導熱層位於該凹口下方且該導熱層自該凹口延伸至該基底的一相對側。
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