TWI617004B - 三維晶片堆疊的方法與結構 - Google Patents

三維晶片堆疊的方法與結構 Download PDF

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TWI617004B
TWI617004B TW105122847A TW105122847A TWI617004B TW I617004 B TWI617004 B TW I617004B TW 105122847 A TW105122847 A TW 105122847A TW 105122847 A TW105122847 A TW 105122847A TW I617004 B TWI617004 B TW I617004B
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Taiwan
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bonding
wafer
device dies
dies
carrier
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TW105122847A
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TW201714274A (zh
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余振華
林詠淇
邱文智
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例之三維晶片堆疊的方法包含置放第一複數裝置晶粒於一第一載體上方，該第一複數裝置晶粒與該第一載體結合形成一第一複合晶圓。該第一複合晶圓接合至第二晶圓，且該第一複數裝置晶粒係經由混合接合而接合至該第二晶圓中的第二複數裝置晶粒。該方法進一步包含自該第一複數裝置晶粒剝離該第一載體，囊封該第一複數裝置晶粒於一囊封材料中，以及形成一互連結構於該第一複數裝置晶粒與該囊封材料上方。

Description

三維晶片堆疊的方法與結構
本發明實施例係關於三維晶片堆疊的方法與結構。
自積體電路發明之後，由於各種電子元件(例如電晶體、二極體、電阻器、電容器等)之整合密度持續改良，因而半導體產業已持續快速成長。在大多數的情況下，整合密度的改良是來自於重複降低最小構件尺寸，這使得可在給定面積上整合更多元件。
此等整合改良本質上主要是二維(2D)，其中整合元件所佔的體積主要是在半導體晶圓的表面上。雖然微影的顯著改良已經在2D積體電路形成造成明顯改良，然而在二維中可達到的密度有物理限制。此等限制之一是製造此等元件所需的最小尺寸。再者，當在一晶片中放入更多裝置時，需要更複雜的設計。
另一限制來自於當裝置數目增加時，裝置之間的互連數目與長度顯著增加。當互連的數目與長度增加時，電路RC延遲與功率消耗皆增加。
因而探究三維(3D)積體電路(integrated circuit,IC)以解決以上所討論的限制。在3DIC的典型形成製程中，形成各自包含一些積體電路的兩個晶圓或晶粒，而後接合在一起。該接合典型包含使用焊料用以接合銅凸塊上所形成的鎳層。
本揭露的一些實施例提供一種方法，其包括置放第一複數裝置晶粒於一第一載體上方，該第一複數裝置晶粒與該第一載體結合形成一第一複合晶圓；接合該第一複合晶圓至一第二複合晶圓，其中該第一複數裝置晶粒經由混合接合(hybrid bonding)而接合至該第二晶圓中的第二複數裝置晶粒；自該第一複數裝置晶粒，剝離該第一載體；囊封該第一複數裝置晶粒於一囊封材料中；以及形成一互連結構於該第一複數裝置晶粒與該囊封材料上方。
本揭露的一些實施例提供一種方法，其包括置放一第一複數裝置晶粒於一載體上方；形成複數貫穿通路於一晶圓的第二複數裝置晶粒上；對準該載體上的該第一複數裝置晶粒與該第二複數裝置晶粒；經由混合接合，接合該第一複數裝置晶粒至該第二複數裝置晶粒，其中該複數貫穿通路延伸至該第一複數裝置晶粒之間的空間；自該第一複數裝置晶粒，剝離該載體；囊封該第一複數裝置晶粒於一囊封材料中；進行一平坦化，以使該第一複數裝置晶粒、該囊封材料、以及該複數貫穿通路齊平；以及形成一互連結構於該第一複數裝置晶粒與該囊封材料上方。
本揭露的一些實施例提供一種封裝，其包括一第一裝置晶粒；一第二裝置晶粒，其係位於該第一裝置晶粒上方並且經由混合接合而接合至該第一裝置晶粒；一囊封材料，其囊封該第一裝置晶粒與該第二裝置晶粒於其中；以及一互連結構，其係位於該第二裝置晶粒上方，其中該互連結構延伸超出該第一裝置晶粒與該第二裝置晶粒二者的邊緣。
20‧‧‧載體
22‧‧‧離型層
24‧‧‧對準標記
25‧‧‧半導體基板
26‧‧‧裝置晶粒
28‧‧‧互連結構
30‧‧‧介電層
32‧‧‧金屬線
34‧‧‧通路
36‧‧‧接合墊
38‧‧‧表面介電層
40‧‧‧介電襯層
42‧‧‧傳導通路
43‧‧‧貫穿通路
44‧‧‧囊封材料
46‧‧‧互連結構
48‧‧‧介電層
50‧‧‧電連接體
52‧‧‧封裝
54‧‧‧金屬墊
55‧‧‧空氣間隙
60‧‧‧裝置晶粒
62‧‧‧貫穿通路
63‧‧‧貫穿通路
64‧‧‧囊封材料
66‧‧‧互連結構
68‧‧‧空氣間隙
70‧‧‧空氣間隙
100‧‧‧複合晶圓
125‧‧‧半導體基板
200‧‧‧晶圓
200’‧‧‧複合晶圓
202‧‧‧裝置晶粒/晶片
203‧‧‧貫穿通路
204‧‧‧半導體基板
220‧‧‧載體
222‧‧‧離型層
223‧‧‧介電層
224‧‧‧對準標記
227‧‧‧RDL
228‧‧‧互連結構
229‧‧‧互連結構
236‧‧‧接合墊
238‧‧‧表面介電層
240‧‧‧介電襯層
242‧‧‧貫穿通路
為協助讀者達到最佳理解效果，建議在閱讀本揭露時同時參考附件圖示及其詳細文字敘述說明。請注意為遵循業界標準作 法，本專利說明書中的圖式不一定按照正確的比例繪製。在某些圖式中，尺寸可能刻意放大或縮小，以協助讀者清楚了解其中的討論內容。
圖1至圖9係根據一些實例說明形成封裝之中間階段的剖面圖。
圖10至圖17係根據一些實施例說明形成封裝之中間階段的剖面圖。
圖18至圖26係根據一些實施例說明形成封裝之中間階段的剖面圖。
圖27至圖35係根據一些實施例說明形成封裝之中間階段的剖面圖。
圖36至圖43係根據一些實施例說明一些封裝的剖面圖。
圖44係根據一些實施例說明例示的互連結構之一部分。
圖45至圖47係根據一些實施例說明混合結合的一些部分之剖面圖。
圖48係根據一些實施例說明形成封裝的流程圖。
本揭露提供了數個不同的實施方法或實施例，可用於實現本發明的不同特徵。為簡化說明起見，本揭露也同時描述了特定零組件與配置的範例。請注意提供此等特定範例的目的僅在於示範，而非予以任何限制。舉例而言，在以下說明第一構件如何在第二構件上或上方的敘述中，可能會包括某些實施例，其中第一構件與第二構件為直接接觸，而敘述中也可能包括其他不同實施例，其中第一構件與第二構件中間另有其他構件，以致於第一構件與第二構件並不直接 接觸。此外，本揭露中的各種範例可能使用重複的參考數字和/或文字註記，以使文件更加簡單化和明確，此等重複的參考數字與註記不代表不同的實施例與配置之間的關聯性。
另外，本揭露在使用與空間相關的敘述詞彙，如「在...之下」、「下方」、「低於」、「在...之上」、「高於」和類似詞彙時，為便於敘述，其用法均在於描述圖示中一個元件或構件與另一個(或多個)元件或構件的相對關係。除了圖示中所顯示的角度方向外，此等空間相對詞彙也用來描述該裝置在使用中以及操作時的可能角度和方向。該裝置的角度方向可能不同(旋轉90度或其它方位)，而在本揭露所使用的此等空間相關敘述可以同樣方式加以解釋。
根據各種例示實施例，提供包含晶粒堆疊的封裝以及晶圓級形成該封裝的方法。說明形成一些封裝的中間階段。討論一些實施例的一些變化。在不同圖式與說明實施例中，相同的元件符號係用以表示相同元件。
圖1至圖9係根據一些實施例說明封裝形成之中間階段的剖面圖。圖1至圖9所示之步驟亦概示說明於圖48所示的製程流程300中。
圖1與圖2係根據一些實施例說明複合晶圓的形成。參閱圖1，提供載體20，在載體20上形成離型層22。載體20可為覆蓋載體晶圓，其可為玻璃載體、陶瓷載體、有機載體、或類似物。載體20可具有圓形俯視形狀，並且可具有矽晶圓的俯視尺寸。例如，載體20可具有8吋直徑、12吋直徑、或類似者。離型層22可由聚合物為基礎的材料(例如光熱轉換(Light To Heat Conversion,LTHC)材料)所形成，其在高能量光的熱能之下可分解。根據本揭露的一些實施例，離型層22係由環氧化合物為基礎的熱釋放材料所形成。離型層22可分散如液體並且硬化。根據其他實施例，離型層22係疊層膜並且疊層於載體20 上。離型層22的頂部表面係齊平並且具有高程度的共平面性。形成對準標記24。個別步驟係如圖48所示之製程中的步驟302所示。根據一些實施例，藉由使用雷射或是微影製程，在離型層22中形成開口，而形成對準標記24。
圖2係說明裝置晶粒26的配置。個別步驟係如圖48所示之製程中的步驟304所示。裝置晶粒26可經由晶粒附接膜(未繪示)而附接至離型層22，該晶粒附接膜可為黏著膜。裝置晶粒26可為包含邏輯電晶體於其中的邏輯裝置晶粒、記憶體裝置晶粒、或類似物。可依據對準標記24而決定裝置晶粒26的位置，因而各個裝置晶粒26具有自各個對準標記24的相同相對偏移。在說明全文中，包含裝置晶粒26與載體20的組合結構係稱為複合晶圓100。
裝置晶粒26為已經通過功能性測試的優良晶粒(known-good-dies)。各個裝置晶粒26包含半導體基板25、主動裝置(未繪示)以及互連結構28。例示的互連結構28係概示於圖44中。根據一些實施例，互連結構28包含介電層30、金屬線32、以及在介電層30中的通路34。在互連結構28的表面可存在表面介電層38中的接合墊36。接合墊36可為含銅墊。表面介電層38可為含矽介電層，其可包含氧化矽。此外，可有(或可無)包圍接合墊36的介電襯層40存在。接合墊36的頂部表面與表面介電層38係彼此共平面。介電襯層40的頂端可與接合墊36的頂部表面共平面或可為凹陷。
參閱圖3，提供晶圓200。晶圓200包含複數個相同的晶片202於其中。晶圓200亦包含半導體基板125、主動裝置(未繪示)、以及互連結構228。晶片202亦可為邏輯晶片、記憶體晶片、IO晶片、或類似物。互連結構228可具有與圖44所示之類似結構，其亦可包含介電層、金屬線、通路、接合墊、以及表面介電層。
在晶圓100的頂部表面上，形成具有傳導柱形狀的傳 導通路42。由於傳導通路42穿過後續形成的囊封材料，因而稱為貫穿通路。個別步驟係如圖48所示之製程流程中的步驟306。雖然繪示一貫穿通路42重疊於各個裝置晶粒202，然而可有複數貫穿通路42重疊於各個裝置晶粒202。在圖2中，貫穿通路42的高度係小於裝置晶粒26的高度。傳導通路42的形成始於在裝置晶粒202之表面的金屬墊54(未繪示於圖3，請參閱圖9)。金屬墊可與裝置晶粒202中的接合墊236(未繪示於圖3，請參閱圖9)共平面並且可同步形成金屬墊與裝置晶粒202中的接合墊236。傳導通路42的形成可包含在晶圓200上形成光阻(未繪示)、圖案化該光阻以暴露部分的該光阻、鍍覆貫穿通路42、以及移除該光阻。
接著，參閱圖4，複合晶圓100與晶圓200經由混合接合(hybrid bonding)而彼此接合，該混合接合為晶圓級接合。個別步驟係如圖48所示之製程流程中的步驟308所示。例如，藉由將對準標記24對準貫穿通路42，複合晶圓100與晶圓200彼此對準。當晶圓100與200對準時，對準標記24可重疊對應於貫穿通路42。圖45係說明裝置晶粒202與裝置晶粒26之間的混合接合之部分的放大圖式。如圖45所示，裝置晶粒202包含裝置晶粒202中的接合墊236經由直接的金屬對金屬接合而接合至裝置晶粒26中的接合墊36。裝置晶粒202中的表面介電層238係經由熔融(氧化物對氧化物)接合而接合至表面介電層38。
返回參閱圖4，該混合接合包含預接合步驟，其中複合晶圓100被配置為與晶圓200接觸。接著，例如，在溫度約200℃與約300℃之間，進行退火約1.5小時與約2.5之間的期間，因而接合墊36與236中的銅(圖45)彼此交互擴散，而形成直接的金屬對金屬接合。
不同於習知的晶圓對晶圓混合接合，所得到的接合結 構中有複數個空間，其中該空間係在複合晶圓100的裝置晶粒26之間。由於氣泡不太可能被截留在晶圓100與200之間，因此這排除了在真空環境進行晶圓級混合接合的需求。作為比較，在習知的晶圓對晶圓混合接合中，在接合的晶圓中，裝置晶粒之間沒有空間。
接著，載體20被剝離(de-bonded)。個別步驟係如圖48所示之製程流程中的步驟310所示。根據一些例示實施例，該剝離(de-bonding)包含在離型層22上投射光(例如雷射)以分解離型層22。根據其他實施例，藉由將圖4中的結構浸入可溶解離型層22的化學溶液中，進行剝離。由於晶圓100與200之間有空間，化學溶液可達到離型層22的內部，接近晶圓100的中心，因而可完全溶解離型層22。由於載體20的剝離，複合晶圓100被分離為分離的裝置晶粒26，各自經由混合接合而接合至晶圓200，如圖5所示。
根據一些例示實施例，預接合與退火皆於載體20的剝離之前進行。根據其他實施例，在剝離之後，進行退火。據此，於晶圓對晶圓層級(wafer-to-wafer level)進行預接合，同時在晶粒對晶圓層級(die-to-wafer level)進行退火。有利的是，在剝離之後藉由進行退火，離型層22的材料可採用無法忍受退火溫度的材料。
接著，如圖6所示，在裝置晶粒26上囊封(成形)囊封材料44。個別步驟係如圖48所示之製程流程中的步驟312所示。囊封材料44填充鄰近裝置晶粒26與貫穿通路42之間的間隙。囊封材料44可包含模塑料、成形底膠填充、環氧化合物、或樹脂。根據一些實施例，囊封材料44的頂部表面係高於貫穿通路42的頂部表面與裝置晶粒26的頂部表面(其係半導體基板25的表面)。而後，進行平坦化步驟(例如化學機械拋光(Chemical Mechanical Polish,CMP))以移除過多的囊封材料44，因而暴露半導體基板25與貫穿通路42。再者，在平坦化中，亦可薄化半導體基板25，例如，至厚度範圍為約2微米與10微米 之間。
接著，參閱圖7，形成互連結構46。個別步驟係如圖48所示之製程流程中的步驟314所示。互連結構46可具有類似於圖44所示之結構，並且包含介電層與該介電層中的重佈線(Redistribution Lines,RDL)。RDL電連接接貫穿通路42。RDL亦包含金屬線部分與通路部分，類似於圖44所示。根據本揭露的一些實施例，互連結構46包含表面接合墊與表面介電層，其具有彼此共平面的頂部表面，其係與圖44所示實質相同。當更多裝置晶粒接合至互連結構46時，如圖37所示，可採用此等實施例。根據其他實施例，互連結構46不具有平坦的頂部表面。
根據本揭露的一些實施例，經由鍍覆而形成互連結構46中的RDL。根據其他實施例，使用鑲嵌製程形成RDL。
參閱圖8，在互連結構46上方形成介電層48。可使用聚合物形成介電層48，該聚合物可包含聚苯并噁唑(PBO)、聚亞醯胺、苯并環丁烯(BCB)、或類似物。
圖8亦說明電連接體50的形成，電連接體50係電耦合至互連結構46中的RDL與貫穿通路42。個別步驟亦如圖48所示之製程流程的步驟314所示。根據一些例示實施例，電連接體50可包含凸塊下金屬層(UBM，未繪示)與焊料區。UBM的形成可包含沉積與圖案化。焊球可配置在UBM上，並且而後回焊。根據其他實施例，電連接體50的形成包含進行鍍覆步驟，以於RDL上方形成焊料區而後回焊該焊料區。電連接體50亦可包含金屬柱以及可能包含焊料蓋，其亦可經由鍍覆而形成。
而後，圖8所示的結構被切割為個別封裝，其中圖9係說明封裝52之一。個別步驟係如圖48所示之製程流程的步驟316所示。封裝52包含較大的裝置晶粒202，其一路延伸至封裝52的邊緣。 較小的裝置晶粒26係經由混合接合而接合至較大的裝置晶粒202，該較小的裝置晶粒26具有較小的橫向尺寸與較小的俯視面積。可自金屬墊54直接形成貫穿通路42，該貫穿通路穿過囊封材料44。囊封材料44進一步包圍裝置晶粒26與貫穿通路42。
圖10至圖17係根據本揭露的一些實施例說明形成封裝之中間階段的剖面圖。除非特別指明，否則此等實施例中的元件之材料與形成方法係與圖1至圖9所示之實施例中以相同元件符號表示的相同元件實質相同。因此，可在圖1至圖9所示之實施例的討論中得到關於圖10至圖17所示之元件的形成製程與材料之細節。
圖10至圖17所示之實施例係類似於圖1至圖9所示之實施例，差別在於在複合晶圓上先形成貫穿通路。參閱圖10，在離型層22上方形成貫穿通路42，該離型層22係進一步位於載體20上方。根據本揭露的一些實施例，在離型層22上方，可形成另一聚合物層，例如PBO(未繪示)。傳導通路42的形成可包含在該另一聚合物層上方形成毯狀晶種層(例如鈦層與該鈦層上方的銅層)，在該晶種層上方形成光阻(未繪示)，圖案化該光阻以暴露該晶種層的一些部分，鍍覆貫穿通路42，移除該光阻，以及進行蝕刻以移除先前受到該光阻覆蓋的該晶種層的該部分。
接著，如圖11所示，裝置晶粒26係配置於離型層22與載體20上方，其中可使用DAF(未繪示)，附接裝至晶粒26至下方結構。裝置晶粒26係優良晶粒。裝置晶粒26、貫穿通路42以及下方的載體20等結合稱為複合晶圓100。
接著，參閱圖12，在複合晶圓100上囊封囊封材料44，而後進行平坦化以移除囊封材料44的過多部分。因此，暴露貫穿通路42的頂部表面以及互連結構28的頂部表面。根據一些例示實施例，互連結構28之暴露的頂部表面包含接合墊36與表面介電層38之暴 露的表面，如圖44所示。根據一些實施例，可採用合適的研磨漿與合適的平坦化製程，使得介電襯層40的頂端比接合墊36與表面介電層38更為凹陷，造成介電襯層40中的凹部，其係如圖46所示。
接著，參閱圖13，複合晶圓100與晶圓200係經由混合接合而彼此接合，這發生於裝置晶粒26與對應的裝置晶粒202之間。另一方面，囊封材料44可接觸但未接合至(未有化學與物理鍵形成)互連結構228的頂部表面。據此，可能囊封材料44的一些部分係實體接觸表C193370PBX_CLAIMS20170823M面介電材料與/或互連結構228中的金屬材料。亦可能為囊封材料44的一些其他部分藉由空氣間隙55而與表面介電材料之個別的下方部分與/或金屬材料隔開，其係如圖13所示。由於囊封材料44的非共平面性，這是囊封材料44之平坦化中造成的，因而可產生空氣間隙55。可理解空氣間隙55的位置與尺寸係隨機的，可擴大所述空氣間隙55的尺寸。
圖13所示的結構係不同於圖6中的結構，囊封材料44係以流體形式分配接觸互連結構228，而後硬化。據此，在圖6的實施例中，囊封材料44不僅實體接觸並且接合至互連結構228的頂部表面。再者，在圖6所示的實施例中，囊封材料44與互連結構228的交界處無空氣間隙形成。
在圖13的步驟形成之後，製程繼續，例如，使用高能量光，藉由分解離型層22而剝離載體20。所得的結構係如圖14所示。後續步驟，如圖15至17所示，係與圖7至9所示實質相同，並且製程細節與對應材料不在此處重複。在圖17所示之所得的封裝中，囊封材料44係接觸但可不接合至互連結構228的表面。囊封材料44係接合至上方的互連結構46。再者，可(或可不)形成空氣間隙55。
圖18至26係根據一些實施例說明形成封裝之中間階段的剖面圖。此等實施例與圖1至17之實施例不同之處在於涉及晶圓對 晶圓混合接合中的兩個晶圓皆為複合晶圓。因此，在所得的封裝中，囊封材料包圍兩個晶粒。
參閱圖18，提供載體220與離型層222，其係分別與構件20與22(圖20)實質相同。在離型層222上形成介電層223。根據本揭露的一些實施例，介電層223係由聚合物形成。介電層223亦可由光敏感材料形成，例如聚苯并噁唑(PBO)、聚亞醯胺、苯并環丁烯(BCB)、或類似物，其可經由曝光與顯影而圖案化。根據其他實施例，介電層223係由氮化物，例如氮化矽、氧化物，例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、或類似物而形成。
在介電層223上方形成貫穿通路242。再者，形成互連結構229，其包含介電層223中的RDL 227。根據一些實施例，RDL 227包含金屬線(未繪示)以及通路。根據其他實施例，RDL 227包含單層通路，如圖18所示。接著，如圖19所示，裝置晶粒202係配置於介電層223上方並且附接至介電層223。裝置晶粒202亦係自晶圓200切割(圖3)並且為優良晶粒。因此，形成複合晶圓200’。
接著，參閱圖20，複合晶圓100與複合晶圓200’係彼此接合，經由混合接合以裝置晶粒26接合至裝置晶粒202。複合晶圓100的形成係如圖1與2所示，可設計複合晶圓100中的對準標記24之位置，以對準(並且可重疊)對應的貫穿通路42，以及貫穿通路42與對準標記24係結合作為晶圓100與200’之對準中的對準標記。接合製程可與圖4與5所示與所討論者實質相同，並且不在本文重述。在複合晶圓100中的載體20剝離之後，所得之結構包含裝置晶粒26，其接合至複合晶圓200中的裝置晶粒202，如圖21所示。在後續步驟中，分配且硬化囊封材料44，如圖22所示。而後，進行平面化以暴露且薄化裝置晶粒26，如圖23所示。亦暴露貫穿通路242。圖24至26所示之後續步驟 係與圖7至9所示之步驟相同，並且製程細節與對應的材料不在本文重述。
在圖26所示的封裝中，囊封材料44囊封裝置晶粒26與202二者，並且自裝置晶粒26的頂部表面持續延伸至裝置晶粒202的底部表面。此外，由於單一囊封材料在一製程形成，因而在囊封材料44中無可分辨的界面。例如，囊封材料44中無可分辨的界面與裝置晶粒26及202之間的界面齊平。各個貫穿通路42亦為連續通路，其具有連續且直的邊緣，以及貫穿通路42，例如在裝置晶粒26與202之間的界面階層中，無可分辨的界面。
圖27至35係根據一些實施例說明形成封裝之中間階段的剖面圖。此等實施例與圖18至26之實施例不同之處在於囊封材料中未形成貫穿通路。而是，貫穿通路43形成於裝置晶粒26中，電耦合裝置晶粒202至互連結構46(圖35)。
圖27與28所示之製程係說明複合晶圓200’的形成。製程步驟係類似於圖18與19所示之步驟，差別在未形成貫穿通路。例如，在離型層222中，形成對準標記224。如圖28所示，裝置晶粒202附接至離型層222。
圖29係說明接合複合晶圓100至複合晶圓200’，其中裝置晶粒26係經由混合接合而接合至個別的裝置晶粒202。裝置晶粒26包含貫穿通路43延伸至半導體基板25中。而後，載體20被剝離，如圖30所示。
接著，參閱圖31，囊封材料44係在裝置晶粒26與202上囊封，而後為如圖32所示之平坦化步驟。在平坦化過程中，裝置晶粒26亦被薄化，並且薄化半導體體基板25以暴露貫穿通路43。圖33至35所示之後續步驟係與圖7至9所示實質相同，並且製程細節與對應材料不在本文重述。
在如圖35所示之所得結構中，囊封材料44包圍裝置晶粒26與202二者。囊封材料44中未形成貫穿通路。再者，囊封材料44係在單一製程中形成，因而囊封材料44中未有可分辨的界面。裝置晶粒202至互連結構46的電連接係經由半導體基板25中的貫穿通路43。
圖36至43係根據本揭露的一些實施例說明所形成之封裝的剖面圖。圖36係說明圖9或圖17所示之封裝。圖37係說明封裝類似於圖36的封裝，差別在於另一裝置晶粒60係接合至互連結構46。該接合亦可為混合接合，類似於圖45、46與47所示之方式。貫穿通路62係自互連結構46中的金屬墊(未繪示)開始形成。囊封材料64將裝置晶粒60與貫穿通路62囊封在內。再者，形成互連結構66、介電層48、以及電連接體50。電連接體50係電耦合至貫穿通路62、互連結構46、貫穿通路42以及裝置晶粒202。
圖38係說明封裝類似於圖36的封裝，其中貫穿通路43係形成於裝置晶粒26的半導體基板25中。圖39係說明封裝類似於圖37的封裝，其中貫穿通路43係形成於裝置晶粒26的半導體基板25中，以及貫穿通路63係形成於裝置晶粒60中的半導體基板61中。
圖40係說明裝置類似於圖26的封裝，差別在於裝置晶粒202包含半導體基板204中的貫穿通路203。貫穿通路203係與互連結構28與229中的傳導構件電性相互耦合。圖41係說明封裝類似於圖40的封裝，其中在裝置晶粒26中的半導體基板25中，進一步形成貫穿通路43。
圖42係說明封裝類似於圖26所示之封裝，其中在裝置晶粒26中的半導體基板中25，進一步形成貫穿通路43，並且未有貫穿通路形成於囊封材料44中。圖43係說明封裝類似於圖42所示之結構，其中形成裝置晶粒60、貫穿通路62、以及囊封材料64。再者，在裝置晶粒60中形成貫穿通路63。
圖45至48係根據本揭露的一些實施例說明一些混合接合方案。參閱圖45，形成介電襯層40與240，以分別包圍接合墊36與236。具有介電襯層40與240，即使發生錯位(misalignment)，並且接合墊36接觸介電襯層240，襯墊240將會防止銅從接合墊36擴散至表面介電層238中。同樣地，當發生錯位且接合墊236接觸介電襯層40時，襯墊40將會防止銅從接合墊236擴散至表面介電層38中。
在圖46與47中，形成空氣間隙68與70。空氣間隙68具有碟(dishing)形，其可藉由調整平坦化裝置晶粒26與/或202之頂部表面的平坦化製程而產生。可藉由使用微影製程，蝕刻襯墊40與/或240而形成空氣間隙70。由於銅無法擴散通過空氣間隙，因而當發生錯位時，空氣間隙68與70亦具有防止不想要的銅擴散之功能。
本揭露的實施例具有一些有利的特徵。藉由形成複合晶圓而後使用複合晶圓進行混合接合，改良接合製程的產量。另一方面，使用複合晶圓使得具有不同尺寸的裝置晶粒使用混合接合而接合在一起。此外，藉由形成複合晶圓而非使用未切割的晶圓，可選擇優良晶粒，並且有缺陷的晶粒不會被封裝而造成浪費。
根據本揭露的一些實施例，一種三維晶片堆疊的方法包含置放第一複數裝置晶粒於第一載體上方，該第一複數裝置晶粒與該第一載體結合形成第一複合晶圓。該第一複合晶圓係接合至第二晶圓，且該第一複數裝置晶粒係經由混合接合而接合至第二晶圓中的第二複數裝置晶粒。該方法進一步包含將該第一載體自該第一複數裝置晶粒剝離，囊封該第一複數裝置晶粒於囊封材料中，以及形成互連結構於該第一複數裝置晶粒與該囊封材料上方。
根據本揭露的一些實施例，一種三維晶片堆疊的方法包含置放第一複數裝置晶粒於載體上方，形成複數貫穿通路於晶圓的第二複數裝置晶粒上，對準該在體上的該第一複數裝置晶粒與該第二 複數裝置晶粒，以及經由混合接合，接合該第一複數裝置晶粒至該第二複數裝置晶粒。該複數貫穿通路延伸至該第一複數裝置晶粒之間的空間中。該方法進一步包含剛該載體自該第一複數裝置晶粒剝離，囊封該第一複數裝置晶粒於囊封材料中，進行平坦化以使該第一複數裝置晶粒、該囊封材料以及該複數貫穿通路的頂部表面齊平，以及形成互連結構於該第一複數裝置晶粒與該囊封材料上方。
根據本揭露的一些實施例，一種封裝包含第一裝置晶粒、位於該第一裝置晶粒上方且經由混合接合而接合至該第一裝置晶粒的第二裝置晶粒、囊封該第一裝置晶粒與該第二裝置晶粒於其中的囊封材料、以及位於該第二裝置晶粒上方的互連結構。該互連結構延伸超出該第一裝置晶粒與該第二裝置晶粒二者的邊緣。
前述內容概述一些實施方式的特徵，因而所屬技術領域中具有通常知識者可更加理解本揭露之各方面。所屬技術領域中具有通常知識者應理解可輕易使用本揭露作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。所屬技術領域中具有通常知識者亦應理解此均等架構並不脫離本揭露揭示內容的精神與範圍，並且所屬技術領域中具有通常知識者可進行各種變化、取代與替換，而不脫離本揭露之精神與範圍。
25‧‧‧半導體基板
26‧‧‧裝置晶粒
28‧‧‧互連結構
42‧‧‧傳導通路
44‧‧‧囊封材料
46‧‧‧互連結構
48‧‧‧介電層
50‧‧‧電連接體
202‧‧‧裝置晶粒/晶片
228‧‧‧互連結構

Claims (10)

  1. 一種三維晶片堆疊的方法，其包括：置放第一複數裝置晶粒於一第一載體上方，該第一複數裝置晶粒與該第一載體結合形成一第一複合晶圓；接合該第一複合晶圓至一第二複合晶圓，其中該第一複數裝置晶粒經由混合接合而接合至該第二複合晶圓中的第二複數裝置晶粒，其中在該接合過程之後，該第一複數裝置晶粒位於該第一載體和該第二複合晶圓之間；自該第一複數裝置晶粒，剝離該第一載體；囊封該第一複數裝置晶粒於一囊封材料中；以及形成一互連結構於該第一複數裝置晶粒與該囊封材料上方。
  2. 如申請專利範圍第1項的方法，其中在該接合過程中，於該第一複數裝置晶粒之間存在空間，進一步包括：在接合該第一複合晶圓至一第二複合晶圓之前形成複數貫穿通路於該第二晶圓上；以及在接合該第一複合晶圓至該第二晶圓中，該複數貫穿通路延伸至該空間中。
  3. 如申請專利範圍第2項的方法，其中當進行該接合時，該複數貫穿通路係與該第一複合晶圓分隔。
  4. 如申請專利範圍第1項的方法，進一步包括：形成複數貫穿通路於該第一複合晶圓上，其中該囊封該第一複數裝置晶粒係在該第一複合晶圓上進行；以及在該接合中，該囊封材料接觸且未接合至該第二複數裝置晶粒。
  5. 如申請專利範圍第1項的方法，進一步包括形成該第二晶圓，其包括：置放第二複數裝置晶粒於一第二載體上方，該第二複數裝置晶 粒與該第二載體結合形成該第二晶圓，其係一第二複合晶圓；以及該囊封材料包圍該第一複數裝置晶粒與該第二複數裝置晶粒。
  6. 如申請專利範圍第1項的方法，其中該混合接合包括：接合該第一複數裝置晶粒的第一接合墊至該第二複數裝置晶粒的第二接合墊；以及接合該第一複數裝置晶粒的第一表面介電層至該第二複數裝置晶粒的第二表面介電層，且該方法進一步包括形成環繞該第一接合墊的空氣間隙。
  7. 一種三維晶片堆疊的方法，其包括：置放一第一複數裝置晶粒於一載體上方，其中在置放該第一複數裝置晶粒於該載體上方之前，該第一複數裝置晶粒彼此分開；形成複數貫穿通路於一晶圓的第二複數裝置晶粒上；對準該載體上的該第一複數裝置晶粒與該第二複數裝置晶粒；經由混合接合，接合該第一複數裝置晶粒至該第二複數裝置晶粒，其中該複數貫穿通路延伸至該第一複數裝置晶粒之間的空間；自該第一複數裝置晶粒，剝離該載體；囊封該第一複數裝置晶粒於一囊封材料中；進行一平坦化，以使該第一複數裝置晶粒、該囊封材料、以及該複數貫穿通路齊平；以及形成一互連結構於該第一複數裝置晶粒與該囊封材料上方。
  8. 如申請專利範圍第7項的方法，其中該混合接合包括：預接合該第一複數裝置晶粒至該第二複數裝置晶粒；以及退火該第一複數裝置晶粒與該第二複數裝置晶粒，以形成該混合接合。
  9. 如申請專利範圍第8項的方法，其中在該第一複數裝置晶粒與該 載體上皆進行該退火。
  10. 一種三維晶片堆疊的封裝，其包括：一第一裝置晶粒，包含一第一表面介電、一第一接合墊、及包圍該第一接合墊的一第一介電襯層；一第二裝置晶粒，包含一第二表面介電、一第二接合墊、及包圍該第二接合墊的一第二介電襯層，其中該第二裝置晶粒係位於該第一裝置晶粒上方並且經由混合接合而以該第二接合墊接合該第一接合墊的方式接合至該第一裝置晶粒；一囊封材料，其囊封該第一裝置晶粒與該第二裝置晶粒於其中；以及一互連結構，其係位於該第二裝置晶粒上方，其中該互連結構延伸超出該第一裝置晶粒與該第二裝置晶粒二者的邊緣。
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