TWI538145B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI538145B
TWI538145B TW103101573A TW103101573A TWI538145B TW I538145 B TWI538145 B TW I538145B TW 103101573 A TW103101573 A TW 103101573A TW 103101573 A TW103101573 A TW 103101573A TW I538145 B TWI538145 B TW I538145B
Authority
TW
Taiwan
Prior art keywords
die
interposer
semiconductor device
electrically connected
contact pads
Prior art date
Application number
TW103101573A
Other languages
English (en)
Other versions
TW201432871A (zh
Inventor
周正三
林志賢
陸湘台
杜榮國
謝東宏
林振華
劉醇明
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201432871A publication Critical patent/TW201432871A/zh
Application granted granted Critical
Publication of TWI538145B publication Critical patent/TWI538145B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2101—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/81895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置及其製造方法。
自從積體電路的發明，半導體工業因各種電子元件(例如，電晶體、二極體、電阻器、電容器等)之積集度(integration density)的改善而經歷了持續且快速的成長。大部份而言，積集度的改善係源自於不斷的縮小最小特徵尺寸，而容許更多元件能被整合於有限的晶片空間中。
積集度的改善本質上是二維(Two-Dimensional,2D)的，因為基本上被整合的元件所佔據的體積是位於半導體晶圓的表面上。儘管微影(lithography)技術戲劇化的進步使得二維積體電路的形成大幅進步，二維上所能達成的積集有其物理限制。其中一項限制為製作所需元件的最小尺寸。另外，必須以更複雜的設計以設置更多裝置於單一晶片上。裝置數量的增加使裝置之間的內連線之數量及長度顯著的增加，這導致了額外的限制。當內連線之數量及長度增加，電路阻容(RC)延遲與電力消耗也增加。
為了嘗試更進一步地增加積集度，開發出三維積體電路(Three-Dimensional Integrated Circuit,3DIC)。在一個典型的三維積體電路中，至少兩個晶粒或晶圓被互相接合，且 在基底上的各晶粒與接觸墊之間形成有電性連接。舉例來說，一種三維積體電路的嘗試包含將兩個晶粒或晶圓互相接合於彼此的頂部上。接著，接合互相堆疊的晶粒至一封裝基底，且以接合線(wire bonds)或焊接凸塊(solder bumps)將各晶粒上的接觸墊電性連接至封裝基底上的接觸墊。
另一種三維封裝係使用堆疊式封裝(Package-on-Package,PoP)或中介片(interposer)技術於堆疊的晶粒，以降低形狀因素(form factor)。PoP通常包括設置一封裝晶粒於另一封裝晶粒上，其中該些晶粒係以焊接凸塊電性連接。底部的晶粒則電性連接至封裝基底。然而，PoP封裝不易降低形狀因素。除此之外，現有利用中介片作為封裝基底的技術依然被其似二維(still 2D-like，亦稱為2.5D)的特徵所侷限，而使其不容易將x-y尺寸最小化。
本發明一實施例提供一種半導體裝置，包括：一第一晶粒，其包括一第一主動表面與相對於第一主動表面的一第一背側表面；一第二晶粒，其包括一第二主動表面與相對於第二主動表面的一第二背側表面；一中介片，第一晶粒的第一主動表面電性連接至中介片的一第一側，第二晶粒的第二主動表面電性連接至中介片的一第二側；一第一連接器，於中介片上方；一第一封裝材料，圍繞第二晶粒，第一封裝材料具有位於中介片上方的一第一表面；以及一導孔，電性連接至第一連接器與中介片，其中導孔之一第一端大抵上與第一封裝材料之第一表面共平面。
本發明另一實施例提供一種半導體裝置，包括：一第一晶粒，其包括一第一表面與一第二表面，第一表面包括多個接觸墊，第二表面相對於第一表面；一第二晶粒，其包括一第三表面與一第四表面，第三表面包括多個接觸墊，第四表面相反於第三表面，第一表面電性連接至第三表面；一封裝材料，圍繞第二晶粒，封裝材料之一表面大抵上與第四表面共平面；一介電層，於第四表面與封裝材料之表面上方；多個連接器，於介電層上方；以及一第一導孔，於封裝材料中，第一導孔連接連接器至少其一與第一晶粒。
本發明又一實施例提供一種半導體裝置的製造方法，包括：將一第一晶粒接附至一中介片的一第一側；以一第一封裝材料封裝第一晶粒；將一第二晶粒接附至中介片的一第二側；以一第二封裝材料封裝第二晶粒；形成一第一導孔於第二封裝材料中，第一導孔具有連接至中介片的一第一端；以及形成多個連接器於第二晶粒與第二封裝材料上方，連接器至少其一連接至導孔的一第二端。
10、20、30‧‧‧半導體裝置
100‧‧‧第一晶粒
110‧‧‧第一組接觸墊
112‧‧‧第二組導電凸塊
120‧‧‧第二組導電接點
130、250‧‧‧底膠材料
140、360‧‧‧塑型化合物
200‧‧‧中介片
210、310‧‧‧接觸墊
220‧‧‧基底穿孔
230‧‧‧內連線
232‧‧‧第三組接觸墊
234、330‧‧‧介電層
240‧‧‧第二組導電接點
300‧‧‧第二晶粒
320‧‧‧導孔
340‧‧‧重分佈層
350‧‧‧第一組導電連接器
500‧‧‧方法
212‧‧‧第一組導電凸塊
312‧‧‧第四組導電凸塊
336‧‧‧第三組導電凸塊
第1圖根據一實施例繪示出半導體裝置之剖面示意圖。
第2圖根據一實施例繪示出用以製造半導體裝置的方法之流程圖。
請參照第3~12圖根據一實施例繪示出形成半導體裝置的中間階段。
第13圖根據另一實施例繪示出半導體裝置的剖面示意圖。
第14圖根據又一實施例繪示出半導體裝置的剖面示意圖。
以下將會配合圖式對本發明實施例作出詳述。本說明書儘可能地在圖式與說明書中使用相同的參考數字對應到相同或相似的部件。在圖式中，為了清楚及方便性而擴大形狀及厚度。以下說明將特別針對本發明實施例之裝置或是其中元件的形成部分。可以理解的是未特別繪示或說明的元件可具有各種習知的型式。任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作替代與潤飾。
本說明書全文中所提及關於”一實施例”的意思是指有關於本實施例中所提及特定的特徵(feature)、結構、或特色係包含於本發明的至少一實施例中。因此，本說明書全文中各處所出現的”在一實施例中”用語所指的並不全然表示為相同的實施例。再者，特定的特徵、結構、或特色能以任何適當方式而與一或多個實施例作結合。可以理解的是以下的圖式並未依照比例繪示，而僅僅提供說明之用。
以下將敘述與特定內容有關的實施例，即晶圓級封裝，其包括中介片(interposer)與接合至中介片的雙面(double-sided)晶粒。然而，其他實施例亦可應用於含有封裝基底的晶圓級封裝、或不含有封裝基底或中介片而含有互相接合的晶粒之晶圓級封裝。
第1圖根據本發明不同實施例繪示出半導體裝置10。半導體裝置10包括中介片200，中介片200具有透過第一組導電接點(joint)120而接附於中介片200之第一側的第一晶 粒100、以及透過第二組導電接點240而接附於中介片200之第二側的第二晶粒300。第一組導電接點120與第二組導電接點240可包括，例如，直徑為約5~50um的微凸塊(microbumps)。半導體裝置10進一步包括於封裝(encapsulating)材料360中的多個導孔(via)320。導孔320可在中介片200與一組導電連接器(connector)350之間提供電性連接，導電連接器350又可連接至其它半導體裝置、封裝基底、或印刷電路板(PCB)(未顯示)。
中介片200可由半導體材料所形成，例如，矽、鍺化矽(silicon germanium)、碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、或其他常用的半導體材料。除此之外，中介片200可由介電材料所形成，例如，玻璃、氧化鋁、氮化鋁等、或前述之組合。中介片200大抵上不具有包括主動裝置(例如，電晶體與二極體)的積體電路裝置。再者，中介片200可包括、或不包括被動裝置，例如，電容器、電阻器、電感器(inductors)、變容器(varactors)等、或前述之組合。
中介片200中的基底穿孔(through substrate via,TSV)220與接觸墊210在第一晶粒100與第二晶粒300之間提供電性連接，亦藉由內連線(interconnects)230、導孔320、以及重分佈層(redistribution layer,RDL)340的方式而在導電連接器350與第一晶粒100及/或第二晶粒300之間提供電性連接。該組導電連接器350連接至RDL 340，且在RDL 340、第二晶粒300與封裝材料360之間具有一選擇性(optional)介電層330。
第一晶粒100與第二晶粒300可為任何適用於特定應用的晶粒。舉例來說，第一晶粒100與第二晶粒300其中一者可為記憶晶片，例如，DRAM、SRAM、及/或NVRAM等，而另一者則為邏輯晶片。第一晶粒100包括第一組接觸墊110，用以透過第一組導電接點120在第一晶粒100與TSV 200之間提供電性連接，以及透過第二組導電接點240在第二晶粒300、TSV 220與內連線230之間提供電性連接。
第一晶粒100與第二晶粒300兩者皆在晶粒與中介片200之間可具有底膠(underfill)材料(底膠130與250)。此外，可在元件上方形成封裝(encapsulating)材料(140與360)以防止元件受到環境影響與外在汙染物。
第2圖根據一實施例繪示出用以製造半導體裝置的方法500之流程圖。儘管以下係以一系列的動作與事件闡明及敘述方法500，應理解的是，這些動作與事件的順序不受限於特定的實施例。舉例來說，除了下述的順序，某些動作可以不同順序執行、或是可與其它動作或事件同時進行。此外，並不需要所有闡明的動作以執行本發明一或多種面向、或實施例。再者，以下描述的一或多個動作可在一或多個獨立的動作及/或階段進行。
在步驟502，第一晶粒100接附至中介片200的第一側。如下述，步驟502繪示於第3圖與第4圖中。
請參照第3圖，其根據一實施例顯示出中介片200。在一實施例中，中介片200包括基底、接觸墊210、以及TSV 220。大體而言，中介片200相似於用以形成晶粒的摻雜 矽(doped silicon)基底。儘管中介片200可由其他材料形成，使用矽基底作為中介片被認為可降低應力，這是因為矽中介片與典型形成晶粒的矽之間的熱膨脹係數(coefficient of thermal expansion,CTE)之失配(mismatch)小於使用其他材料形成的中介片。
在隨後的製作步驟中完成的TSV 200在中介片200之第一側上的接觸墊210與中介片200之第二側上的接觸墊210之間提供電性傳導路徑。可由任何合適的方法形成TSV 200。舉例來說，可藉由，例如，一或多道蝕刻製程、研磨(milling)、或雷射技術等，而形成延伸至基底206之中的開口。在一實施例中，可形成深度為約30~300um、與寬度危3~30um的開口。可使用擴散阻障(diffusion barrier)層、接著層、及/或隔離層等內襯(line)開口，並以導電材料填充開口。舉例來說，擴散阻障層可包括一或多層的TaN、Ta、TiN、Ti、或CoW等，而導電材料可包括，例如，銅、鎢、鋁、銀、及/或前述之組合等。可藉由電化學電鍍(electro-chemical plating)製程形成導電材料，進而形成TSV 220。隔離層可包括，例如，SiOx、SiNx等、或前述之組合。
接觸墊210係形成於中介片200的基底上。一些實施例中，在TSV 220與接觸墊210之間有內連線結構(未顯示)，內連線結構包括一或多個介電層、以及介電層中的金屬線與導孔。在一些實施例中，接觸墊210為重分佈線(redistribution line,RDL)。接觸墊210可包括鋁、金、銅等、或前述之組合。
接著，在中介片200之第一側上形成第一組導電凸塊212，第一組導電凸塊212電性連接至TSV 220與接觸墊210。一些實施例中，導電凸塊212為焊接(solder)凸塊，例如，共熔(eutectic)焊接凸塊。另一些實施例中，導電凸塊212為銅凸塊或由金、銀、鎳、鎢、鋁等、或前述之組合所形成的其他金屬凸塊，且導電凸塊212可包括在金屬柱(pillar)與阻障層上方的焊接凸塊結構。
第一晶粒100可為裝置晶粒(device die)，其包括基底電路裝置形成於其中，例如，電晶體、電容器、電感器、電阻器等(未顯示)。此外，第一晶粒100可為邏輯晶粒，其包括核心電路(core circuit)，且其可為，例如，中央處理單元(central processing unit,CPU)晶粒。一些實施例中，第一晶粒100可包括多重堆疊(multiple stacked)晶粒，如記憶堆疊(memory stacking)。在第一晶粒上的接觸墊110可相似於上述的接觸墊210，因此在此不再贅述。此外，形成於接觸墊110上方的第二組導電凸塊112可相似於上述的第一組導電凸塊212，因此在此不再贅述。
第一晶粒100具有主動表面，主動表面包括接合至中介片200之第一側的第一組導電凸塊112。第一組導電凸塊212與第二組導電凸塊112之間的接合可為焊料接合(solder bonding)或直接金屬對金屬接合(direct metal-to-metal bonding)(例如，銅對銅或錫對錫)。一實施例中，第一晶粒可藉由迴焊(reflow)製程而接附至中介片，迴焊製程係在溫度為約200~300℃下進行約10分鐘。在回焊製程期間，第一組導電 凸塊212與第二組導電凸塊112接觸，以形成第一組導電接點120(請參見第4圖)。
第4圖繪示出第一晶粒100以第一組導電接點120接附至中介片200。一些實施例中，導電接點120之高度為約10~60um。可視情況地在第一晶粒100與中介片200之間的間隙注入或形成底膠材料130。底膠材料130可包括，例如，液態環氧樹脂(epoxy)、可塑形(deformable)的膠、或矽橡膠(silicon rubber)等，且底膠材料130分佈於第一晶粒100與中介片200之間，接著固化(cure)底膠材料130以使其硬化。此外，底膠材料130係用以減少第一組導電接點120的破裂(cracking)以及防止接點遭受到汙染物。
在步驟504中，封裝(encapsulate)第一晶粒100。如下述，步驟504繪示於第5圖中。
請參照第5圖，塑型化合物(molding compund)140(又稱為封膠(encapsulating)材料)成型於第一晶粒100與中介片200上。塑型化合物140之頂表面可高於或齊平於第一晶粒100的頂表面。一些實施例中，取決於第一晶粒100的厚度，塑型化合物140的厚度為約300~800um。另一些實施例中，可省略塑型化合物140與底膠材料130，且第一晶粒100可接附至載體基底(未顯示)。
在步驟506中，薄化中介片200的背側。如下述，步驟506繪示於第6圖中。
第6圖繪示出在中介片200之背側上進行薄化製程以暴露出TSV 220。薄化製程可藉由使用蝕刻製程及/或平坦 化(planarization)製程而進行，例如，化學機械研磨(chemical mechanical polishing,CMP)製程。TSV 200可從中介片200凸出(protrude)，或大抵上與中介片200共平面。舉例來說，可在最初執行平坦化製程(例如CMP)以暴露出TSV 220的襯層(liner)。在此之後，可進行一或多道對襯層與中介片具有高蝕刻率選擇比(etch-rate selectivity)的濕蝕刻製程，進而產生從中介片200之背側凸出的TSV 200(如第7圖所示)。在實施例中，中介片200包括矽，而蝕刻製程可為，例如，使用HBr/O2、HBr/Cl2/O2、SF6/CL2、SF6電漿等的乾蝕刻製程。
在步驟508中，第二晶粒接附至中介片的第二側。如下述，步驟508繪示於第7圖與第8圖中。
在凹蝕中介片200之背側後，如第7圖所示，可在中介片200之第二側(又稱為背側)上形成介電層234，其中中介片200的第二側與中介片200的第一側相對。介電層234可形成於中介片200上，其中介電層234可為低溫聚亞醯胺(polyimide)層，或可為任何習知的介電材料(例如，旋塗式玻璃(spin-on glass)、氧化矽、氮化矽、氮氧化矽等、或前數之組合)。亦可使用化學氣相沉積(chemical vapor deposition,CVD)形成介電層234。當使用低溫聚亞醯胺時，藉電層234亦可作為應力緩衝層。
可在介電層234上方形成第三組接觸墊232，第三組接觸墊232電性連接至TSV 200。一些實施例中，在TSV 220與接觸墊232之間有內連線結構(未顯示)，內連線結構包括一或多個介電層、以及介電層中的金屬線與導孔。接觸墊210可 包括鋁、金、銅等、或前述之組合。
也可在介電層234上方形成一組內連線230。內連線230可相似於上述的第三組接觸墊232，因此在此不再贅述。然而，內連線230不必相同於接觸墊232。內連線230將中介片200、第一晶粒100、及/或第二晶粒300電性連接至隨後形成的導孔320，而導孔320可連接至導墊連接器350。
接著，在中介片200的第二側上形成第三組導電凸塊236，第三組導電凸塊236電性連接至TSV 220、接觸墊232以及內連線230。第三組導電凸塊236可相似於上述的第一與第二組導電凸塊112與212，因此在此不再贅述。然而，第一、第二與第三組導電凸塊112、212與236不需相同。
第二晶粒300可為裝置晶粒，其包括積體電路裝置，例如，電晶體、電容器、電感器、電阻器等(未顯示)。第二晶粒300與第一晶粒100可為不同種的晶粒。舉例來說，第一晶粒可為邏輯晶粒，例如CPU晶粒，而第二晶粒300可為記憶晶粒。一些實施例中，第二晶粒300可包括複合堆疊(multiple stacked)晶粒。第二晶粒300上的接觸墊310可相似於上述的接觸墊220與232，因此在此不再贅述。此外，形成於接觸墊310上的第四組導電凸塊312可相似於上述的第一、第二與第三組導電凸塊112、212與236，因此在此不再贅述。
第二晶粒300具有主動表面，主動表面包括接合至中介片200之第二側的第三組導電凸塊236。第三組導電凸塊236與第四組導電凸塊312之間的接合可為焊料接合(solder bonding)或直接金屬對金屬接合(direct metal-to-metal bonding)(例如，銅對銅)。一些實施例中，第二晶粒300可藉由迴焊(reflow)製程而接附至中介片，迴焊製程係在溫度為約200~300℃下進行約10分鐘。在回焊製程期間，第三組導電凸塊236與第四組導電凸塊312接觸，以形成第二組導電接點240(請參見第8圖)。
第8圖繪示出第二晶粒300以第二組導電接點240接附至中介片200。一些實施例中，第二組導電接點240之高度為約10~60um。可視情況地在第二晶粒300與中介片200之間的間隙注入或形成底膠材料250。底膠材料250可包括，例如，液態環氧樹脂(epoxy)、可塑形(deformable)的膠、或矽橡膠(silicon rubber)等，且底膠材料250分佈於第二晶粒300與中介片200之間，接著固化(cure)底膠材料250以使其硬化。此外，底膠材料250係用以減少第二組導電接點240的破裂(cracking)以及防止接點遭受到汙染物。
在步驟510，導孔形成於中介片之第二側上的墊。如下述，步驟510繪示於第9圖中。
第9圖繪示出形成導孔320於內連線230。導孔320將隨後形成的導電連接器350(參見第12圖)電性連接至內連線230，導孔320可包括利用傳統的打線技術接合至內連線230的導線。導線可包括銅、鋁、金、鎢、鎳等、或前述之組合，且導孔之直徑為約0.5~3密耳(mil)。一些實施例中，可在以塑型化合物360(參見第11圖)封裝第二晶粒後形成導孔320，可藉由在塑型化合物中以溼蝕刻、乾蝕刻、雷射鑽孔(laser drilling)、或前述之組合等方式形成開口，再以導電材料(例 如，銅、鋁、金、鎢、鎳等、或前述之組合)填入開口中而形成導孔320。導孔320之頂表面可高於、或齊平於第二晶粒300的頂表面。
在步驟512中，封裝(encapsulate)第二晶粒。如下述，步驟504繪示於第10圖與第11圖中。
第10圖繪示出塑型化合物(molding compund)360(又稱為封膠(encapsulating)材料)成型於第二晶粒300、導孔320、與中介片200上。塑型化合物360之頂表面可高於或齊平於第二晶粒300及/或導孔320的頂表面。一些實施例中，取決於第二晶粒300的厚度與導孔320的深度，塑型化合物360的厚度為約300~800um。
在塑型化合物360的頂表面高於第二晶粒300及/或導孔320的頂表面的實施例中，可薄化塑型化合物360的頂表面以暴露出導孔320(如第11圖所示)。可使用蝕刻製程及/或平坦化製程進行薄化，例如，研磨(grinding)製程。導孔320可從塑型化合物360凸出(protrude)，或大抵上與塑型化合物360共平面。
在步驟514中，連接器形成於第二晶粒與導孔上方。如下述，步驟514繪示於第12圖中。
第12圖繪示出選擇性(optional)介電層330、RDL 340、與連接至RDL 340的導電連接器350之形成。選擇性介電層330可形成於第二晶粒300之頂表面與塑型化合物360的頂表面上方。在塑型化合物360殘留於第二晶粒300的頂表面上方的實施例中，可省略介電層330(參見第11圖)。介電層330 可為低溫聚亞醯胺(polyimide)層，或可為任何習知的介電材料(例如，旋塗式玻璃(spin-on glass)、氧化矽、氮化矽、氮氧化矽等、或前述之組合)。亦可使用化學氣相沉積(chemical vapor deposition,CVD)形成介電層330。當使用低溫聚亞醯胺時，藉電層330亦可作為應力緩衝層。
RDL 340可形成於介電層330上方且電性連接至導孔320。RDL 340可由任何合適的導電材料所形成，例如，銅、銅合金、鋁、銀、金等、或前述之組合，並由任何合適的技術形成，例如，電化學電鍍(electro-chemical plating,ECP)、無電電鍍(electroless plating)、其他沉積製程(如濺鍍、印刷、CVD)等。一些實施例中，在RDL 340與導孔320之間的介電層中可具有內連線結構(未顯示)，內連線結構包括一或多個介電層、金屬線與導孔。
接著，可在RDL 340上方形成導電連接器350，且一些導電連接器350可透過RDL 340而電性連接至導孔320。導電連接器350可由共熔(eutectic)焊料、或無鉛焊料等所形成。可由任何合適的方法形成導電連接器350，例如，倒晶封裝法(Controlled Collapse Chip Connection,C4)、或球格陣列(ball grid array,BGA)等。一些實施例中，RDL 340可包括底凸塊金屬層(under bump metallization,UBM)，且導電連接器350可形成UBM上方。
經發現，上述實施例可降低晶粒與中介片之間的應力。應力的降低部份原因是因為將第一晶粒100、中介片200與第二晶粒300之間的熱膨脹係數失配(CTE mismatch)最小 化。此外，在上述實施例中，不需在晶粒中形成TSV，因此晶粒可維持自身的電晶體及/或二極體的品質，且不必承受形成TSV產生的應力。再者，在上述實施例中，半導體裝置不包括封裝基底，且在製程期間不需要使用載體基底，因此可以降低裝置的尺寸與成本。
第13圖繪示出包括封裝基底400的半導體裝置20。此實施例相似於上述實施例，其差異在於此結構包括第一晶粒100與中介片200，而第二晶粒300係接附(attach)至封裝基底400並以導線380連接至封裝基底400。此實施例的形成方法相似於上述實施例，其差異在於第二晶粒300之頂表面係接附至封裝基底，且導線380係接合至中介片上的內連線230以及封裝基底400。在封裝基底上方，第一晶粒100、中介片200、第二晶粒300與導線380全以塑型化合物140封裝(encapsulate)。
第14圖繪示出包括第一晶粒100直接地接附至第二晶粒300的半導體裝置30。此實施例的形成方法相似於上述實施例，其差異在於第一晶粒100與第二晶粒300之間不具有中介片，而是直接地互相接合。此接合製程相似於上述由第一晶粒100上的第一組導墊凸塊與第二晶粒300上的第二組導電凸塊而形成的第一組導電接點120所使用的迴焊製程。導孔320將第一晶粒100上的內連線230電性連接至塑型化合物140與第二晶粒300之頂表面上的RDL 340。
經發現，上述實施例可縮小半導體裝置的整體尺寸。此外，在上述實施例中，可減少製程步驟，並減少元件的 數量，進而降低裝置的成本。
然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
10‧‧‧半導體裝置
100‧‧‧第一晶粒
110‧‧‧第一組接觸墊
120‧‧‧第二組導電接點
130、250‧‧‧底膠材料
140、360‧‧‧塑型化合物
200‧‧‧中介片
210、310‧‧‧接觸墊
220‧‧‧基底穿孔
230‧‧‧內連線
240‧‧‧第二組導電接點
300‧‧‧第二晶粒
320‧‧‧導孔
330‧‧‧介電層
340‧‧‧重分佈層
350‧‧‧第一組導電連接器

Claims (9)

  1. 一種半導體裝置，包括：一第一晶粒，其包括一第一主動表面與相對於該第一主動表面的一第一背側表面；一第二晶粒，其包括一第二主動表面與相對於該第二主動表面的一第二背側表面；一中介片，該第一晶粒的該第一主動表面電性連接至該中介片的一第一側，該第二晶粒的該第二主動表面電性連接至該中介片的一第二側；一第一連接器，於該中介片上方；一第一封裝材料，圍繞該第二晶粒，該第一封裝材料具有位於該中介片上方的一第一表面；以及一導孔，電性連接至該第一連接器與該中介片，其中該導孔之一第一端大抵上與該第一封裝材料之該第一表面共平面，其中該導孔位於該第一封裝材料之中，且其中該導孔包括一導線，接合至該中介片之該第二側上的一內連線與該第一封裝材料上的一重分佈層，且其中該第一連接器藉由該重分佈層、該導線及該內連線電性連接至該第二晶粒。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該中介片大抵上不具有主動裝置。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該中介片包括多個基底穿孔(through substrate via,TSV)，該TSV電性連接至該第一晶粒與該第二晶粒，且其中該中介片為一 矽中介片。
  4. 一種半導體裝置，包括：一第一晶粒，其包括一第一表面與一第二表面，該第一表面包括多個接觸墊，該第二表面相反於該第一表面；一第二晶粒，其包括一第三表面與一第四表面，該第三表面包括多個接觸墊，該第四表面相反於該第三表面，該第一表面電性連接至該第三表面；一封裝材料，圍繞該第二晶粒，該封裝材料之一表面大抵上與該第四表面共平面；一介電層，於該第四表面與該封裝材料之該表面上方；多個連接器，於該介電層上方；以及一中介片，於該第一晶粒與該第二晶粒之間；一第一導孔，於該封裝材料中，該第一導孔連接該些連接器至少其一與該第一晶粒，其中該第一導孔包括一導線，接合至該中介片上的一內連線與該封裝材料上的一重分佈層，且其中該些連接器中的至少一者藉由該重分佈層、該導線及該內連線電性連接至該第二晶粒。
  5. 如申請專利範圍第4項所述之半導體裝置，其中部份的該些連接器係位於該第二晶粒上，而另一部份的該些連接器係位於該封裝材料上方。
  6. 如申請專利範圍第4項所述之半導體裝置，更包括：多個基底穿孔(TSV)位於該中介片中，該些基底穿孔將該第一晶粒的該些接觸墊電性連接至該第二晶粒的該些接觸墊； 一第一組導電接點，於該第一晶粒與該中介片之間；以及一第二組導電接點，於該第二晶粒與該中介片之間。
  7. 一種半導體裝置的製造方法，包括：將一第一晶粒接附至一中介片的一第一側；以一第一封裝材料封裝該第一晶粒；將一第二晶粒接附至該中介片的一第二側；以一第二封裝材料封裝該第二晶粒；形成一第一導孔於該第二封裝材料中，該第一導孔具有一第一端及一第二端，其中該第一端連接至該中介片上的一內連線，且該第二端連接至該第二封裝材料上的一重分佈層；以及形成多個連接器於該第二晶粒與該第二封裝材料上方，該些連接器至少其一藉由該重分佈層、該第一導孔及該內連線電性連接至該第二晶粒。
  8. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中形成該第一導孔的步驟更包括：在封裝該第二晶粒的步驟之前，將一導線接合至該中介片的該第二側；以及將該導線封裝於該第二封裝材料中，其中該導線的一端大抵上與該第二封裝材料的一表面共平面。
  9. 如申請專利範圍第7項所述之半導體裝置的製造方法，更包括：形成一基底穿孔於該中介片之中，該基底穿孔從該中介片的該第一側形成至一深度； 薄化該中介片以暴露出該基底穿孔的一端；形成多個接觸墊於該基底穿孔的每一端；以及形成一導電凸塊於每一該些接觸墊上，其中該些導電凸塊、該些接觸墊、與該基底穿孔電性連接至該第一晶粒與該第二晶粒。
TW103101573A 2013-02-04 2014-01-16 半導體裝置及其製造方法 TWI538145B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/758,665 US8970023B2 (en) 2013-02-04 2013-02-04 Package structure and methods of forming same

Publications (2)

Publication Number Publication Date
TW201432871A TW201432871A (zh) 2014-08-16
TWI538145B true TWI538145B (zh) 2016-06-11

Family

ID=51258613

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103101573A TWI538145B (zh) 2013-02-04 2014-01-16 半導體裝置及其製造方法

Country Status (3)

Country Link
US (2) US8970023B2 (zh)
KR (1) KR101504820B1 (zh)
TW (1) TWI538145B (zh)

Families Citing this family (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG130055A1 (en) * 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US20140242777A1 (en) * 2013-02-26 2014-08-28 Varughese Mathew Method for Bonding Semiconductor Devices
US9373588B2 (en) * 2013-09-24 2016-06-21 Intel Corporation Stacked microelectronic dice embedded in a microelectronic substrate
US9543373B2 (en) * 2013-10-23 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9870946B2 (en) 2013-12-31 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and method of forming same
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
KR20150091932A (ko) * 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9527723B2 (en) * 2014-03-13 2016-12-27 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming microelectromechanical systems (MEMS) package
US9881859B2 (en) * 2014-05-09 2018-01-30 Qualcomm Incorporated Substrate block for PoP package
US10468351B2 (en) * 2014-08-26 2019-11-05 Xilinx, Inc. Multi-chip silicon substrate-less chip packaging
US9318466B2 (en) * 2014-08-28 2016-04-19 Globalfoundries Inc. Method for electronic circuit assembly on a paper substrate
US9613857B2 (en) * 2014-10-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection structure and method
KR101640076B1 (ko) * 2014-11-05 2016-07-15 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨의 칩 적층형 패키지 및 이의 제조 방법
US9570322B2 (en) * 2014-11-26 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
JP6537815B2 (ja) * 2014-12-11 2019-07-03 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
JP2017503360A (ja) * 2014-12-15 2017-01-26 インテル コーポレイション オポッサム・ダイ型パッケージ・オン・パッケージ装置
WO2016099523A1 (en) * 2014-12-19 2016-06-23 Intel IP Corporation Stacked semiconductor device package with improved interconnect bandwidth
US9564416B2 (en) * 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
KR20160122022A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 인터포저를 갖는 반도체 패키지 및 제조 방법
US9786519B2 (en) * 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US10032756B2 (en) 2015-05-21 2018-07-24 Mediatek Inc. Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same
KR102505189B1 (ko) * 2015-07-22 2023-03-02 인텔 코포레이션 다층 패키지
US9786632B2 (en) 2015-07-30 2017-10-10 Mediatek Inc. Semiconductor package structure and method for forming the same
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US9773768B2 (en) * 2015-10-09 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure of three-dimensional chip stacking
US9893042B2 (en) * 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10204884B2 (en) 2016-06-29 2019-02-12 Intel Corporation Multichip packaging for dice of different sizes
US9871020B1 (en) 2016-07-14 2018-01-16 Globalfoundries Inc. Through silicon via sharing in a 3D integrated circuit
TWI628742B (zh) * 2016-07-21 2018-07-01 南亞科技股份有限公司 堆疊式封裝結構
US10366968B2 (en) * 2016-09-30 2019-07-30 Intel IP Corporation Interconnect structure for a microelectronic device
US10580757B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Face-to-face mounted IC dies with orthogonal top interconnect layers
US10607136B2 (en) 2017-08-03 2020-03-31 Xcelsis Corporation Time borrowing between layers of a three dimensional chip stack
US10600735B2 (en) 2016-10-07 2020-03-24 Xcelsis Corporation 3D chip sharing data bus
US10672743B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D Compute circuit with high density z-axis interconnects
US10593667B2 (en) 2016-10-07 2020-03-17 Xcelsis Corporation 3D chip with shielded clock lines
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10672745B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D processor
US10586786B2 (en) 2016-10-07 2020-03-10 Xcelsis Corporation 3D chip sharing clock interconnect layer
US10600691B2 (en) 2016-10-07 2020-03-24 Xcelsis Corporation 3D chip sharing power interconnect layer
US10600780B2 (en) 2016-10-07 2020-03-24 Xcelsis Corporation 3D chip sharing data bus circuit
US10672744B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D compute circuit with high density Z-axis interconnects
KR102393946B1 (ko) 2016-10-07 2022-05-03 엑셀시스 코포레이션 직접-접합된 네이티브 상호접속부 및 능동 베이스 다이
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
KR102605618B1 (ko) 2016-11-14 2023-11-23 삼성전자주식회사 이미지 센서 패키지
WO2018125061A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Stacking multiple dies having dissimilar interconnect structure layout and pitch
DE102017127920A1 (de) 2017-01-26 2018-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Erhöhte Durchkontaktierung für Anschlüsse auf unterschiedlichen Ebenen
US10134716B2 (en) * 2017-03-16 2018-11-20 Intel Corporatin Multi-package integrated circuit assembly with through-mold via
US11569176B2 (en) * 2017-03-21 2023-01-31 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing thereof
US10134677B1 (en) * 2017-05-16 2018-11-20 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10283474B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10727198B2 (en) * 2017-06-30 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
TWI624016B (zh) * 2017-08-16 2018-05-11 矽品精密工業股份有限公司 電子封裝件及其製法
EP3462486B1 (en) 2017-09-29 2021-03-24 Qorvo US, Inc. Process for making a double-sided module with electromagnetic shielding
US11610844B2 (en) 2017-10-11 2023-03-21 Octavo Systems Llc High performance module for SiP
US10622302B2 (en) 2018-02-14 2020-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Via for semiconductor device connection and methods of forming the same
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11158775B2 (en) * 2018-06-08 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
DE102018126130B4 (de) 2018-06-08 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und -verfahren
US10992100B2 (en) 2018-07-06 2021-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US20200075547A1 (en) 2018-08-31 2020-03-05 Qorvo Us, Inc. Double-sided integrated circuit module having an exposed semiconductor die
JP2020047793A (ja) * 2018-09-19 2020-03-26 株式会社東芝 半導体装置の製造方法
US12086410B1 (en) 2019-05-31 2024-09-10 Kepler Computing Inc. Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
US10886223B2 (en) * 2019-06-03 2021-01-05 Advanced Semiconductor Engineering, Inc. Semiconductor package
US11296062B2 (en) * 2019-06-25 2022-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimension large system integration
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11201467B2 (en) 2019-08-22 2021-12-14 Qorvo Us, Inc. Reduced flyback ESD surge protection
US11599299B2 (en) 2019-11-19 2023-03-07 Invensas Llc 3D memory circuit
US11227837B2 (en) * 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
CN111128994A (zh) * 2019-12-27 2020-05-08 华为技术有限公司 一种系统级封装结构及其封装方法
US11521959B2 (en) * 2020-03-12 2022-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Die stacking structure and method forming same
DE102020119293A1 (de) 2020-03-12 2021-09-16 Taiwan Semiconductor Manufacturing Co., Ltd. Die-stapelstruktur und verfahren zum bilden derselben
TWI766280B (zh) * 2020-05-14 2022-06-01 南茂科技股份有限公司 晶圓級晶片尺寸封裝結構及其製造方法
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11574890B2 (en) * 2020-07-01 2023-02-07 Amkor Technology Singapore Holding Pte. Lte. Semiconductor devices and methods of manufacturing semiconductor devices
US11784151B2 (en) * 2020-07-22 2023-10-10 Qualcomm Incorporated Redistribution layer connection
KR20220052612A (ko) * 2020-10-21 2022-04-28 삼성전자주식회사 반도체 패키지
US11817426B2 (en) * 2021-01-13 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of fabricating the same
US11735544B2 (en) 2021-01-13 2023-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages with stacked dies and methods of forming the same
US11791326B2 (en) 2021-05-10 2023-10-17 International Business Machines Corporation Memory and logic chip stack with a translator chip
US11769712B2 (en) * 2021-05-28 2023-09-26 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204562B1 (en) * 1999-02-11 2001-03-20 United Microelectronics Corp. Wafer-level chip scale package
TW417839U (en) * 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
JP3772066B2 (ja) * 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
KR100636259B1 (ko) * 2001-12-07 2006-10-19 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
US7314781B2 (en) * 2003-11-05 2008-01-01 Lsi Corporation Device packages having stable wirebonds
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR101313391B1 (ko) * 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
KR100840788B1 (ko) * 2006-12-05 2008-06-23 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
KR100891537B1 (ko) 2007-12-13 2009-04-03 주식회사 하이닉스반도체 반도체 패키지용 기판 및 이를 갖는 반도체 패키지
KR100961310B1 (ko) 2008-02-25 2010-06-04 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US7863755B2 (en) * 2008-03-19 2011-01-04 Stats Chippac Ltd. Package-on-package system with via Z-interconnections
TWI362732B (en) * 2008-04-07 2012-04-21 Nanya Technology Corp Multi-chip stack package
KR101011840B1 (ko) 2008-11-14 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그의 제조 방법
US8119447B2 (en) * 2009-06-17 2012-02-21 Stats Chippac Ltd. Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8446017B2 (en) * 2009-09-18 2013-05-21 Amkor Technology Korea, Inc. Stackable wafer level package and fabricating method thereof
US8008121B2 (en) * 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
TWI401753B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
US8455995B2 (en) * 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
US8411459B2 (en) 2010-06-10 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd Interposer-on-glass package structures
US8642381B2 (en) * 2010-07-16 2014-02-04 Stats Chippac, Ltd. Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die
US8884431B2 (en) * 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
TWI416679B (zh) * 2010-12-06 2013-11-21 Ind Tech Res Inst 半導體結構及其製造方法
US8716859B2 (en) * 2012-01-10 2014-05-06 Intel Mobile Communications GmbH Enhanced flip chip package
US8372741B1 (en) * 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8889484B2 (en) * 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package

Also Published As

Publication number Publication date
US8970023B2 (en) 2015-03-03
KR20140099806A (ko) 2014-08-13
US20140217604A1 (en) 2014-08-07
US20150162220A1 (en) 2015-06-11
KR101504820B1 (ko) 2015-03-20
US10269586B2 (en) 2019-04-23
TW201432871A (zh) 2014-08-16

Similar Documents

Publication Publication Date Title
TWI538145B (zh) 半導體裝置及其製造方法
US11018073B2 (en) Heat spreading device and method
US11189603B2 (en) Semiconductor packages and methods of forming same
TWI642157B (zh) 半導體封裝件及其形成方法
US20230170320A1 (en) Packaged Semiconductor Device and Method of Forming Thereof
US10867885B2 (en) Heat spreading device and method
TWI683410B (zh) 半導體封裝及其形成方法
US11810831B2 (en) Integrated circuit package and method of forming same
TW201916304A (zh) 半導體封裝
KR102309989B1 (ko) 집적 회로 패키지 및 이의 형성 방법
US8647924B2 (en) Semiconductor package and method of packaging semiconductor devices
US20140210080A1 (en) PoP Device
TW201737431A (zh) 晶片封裝體
TW201935562A (zh) 封裝及其形成方法
KR102564124B1 (ko) 집적 회로 패키지 및 그 형성 방법
TW201727775A (zh) 堆疊式半導體元件的製造方法
TWI776646B (zh) 積體電路封裝體及其形成方法
US20230029098A1 (en) Semiconductor package
TW202407904A (zh) 積體電路封裝及其形成方法
TW202329377A (zh) 半導體封裝及其製造方法