TWI683410B - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

Info

Publication number
TWI683410B
TWI683410B TW107123828A TW107123828A TWI683410B TW I683410 B TWI683410 B TW I683410B TW 107123828 A TW107123828 A TW 107123828A TW 107123828 A TW107123828 A TW 107123828A TW I683410 B TWI683410 B TW I683410B
Authority
TW
Taiwan
Prior art keywords
polymer material
die
forming
semiconductor package
layer
Prior art date
Application number
TW107123828A
Other languages
English (en)
Other versions
TW201924014A (zh
Inventor
游濟陽
陳海明
李建勳
鄭榮偉
梁裕民
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201924014A publication Critical patent/TW201924014A/zh
Application granted granted Critical
Publication of TWI683410B publication Critical patent/TWI683410B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種實施例方法包含將半導體晶粒包封在包封體中，對所述包封體平面化平坦化，以及將聚合物材料沈積於所述包封體上。所述方法更包含對所述聚合物材料平坦化以及在所述聚合物材料上形成金屬化圖案。所述金屬化圖案將所述半導體晶粒之晶粒連接件電性連接至配置在所述半導體晶粒之外部的導電構件。

Description

半導體封裝及其形成方法
本發明實施例是有關於半導體封裝及其形成方法。
半導體產業因為多種電子組件(例如電晶體、二極體、電阻器、電容器等)的積集度(integration density)正在進行改良而經歷快速發展。主要地，積集度的改良源自於最小特徵尺寸的迭代減小，其允許更多組件集成至給定區域中。隨著對於縮小的電子元件的需求增長，已出現對於更小且更具創造性的半導體晶粒的封裝技術的需求。此等封裝系統之一實例為疊層封裝(Package-on-Package；PoP)技術。在PoP元件中，頂部半導體封裝堆疊於底部半導體封裝之頂部上，以提供高積集度以及高組件密度。PoP技術實質上能夠在印刷電路板(printed circuit board；PCB)上使半導體元件的生產具有增強的功能性以及小的佔據面積。
本發明實施例的半導體封裝的形成方法包括：將半導體晶粒包封在包封體中；對所述包封體平坦化；將聚合物材料沈積在 所述包封體上；對所述聚合物材料平坦化；以及將金屬化圖案形成於所述聚合物材料上，其中所述金屬化圖案將所述半導體晶粒之晶粒連接件電性連接至配置在所述半導體晶粒之外部的導電構件。
本發明實施例的半導體封裝的形成方法包括：配置與第二積體電路晶粒相鄰的第一積體電路晶粒；將所述第一積體電路晶粒及所述第二積體電路晶粒包封在模製化合物中，所述模製化合物包括多個填充物；對所述模製化合物平坦化以暴露所述第一積體電路晶粒之第一晶粒連接件以及所述第二積體電路晶粒之第二晶粒連接件，對所述模製化合物平坦化在所述模製化合物之頂部表面處定義出多個凹口；將聚合物材料沈積於所述模製化合物上方，所述聚合物材料配置在所述模製化合物之所述頂部表面處的所述多個凹口中；對所述聚合物材料平坦化；以及在所述聚合物材料上方形成金屬化圖案，所述金屬化圖案將所述第一晶粒連接件電性連接至所述第二晶粒連接件。
本發明實施例的半導體封裝包括積體電路晶粒、包封體、聚合物材料、雜質以及導電線。所述積體電路晶粒包括晶粒連接件。所述包封體配置在所述積體電路晶粒周圍。所述聚合物材料在所述包封體之至少一部分上方。所述雜質配置在所述聚合物材料之頂部表面處，所述雜質之材料不同於所述聚合物材料。所述導電線在所述聚合物材料上方，所述導電線將所述晶粒連接件電性連接至導電構件，且所述包封體之一部分配置在所述晶粒連接件與所述導電構件之間。
100‧‧‧載體基底
102‧‧‧釋放層
104、108、132、140、148、156‧‧‧介電層
106、138、146、154‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112‧‧‧穿孔
114、114A、114B‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧半導體基底
120‧‧‧內連線結構
122‧‧‧焊墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
130A‧‧‧填充物
130B‧‧‧中空核心
130C、604‧‧‧區域
131‧‧‧聚合物材料
133‧‧‧殘留物
160‧‧‧前側重佈線結構
162‧‧‧焊墊
162A、166A‧‧‧連接件
166‧‧‧導電連接件
170‧‧‧開口
190‧‧‧膠帶
200、500、502、504、506、550‧‧‧封裝
250‧‧‧第一封裝
300‧‧‧第二封裝
302、400‧‧‧基底
303、304、402‧‧‧接合墊
306‧‧‧穿孔
308、308A、308B‧‧‧堆疊式晶粒
310‧‧‧電線接合
312‧‧‧模製材料
314‧‧‧功能性連接件
318‧‧‧阻焊劑
600‧‧‧第一封裝區域
602‧‧‧第二封裝區域
T1、T2‧‧‧厚度
結合附圖閱讀以下詳細描述，會最佳地理解本發明之態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種構件之尺寸。
圖1、圖2、圖3、圖4A、圖4B、圖5、圖6A、圖6B、圖7A、圖7B、圖8A、圖8B、圖9A、圖9B、圖10A、圖10B、圖11A、圖11B、圖12、圖13、圖14、圖15、圖16、圖17、圖18、圖19、圖20、圖21、圖22、圖23、圖24、圖25A以及圖25B說明根據一些實施例用於形成封裝的製程期間的中間步驟之橫截面視圖。
圖26A、圖26B以及圖27說明根據一些替代實施例用於形成封裝的製程期間的中間步驟的橫截面視圖。
圖28A、圖28B、圖29A、圖29B、圖30A、圖30B、圖31A、圖31B、圖32A、圖32B、圖32C、圖33A、圖33B、圖33C、圖34A以及圖34B說明根據一些替代實施例用於形成封裝的製程期間的中間步驟的橫截面視圖。
以下揭示內容提供用於實施本發明之不同構件的許多不同實施例或實例。下文描述組件以及配置的特定實例以簡化本發明。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一構件在第二構件上方或上的形成可包含第一構件以及第二構件直接接觸地形成的實施例，且亦可包含額外 構件可在第一構件與第二構件之間形成使得第一構件與第二構件可不直接接觸的實施例。另外，本發明可在各種實例中重複參考數字及/或字母。此重複是出於簡單性及清晰性之目的，且本身並不指示所論述之各種實施例及/或組態之間的關係。
此外，諸如「在...下方(beneath)」、「在...下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」及類似者之空間相對術語可在本文中出於簡單描述而使用以描述如圖式中所說明的一個元件或構件關於另一元件或構件之關係。除了諸圖中所描繪的定向以外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
本文所論述之實施例可在特定情況下論述，亦即具有配置在包封體上之聚合物層的封裝結構(例如疊層封裝(PoP)結構)。包封體配置在一或多個積體電路晶粒以及延伸穿過包封體的導通孔(conductive via)周圍。此外，包封體可經配給、固化且隨後平坦化以暴露積體電路晶粒之接觸窗(contact)以及穿孔(through via)。然而，歸因於配置在包封體內的填充物(fillers)，所述平坦化製程可能導致模製化合物在平坦化之後具有不平(uneven)的頂部表面。此不平的頂部表面可能進一步導致形成於包封體上方的構件中的製造缺陷。舉例而言，一些填充物可能具有中空核心(hollow cores)，對這些填充物平坦化可能導致平坦化之後在模製化合物之頂部表面處產生凹點(pit)(例如，由暴露中空核心產生)。即使沒有中空核心填充物，平坦化之後模製化合物之表面紋理可能不合 需要地變粗糙。由於模製化合物之凹點以及粗糙表面，形成於模製化合物上的金屬化圖案(有時被稱為重佈線或重佈層)可能遭受製造缺陷，諸如金屬化圖案中的斷線(例如，導致斷路)及/或金屬化圖案中的橋接線(例如，導致短路)。
在各種實施例中，為後續形成金屬化圖案提供改良的表面構形，可將聚合物材料配給在模製化合物上。接著可將平坦化製程應用於聚合物材料。在一些實施例中，聚合物材料實質上可不含填充物，相較模製化合物，其使得在平坦化之後聚合物材料之上表面具有改良之光滑度。已觀察到，藉由在模製化合物之頂部表面上包含此聚合物材料，可有利地減少在模製化合物上方形成金屬化圖案之製造缺陷。
圖1至圖25說明根據一些實施例用於形成第一封裝組件的製程期間的中間步驟的橫截面視圖。圖1說明載體基底100以及形成於載體基底100上的釋放層102。說明分別用於形成第一封裝以及第二封裝的第一封裝區域600以及第二封裝區域602。
載體基底100可為玻璃載體基底、陶瓷載體基底或其類似者。載體基底100可為晶圓，使得多個封裝體可在載體基底100上同時形成。釋放層102可由聚合物基材料形成，可將其連同載體基底100一起自將在後續步驟中形成之上覆結構移除。在一些實施例中，釋放層102為在加熱時損失其黏著特性之環氧樹脂基熱釋放材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)釋放塗層。在其他實施例中，釋放層102可為在暴露於紫外線(ultra-violet；UV)光時損失其黏著特性之UV黏膠。釋放層102可配給為液體及經固化，可為層壓至載體基底100上之層壓膜，或可為 類似者。釋放層102之頂部表面可經水平化，且可具有高度共面性。
圖2至圖3說明視情況選用之背側重佈線結構110(參見圖3)以及視情況選用之穿孔112(參見圖3)之形成。在其他實施例中，可省略背側重佈線結構110以及穿孔112(參見例如圖4B及圖25B之實施例)。在圖2中，形成介電層104以及金屬化圖案106(有時被稱作重佈層106或重佈線106)。如圖2中所示，介電層104形成於釋放層102上。介電層104之底表面可與釋放層102之頂部表面相接觸。在一些實施例中，介電層104由聚合物，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯環丁烷(benzocyclobutene；BCB)或類似者形成。在其他實施例中，介電層104由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)或其類似者；或其類似者。介電層104可藉由任何可接受的沈積製程形成，諸如旋轉塗佈、化學氣相沈積(chemical vapor deposition；CVD)、層壓(lamination)、類似者或其組合。
金屬化圖案106形成於介電層104上。作為形成金屬化圖案106之實例，晶種層(未示出)形成於介電層104上方。在一些實施例中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋轉塗佈或其 類似者形成且可暴露於光線以用於圖案化。光阻劑之圖案對應於金屬化圖案106。圖案化形成貫穿光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及形成於晶種層之暴露部分上。導電材料可藉由鍍覆(plating)形成，諸如電鍍(electroplating)或無電式鍍覆(electroless plating)，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或其類似者。接著，移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦光阻劑經移除，諸如使用可接受的蝕刻製程(諸如，藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層以及導電材料之剩餘部分形成金屬化圖案106。
在圖3中，介電層108形成於金屬化圖案106以及介電層104上。在一些實施例中，介電層108由聚合物形成，聚合物可為可使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層108由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG；或其類似者。可藉由旋轉塗佈、層壓、CVD、其類似者或其組合形成介電層108。接著圖案化介電層108以形成開口來暴露金屬化圖案106之部分。圖案化可藉由可接受的製程，諸如，當介電層108為感光性材料時，藉由將介電層108暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。
介電層104以及介電層108以及金屬化圖案106可稱作背側重佈線結構110。如所說明，背側重佈線結構110包含兩個介電層104以及介電層108以及一個金屬化圖案106。在其他實施例 中，背側重佈線結構110可包含任何數目的介電層、金屬化圖案以及通孔，或可整體省略背側重佈線結構110。可藉由重複用於形成金屬化圖案106以及介電層108的製程而在背側重佈線結構110中形成一或多個額外金屬化圖案以及介電層。可在形成金屬化圖案期間藉由在介電層之下的開口中形成金屬化圖案的晶種層以及導電材料而形成通孔。通孔可因此互連且電性耦接各種金屬化圖案。在一些實施例中，可不包含背側重佈線結構110。
此外，在圖3中，形成視情況選用之穿孔112。作為形成穿孔112之實例，晶種層形成於背側重佈線結構110(若存在)上方，例如，如所示出的介電層108以及金屬化圖案106之暴露部分。在一些實施例中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。在晶種層上形成且圖案化光阻劑。光阻劑可藉由旋轉塗佈或其類似者形成且可暴露於光線以用於圖案化。光阻劑之圖案對應於穿孔。圖案化形成貫穿光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及形成於晶種層之暴露部分上。導電材料可藉由鍍覆形成，諸如電鍍或無電式鍍覆，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁，或其類似者。移除上方未形成導電材料的光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦光阻劑經移除，諸如使用可接受的蝕刻製程(諸如，藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層以及導電材料之剩餘部分形成穿孔112。在其它實施例中，可省略穿孔112(例如，參見圖4B及圖25B)。
在圖4A中，積體電路晶粒114A及114B藉由黏著劑116黏附至介電層108。如在圖4中所說明，兩個積體電路晶粒114A/114B黏附於第一封裝區域600以及第二封裝區域602之每一者中，且在其他實施例中，更多或更少積體電路晶粒114A/114B可黏附於每一區域中。舉例而言，在一實施例中，僅一個積體電路晶粒114A及/或114B可黏附於每一區域中。積體電路晶粒114A/114B可為邏輯晶粒(例如，中央處理單元、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取記憶體(static random access memory；SRAM)晶粒、混合記憶體立方體(hybrid memory cube；HMC)、寬輸入/輸出(wide input/output；wideIO)記憶體晶粒、磁電阻隨機存取記憶體(magnetoresistive random access memory；mRAM)晶粒、電阻性隨機存取記憶體(resistive random access memory；rRAM)晶粒等)、功率管理晶粒(例如，功率管理積體電路(power management integrated circuit；PMIC)晶粒)、射頻(radio frequency；RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、信號處理晶粒(例如，數位信號處理(digital signal processing；DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end；AFE)晶粒)、類似者或其組合。舉例而言，可執行相同類型功能或不同類型功能的積體電路晶粒114A/114B。在一實施例中，積體電路晶粒114A為處理器晶粒，而積體電路晶粒114B為記憶體晶粒。又，在一些實施例中，積體電路晶粒114A/114B可為不同尺寸(例如，不同高度及/或表面積)，且在其他實施例中，積體電路晶粒114A/114B可為相同尺寸(例 如，相同高度及/或表面積)。
在黏附至介電層108之前，可根據適用製造製程處理積體電路晶粒114A/114B，以在積體電路晶粒114A/114B中形成積體電路。舉例而言，積體電路晶粒114A/114B各自包含半導體基底118，諸如摻雜或未摻雜矽、或絕緣層上半導體(semiconductor-on-insulator；SOI)基底之主動層。半導體基底可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層或梯度基底。諸如電晶體、二極體、電容器、電阻器等元件可形成於半導體基底118中及/或形成於半導體基底118上，且可藉例如由半導體基底118上的一或多個介電層中的金屬化圖案形成的內連線結構120互連，以形成積體電路。
積體電路晶粒114A/114B進一步包括焊墊122(諸如鋁焊墊)，對焊墊122進行外部連接。焊墊122在被稱作積體電路晶粒114A/114B之各個主動側的物件上。鈍化膜124在積體電路晶粒114A/114B上且在焊墊122之部分上。開口貫穿鈍化膜124而至焊墊122。晶粒連接件126(諸如，導電柱(例如，包括諸如銅的金屬)在穿過鈍化膜124的開口中，且機械及電性耦接至各個焊墊122。可藉由例如鍍覆或類似者形成晶粒連接件126。晶粒連接件126電性耦接積體電路晶粒114A/114B之各個積體電路。
介電材料128在積體電路晶粒114A之主動側上，諸如在鈍化膜124及晶粒連接件126上。介電材料128側向地包封晶粒連接件126，且介電材料128與各個積體電路晶粒114A側向地共 端。介電材料128可為聚合物，諸如PBO、聚醯亞胺、BCB或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者；其類似者或其組合，且可例如藉由旋轉塗佈、層壓、CVD或類似者形成。此外，在一些實施例中，自積體電路晶粒114B省略介電材料128，以暴露晶粒連接件126之頂部表面以及側壁。在其他實施例中(未示出)，介電材料128可形成於積體電路晶粒114B之晶粒連接件周圍。
黏著劑116在積體電路晶粒114A/114B之背側上，且將積體電路晶粒114A/114B黏附至背側重佈線結構110，諸如說明中的介電層108。黏著劑116可為任何適合之黏著劑、環氧樹脂、晶粒附著膜(die attach film；DAF)或其類似者。黏著劑116可塗覆於積體電路晶粒114A/114B之背側(諸如，塗覆於各個半導體晶圓之背側)，或可塗覆於載體基底100之表面上方。可藉由諸如鋸割或切割而使積體電路晶粒114A/114B單體化，且使用例如抓放工具(pick-and-place tool)藉由黏著劑116將積體電路晶粒114A/114B黏附至介電層108。在一些實施例中(例如，如由圖4A所說明)，在將積體電路晶粒114A/114B附接至載體基底100之前將黏著劑116黏附至積體電路晶粒114A/114B之每一者。在其他實施例中(例如，如由圖4B所說明)，尤其當省略背側重佈線結構110及穿孔112時，可將黏著劑116毯式沈積至載體基底100上，以使得連續黏著劑116覆蓋載體基底100之全部。在此等實施例中，在沈積黏著劑116之後，將積體電路晶粒114A/114B置放在黏著劑116上且黏附至載體基底100。
在圖5中，包封體130形成於各種組件上。包封體130可 為模製化合物、環氧樹脂或其類似者，且可藉由壓縮成型、轉移成型或其類似者來應用。包封體130可進一步包括填充物，諸如二氧化矽或類似者(例如，填充物130A，參見圖6B)。在一些實施例中，包封體130中之一些或所有的填充物中可為中空的。包封體130可在穿孔112及積體電路晶粒114A/114B周圍以液體形式配給。在積體電路晶粒114B之晶粒連接件126之側壁為暴露的實施例中，包封體130可進一步在積體電路晶粒114B之晶粒連接件126周圍配給。舉例而言，包封體130可與積體電路晶粒114B之晶粒連接件126物理接觸。可配給包封體130以覆蓋穿孔112以及積體電路晶粒114A/114B之頂部表面。在配給包封體130之後，可執行固化製程以硬化包封體130。
在固化之後，包封體130可經歷平坦化製程(例如，機械研磨(mechanical grindig)、化學機械研磨(chemical mechanical polish；CMP)或類似者)以暴露如由圖6A所說明的穿孔112以及晶粒連接件126。圖6B說明圖6A中區域604之詳細橫截面視圖。平坦化製程的結果，包封體130之頂部表面可為不平的。包封體130之頂部表面之不平至少可部分地歸因於包封體130中的填充物的結果。舉例而言，參考圖6B，平坦化製程可暴露一或多個填充物130A之中空核心130B，其導致在包封體130之頂部表面處產生凹點。此外，即使在填充物130A具有固體核心時，平坦化亦可裂解填充物130A及/或移除填充物130A，以使得在平坦化之後包封體130之頂部表面為不平的。
在平坦化之後，聚合物材料131形成於包封體130上，如圖7A所說明。圖7B說明圖7A中區域604之詳細橫截面視圖。 聚合物材料131可包括PBO、聚醯亞胺、BCB或類似者。在一些實施例中，聚合物材料131為感光性材料。形成聚合物材料131可包括塗佈製程，諸如旋塗製程。聚合物材料131可經塗佈以填充包封體130之頂部表面處的凹點及其他凹口(depression)。聚合物材料131可進一步覆蓋晶粒連接件126及穿孔112之頂部表面。舉例而言，參考圖7B，聚合物材料131可填充填充物130A之任何暴露的中空核心130B(參見圖6B)。聚合物材料131可配給為厚度T1以提供包封體130之不平構形之充足覆蓋。在一些實施例中，聚合物層之厚度T1與填充物130A之平均直徑之比率可為至少約0.5。在一些實施例中，聚合物層之厚度T1為至少10μm。在一些實施例中，用於形成聚合物材料131連同包封體130之不平構形的塗佈製程可導致聚合物材料131之頂部表面為非平面的。舉例而言，在暴露的中空核心130B(參見圖6B)正上方的聚合物材料131之頂部表面之部分可為不平的。
在塗佈之後，可將固化製程(例如，退火)應用於聚合物材料131。在積體電路晶粒114A/114B之一或多者為溫感性(例如，記憶體晶粒)的實施例中，聚合物材料131可包括低溫聚合物，其在相對較低溫度(例如，小於約300℃)下固化，故不會損壞積體電路晶粒114A/114B。在其他實施例中，聚合物材料131可在任何適合溫度下固化。
在圖8A以及圖8B中，將平坦化製程應用於聚合物材料131以暴露晶粒連接件126以及穿孔112。圖8B說明圖8A中區域604之詳細橫截面視圖。平坦化製程進一步提供具有高平面度之頂部表面用於在包封體130以及聚合物材料131上方形成額外 構件(例如，金屬化圖案)。在一些實施例中，平坦化製程包括使用化學漿料的CMP，其以比包封體130更高的速率選擇性地移除聚合物材料131。舉例而言，化學漿料可包括氧化矽、氧化鋁、其組合或類似者。平坦化可進一步為藉由定時來決定平坦化製程之終點的定時製程。
平坦化之後，可保持填充包封體130之頂部表面中的凹點以及其他凹口的聚合物材料131之部分。此外，平坦化製程可移除聚合物材料131之其他部分，以暴露包封體130之區域(例如，圖8B中區域130C)。舉例而言，平坦化之後，聚合物材料131、包封體130、積體電路晶粒114A/114B以及穿孔112之最頂部表面實質上可為共平面的。此外，平坦化之後，聚合物材料131之厚度可發生變化，且跨越包封體130之頂部表面可在0μm至約0.1μm之範圍內。此外，平坦化製程可導致CMP殘留物(例如，殘留物133，亦被稱作雜質133)留存於聚合物材料131及/或包封體130之頂部表面上。CMP殘留物(亦被稱作雜質)為不同於聚合物材料131之材料，且CMP殘留物可包括在CMP期間使用的化學漿料之材料。舉例而言，當化學漿料包括氧化矽、氧化鋁、其組合或類似者時，CMP殘留物可同樣包括矽、鋁、氧、其組合或類似者之分子。
在圖9A至圖19中，形成前側重佈線結構160。如將在圖20中所說明，前側重佈線結構160包含介電層132、介電層140、介電層148以及介電層156，以及金屬化圖案138、金屬化圖案146以及金屬化圖案154(有時被稱作重佈線層138、重佈線層146以及重佈線層154或重佈線138、重佈線146以及重佈線 154)。
在圖9A及圖9B中，介電層132沈積在包封體130、聚合物材料131、穿孔112以及晶粒連接件126上。圖9B說明圖9A中區域604之詳細橫截面視圖。在一些實施例中，介電層132由聚合物形成，聚合物可為使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層132由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG或其類似者。介電層132之材料組成物與聚合物材料131可相同或不同。可藉由旋轉塗佈、層壓、CVD、其類似者或其組合形成介電層132。介電層132可形成與聚合物材料131及/或包封體130之界面。此外，在一些實施例中，CMP殘留物(例如，殘留物133)可配置在介電層132與聚合物材料131之間的界面處及/或配置在介電層132與包封體130之間的界面處(未明確示出)。藉由包含聚合物材料131以填充包封體130之頂部表面中的凹口，介電材料132形成於具有改良之平面度之表面上，其導致介電材料132之頂部表面亦具有相對平坦的構形。
在圖10A及圖10B中，接著，圖案化介電層132。圖案化形成開口以暴露穿孔112及晶粒連接件126之部分。圖10B說明圖10A中區域604之詳細橫截面視圖。圖案化可藉由可接受的製程，諸如，當介電層132為感光性材料時，藉由將介電層132暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。若介電層132為感光性材料，則介電層132可在曝光之後顯影(例如，經由退火來固化)。
在圖11A及圖11B中，具有通孔的金屬化圖案138形成 於介電層132上。圖11B說明圖11A中區域604之詳細橫截面視圖。作為形成金屬化圖案138之實例，晶種層(未繪示)形成於介電層132上方，且形成於穿過介電層132的開口中。在一些實施例中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋轉塗佈或其類似者形成且可暴露於光線以用於圖案化。光阻劑之圖案對應於金屬化圖案138。圖案化形成貫穿光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及形成於晶種層之暴露部分上。導電材料可藉由鍍覆形成，諸如電鍍或無電式鍍覆，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或其類似者。接著，移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦光阻劑經移除，諸如使用可接受的蝕刻製程(諸如，藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層以及導電材料之剩餘部分形成金屬化圖案138以及通孔。通孔形成於穿過介電層132至例如穿孔112及/或晶粒連接件126的開口中。在一些實施例中，金屬化圖案138為線寬為例如5μm或以下的精細間距的重佈線。在其他實施例中，金屬化圖案138可具有其他尺寸。藉由包含聚合物材料131以填充包封體130之頂部表面中的凹口，金屬化圖案138可形成於介電層132之相對平坦的頂部表面上。因此，可有利地減少金屬化圖案138(例如，破損及/或融合的導電線)中的製造缺陷。
在圖12中，介電層140沈積於金屬化圖案138以及介電 層132上。在一些實施例中，介電層140由聚合物形成，聚合物可為使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層140由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG或其類似者。可藉由旋轉塗佈、層壓、CVD、其類似者或其組合形成介電層140。
在圖13中，接著，圖案化介電層140。圖案化形成開口以暴露金屬化圖案138之部分。圖案化可藉由可接受的製程，諸如，當介電層為感光性材料時，藉由將介電層140暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。若介電層140為感光性材料，則介電層140可在曝光之後顯影。
在圖14中，具有通孔的金屬化圖案146形成於介電層140上。作為形成金屬化圖案146之實例，晶種層(未繪示)形成於介電層140上方，且形成於穿過介電層140的開口中。在一些實施例中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋轉塗佈或其類似者形成且可暴露於光線以用於圖案化。光阻劑之圖案對應於金屬化圖案146。圖案化形成貫穿光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及形成於晶種層之暴露部分上。導電材料可藉由鍍覆形成，諸如電鍍或無電式鍍覆，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或其類似者。接著，移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或 剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦光阻劑經移除，諸如使用可接受的蝕刻製程(諸如，藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層以及導電材料之剩餘部分形成金屬化圖案146以及通孔。通孔形成於穿過介電層140至例如金屬化圖案138之部分的開口中。
在圖15中，介電層148沈積於金屬化圖案146以及介電層140上。在一些實施例中，介電層148由聚合物形成，聚合物可為使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層148由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG或其類似者。可藉由旋轉塗佈、層壓、CVD、其類似者或其組合形成介電層148。
在圖16中，接著，圖案化介電層148。圖案化形成開口以暴露金屬化圖案146之部分。圖案化可藉由可接受的製程，諸如，當介電層為感光性材料時，藉由將介電層148露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。若介電層148為感光性材料，則介電層148可在曝光之後顯影。
在圖17中，具有通孔的金屬化圖案154形成於介電層148上。作為形成金屬化圖案154之實例，晶種層(未繪示)形成於介電層148上方，且形成於穿過介電層148的開口中。在一些實施例中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋轉塗佈或其類似 者形成且可暴露於光線以用於圖案化。光阻劑之圖案對應於金屬化圖案154。圖案化形成貫穿光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及形成於晶種層之暴露部分上。導電材料可藉由鍍覆形成，諸如電鍍或無電式鍍覆，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或其類似者。接著，移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦光阻劑經移除，諸如使用可接受的蝕刻製程(諸如，藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層以及導電材料之剩餘部分形成金屬化圖案154以及通孔。通孔形成於穿過介電層148至例如金屬化圖案146之部分的開口中。
在圖18中，介電層156沈積於金屬化圖案154以及介電層148上。在一些實施例中，介電層156由聚合物形成，聚合物可為使用微影罩幕圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層156由以下各者形成：氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG或其類似者。可藉由旋轉塗佈、層壓、CVD、其類似者或其組合形成介電層156。
在圖19中，接著，圖案化介電層156。圖案化形成開口以暴露金屬化圖案154之部分。圖案化可藉由可接受的製程，諸如，當介電層為感光性材料時，藉由將介電層156暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。若介電層156為感光性材料，則介電層156可在曝光之後顯影。
前側重佈線結構160繪示為一實例。較多或較少介電層 以及金屬化圖案可形成於前側重佈線結構160中。若較少介電層及金屬化圖案待形成，則可省略上文所論述之步驟及製程。若較多介電層及金屬化圖案待形成，則可重複上文所論述之步驟及製程。所屬領域中具通常知識者將容易理解哪些步驟及製程將被省略或重複。
在圖20中，焊墊162形成於前側重佈線結構160之外部側上。焊墊162用於耦接至導電連接件166(參見圖21)，且可被稱作凸塊下金屬(under bump metallurgies；UBMs)162或導電柱162(參見圖25B)。在所說明實施例中，穿過開口形成焊墊162，開口穿過介電層156至金屬化圖案154。作為形成焊墊162之一實例，晶種層(未繪示)形成於介電層156上方。在一些實施例中，晶種層為金屬層，金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方之銅層。可使用例如PVD或其類似者形成晶種層。接著在晶種層上形成及圖案化光阻劑。光阻劑可藉由旋轉塗佈或其類似者形成且可暴露於光線以用於圖案化。光阻劑之圖案對應於焊墊162。圖案化形成貫穿光阻劑之開口以暴露晶種層。導電材料形成於光阻劑之開口中及形成於晶種層之暴露部分上。導電材料可藉由鍍覆形成，諸如電鍍或無電式鍍覆，或其類似者。導電材料可包括金屬，如銅、鈦、鎢、鋁或其類似者。接著，移除上方未形成導電材料之光阻劑及部分之晶種層。可藉由可接受的灰化或剝離製程移除光阻劑，諸如使用氧電漿或其類似者。一旦光阻劑經移除，諸如使用可接受的蝕刻製程(諸如，藉由濕式或乾式蝕刻)移除晶種層之暴露部分。晶種層以及導電材料之剩餘部分形成焊墊162。在以不同 方式形成焊墊162的實施例中，可利用更多光阻劑以及圖案化步驟。
在圖21中，導電連接件166形成於焊墊162(凸塊下金屬)上。導電連接件166可為BGA連接件、焊球、焊料蓋、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection；C4)凸塊、微凸塊、化學鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold；ENEPIG)技術形成的凸塊、或類似者。導電連接件166可包含導電材料，諸如，焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，形成導電連接件166是藉由諸如蒸鍍(evaporation)、電鍍、列印、焊料轉移(solder transfer)、植球(ball placement)或類似者的此等常用方法先形成焊料層。一旦焊料層已形成於結構上，則可執行回焊以便將材料塑形成所要的凸塊形狀。在另一實施例中，導電連接件166為藉由濺鍍、列印、電鍍、無電式鍍覆、CVD或類似者所形成的金屬柱(諸如，銅柱)。金屬柱可為無焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層(未繪示)形成於導電連接件166(金屬柱連接件)之頂部上。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合，且可藉由鍍覆製程形成。
在圖22中，執行載體基底剝離以將載體基底100自背側重佈線結構(例如，介電層104)拆離(剝離)。根據一些實施例，剝離包含將諸如雷射光或UV光的光投影於釋放層102上，以使得釋放層102在光熱下分解且可移除載體基底100。接著翻轉結構且將其置放於膠帶190上。
如在圖22中進一步說明，穿過介電層104形成開口以暴 露金屬化圖案106之部分。舉例而言，可使用雷射鑽孔、蝕刻或類似者形成開口。
在圖23中，藉由沿著切割道區域(例如，在相鄰區域600與區域602之間)鋸割執行單體化製程。鋸割將第一封裝區域600自第二封裝區域602單體化。
圖23說明所得單體化封裝200，封裝200可來自第一封裝區域600或第二封裝區域602之一者。封裝200亦可稱作積體扇出型(integrated fan-out；InFO)封裝200。
圖24說明包含封裝200(可稱作第一封裝200)以及視情況選用之第二封裝300的封裝結構500。第二封裝300包含基底302以及耦接至基底302的一或多個堆疊式晶粒308(308A以及308B)。基底302可由半導體材料製成，諸如矽、鍺、金剛石或類似者。在一些實施例中，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷化鎵、磷化鎵銦、其組合或其類似者。另外，基底302可為絕緣層上矽(silicon-on-insulator；SOI)基底。通常，SOI基底包含諸如磊晶矽、鍺、矽鍺、SOI、絕緣層上矽鍺(silicon germanium on insulator；SGOI)或其組合的半導體材料層。在一個替代性實施例中，基底302是基於諸如玻璃纖維補強樹脂核心(fiberglass reinforced resin core)的絕緣核心。核心材料的一個實例為玻璃纖維樹脂，諸如FR4。核心材料之替代方案包含雙馬來醯亞胺三嗪(bismaleimide-triazine；BT)樹脂，或替代地包括其他印刷電路板(PCB)材料或膜。組成薄膜(build-up film)，諸如味之素組成薄膜(Ajinomoto build-up film；ABF)或其他疊層可用於基底302。
基底302可包含主動元件以及被動元件(圖21中未示)。如所屬領域中具通常知識者將理解到，廣泛多種元件(諸如電晶體、電容器、電阻器、其組合或類似者)可用以產生半導體封裝300的結構以及功能要求的設計。這些元件可使用任何適合的方法形成。
基底302亦可包含金屬化層(未繪示)以及穿孔306。金屬化層可形成於主動元件以及被動元件上方，且經設計以連接各種元件以形成功能電路。金屬化層可由介電材料(例如低k介電材料)與導電材料(例如銅)的交替層形成，其中通孔互連導電材料層且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或類似者)形成。在一些實施例中，基底302實質上不含主動元件以及被動元件。
基底302可在基底302之第一側上具有接合墊303以耦接至堆疊式晶粒308，且在基底302之第二側上具有接合墊304以耦接至功能性連接件314，所述第二側與基底302之第一側相對。在一些實施例中，藉由在基底302之第一側以及第二側上形成凹陷(recess)(未繪示)至介電層(未繪示)中來形成接合墊303以及接合墊304。可形成凹陷以允許接合墊303以及接合墊304嵌入於介電層中。在其他實施例中，省略凹陷，這是由於接合墊303以及接合墊304可形成於介電層上。在一些實施例中，接合墊303以及接合墊304包含由銅、鈦、鎳、金、鈀、其類似者或其組合製成的薄晶種層(未繪示)。接合墊303以及接合墊304之導電材料可沈積於薄晶種層上方。可藉由電化學電鍍製程、無電式鍍覆製程、CVD、ALD、PVD、類似者或其組合形成導電材料。在一實施例中， 接合墊303以及接合墊304之導電材料為銅、鎢、鋁、銀、金、其類似者或其組合。
在一實施例中，接合墊303以及接合墊304為包含三層導電材料層(諸如，鈦層、銅層以及鎳層)的UBM。然而，一般所屬領域中具通常知識者將理解到，存在適合形成UBM 303(接合墊303)以及UBM 304(接合墊304)的許多適合的材料及層的配置，諸如，鉻/鉻銅合金/銅/金之配置、鈦/鈦鎢/銅之配置，或銅/鎳/金之配置。可用於UBM 303(接合墊303)以及UBM 304(接合墊304)的任何適合的材料或材料層全部意欲包含於本申請案之範疇內。在一些實施例中，穿孔306延伸穿過基底302且將至少一個接合墊303耦接至至少一個接合墊304。
在所說明實施例中，堆疊式晶粒308藉由電線接合310耦接至基底302，但可使用其他連接件，諸如導電凸塊。在一實施例中，堆疊式晶粒308為堆疊式記憶體晶粒。舉例而言，堆疊式記憶體晶粒308(堆疊式晶粒308)可包含低功率(low-power；LP)雙資料速率(double data rate；DDR)記憶體模組，諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4、或類似記憶體模組。
在一些實施例中，堆疊式晶粒308以及電線接合310可由模製材料312包封。可使用例如壓縮模製將模製材料312模製於堆疊式晶粒308以及電線接合310上。在一些實施例中，模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填充物材料、其類似者或其組合。可執行固化步驟以固化模製材料312，其中固化可為熱固化、UV固化、其類似者或其組合。
在一些實施例中，堆疊式晶粒308以及電線接合310埋 入於模製材料312中，且在固化模製材料312之後，執行諸如研磨的平坦化步驟以移除模製材料312之過量部分以及為第二封裝300提供實質上平面的表面。
在形成第二封裝300之後，封裝300借助於功能性連接件314、接合墊304以及金屬化圖案106以機械及電性接合至第一封裝200。在一些實施例中，堆疊式記憶體晶粒308(堆疊式晶粒308)可經由電線接合310、接合墊303以及接合墊304、穿孔306、功能性連接件314以及穿孔112耦接至積體電路晶粒114。
功能性連接件314可類似於上文所描述的導電連接件166，且在此不再赘述，而功能性連接件314以及導電連接件166不必相同。功能性連接件314可配置在與堆疊式記憶體晶粒308(堆疊式晶粒308)的基底302之相對側上。在一些實施例中，阻焊劑318亦可形成於與堆疊式記憶體晶粒308(堆疊式晶粒308)相對的基底302之一側上。功能性連接件314可配置在阻焊劑318中之開口中以電性及機械耦接至基底302中之導電構件(例如，接合墊304)。阻焊劑318可用於保護基底302之區域不受外部損害。
在一些實施例中，在接合功能性連接件314之前，功能性連接件314塗佈有助焊劑(flux)(未繪示)，諸如免清助焊劑。功能性連接件314可浸漬於助焊劑中，或助焊劑可噴射至功能性連接件314上。在另一實施例中，助焊劑可塗覆於金屬化圖案106之表面。
在一些實施例中，在第二封裝300附接至第一封裝200之後，功能性連接件314與剩餘的環氧樹脂助焊劑的環氧樹脂部 分中之至少一些回焊之前，功能性連接件314可具有視情況選用之環氧樹脂助焊劑(未繪示)形成於其上。此剩餘環氧樹脂部分可充當底填充料以減小應力以及保護產生於回焊所述功能性連接件314的接點。
第二封裝300與第一封裝200之間的接合可為焊料接合。在一實施例中，藉由回焊製程將第二封裝300接合至第一封裝200。在此回焊製程期間，功能性連接件314與接合墊304以及金屬化圖案106接觸，以將第二封裝300物理且電性耦接至第一封裝200。在接合製程之後，介金屬化合物(intermetallic compound；IMC，未繪示)可形成於金屬化圖案106與功能性連接件314之界面處，且亦形成於功能性連接件314與接合墊304(未繪示)之間的界面處。儘管圖23及圖24說明在第一封裝200單體化之後，第二封裝300接合至第一封裝200，但在其他實施例中，第二封裝300可在單體化之前接合至第一封裝200(例如，當第一封裝200為封裝晶圓之部分時，參見圖21)。在第二封裝300接合至第一封裝200之後，第一封裝200可接著自封裝晶圓中之其他封裝單體化。
第二封裝300為視情況選用的。在其他實施例中(例如，參見圖25B)，尤其當省略背側重佈線結構110以及穿孔112時，亦可省略第二封裝300。在此等實施例中，可由積體電路晶粒114B提供封裝之記憶體組件，所述積體電路晶粒114B連同積體電路晶粒114A(例如，處理器晶粒)模製於第一封裝200中。藉由將記憶體組件以及處理器組件兩者包封於單個包封層中，可有利地減少最終封裝(例如，圖25B之封裝550)之形狀因子以及製造成 本。
圖25A說明在將封裝200及封裝300安裝至基底400之後的半導體封裝500。基底400可稱作封裝基底400。使用導電連接件166將封裝200安裝至封裝基底400。
封裝基底400可由半導體材料製成，諸如矽、鍺、金剛石或類似者。或者，亦可使用化合物材料，諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷化鎵、磷化鎵銦、其組合或其類似者。另外，封裝基底400可為SOI基底。大體而言，SOI基底包含半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合。在一個替代性實施例中，封裝基底400是基於諸如玻璃纖維補強樹脂核心的絕緣核心。核心材料的一個實例為玻璃纖維樹脂，諸如FR4。核心材料之替代方案包含雙馬來醯亞胺三嗪BT樹脂，或替代地包括其他PCB材料或薄膜。組成薄膜，諸如ABF或其他疊層可用於封裝基底400。
封裝基底400可包含主動元件以及被動元件(圖29中未示)。如本領域的技術人員將理解到，廣泛多種元件，諸如電晶體、電容器、電阻器、其組合以及類似者可用以產生半導體封裝500的結構以及功能要求的設計。這些元件可使用任何適合的方法形成。
封裝基底400亦可包含金屬化層以及通孔(未繪示)，以及在金屬化層以及通孔上方的接合墊402。金屬化層可形成於主動元件以及被動元件上方，且設計為連接各種元件以形成功能電路。金屬化層可由介電材料(例如低k介電材料)與導電材料(例如銅)的交替層形成，其中通孔互連導電材料層且可經由任何適合的製程(諸如沈積、鑲嵌、雙鑲嵌或類似者)形成。在一些實施例中， 封裝基底400實質上不含主動元件以及被動元件。
在一些實施例中，可回焊導電連接件166以將封裝200附接至接合墊402。導電連接件166將基底400(包含基底400中的金屬化層)電性及/或物理耦接至第一封裝200。在一些實施例中，可在安裝在基底400上之前將被動元件(例如，表面安裝元件(surface mount device；SMD)，未示出)附接至封裝200(例如，接合至接合墊402)。在此等實施例中，可將被動元件接合至封裝200之與導電連接件166相同的表面。
在封裝200附接至基底400之後，導電連接件166與剩餘的環氧樹脂助焊劑的環氧樹脂部分中之至少一些回焊之前，導電連接件166可具有環氧樹脂助焊劑(未繪示)形成於其上。此剩餘環氧樹脂部分可充當底填充料以減小應力以及保護產生於回焊所述導電連接件166的接點。在一些實施例中，底填充料(未繪示)可形成於第一封裝200與基底400之間且環繞導電連接件166。可在封裝200附接之後藉由毛細流動製程形成底填充料，或可在封裝200附接之前藉由適合的沈積方法形成底填充料。
亦可包含其他構件及製程。舉例而言，可包含測試結構以幫助對3D封裝或3DIC元件之驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試焊墊，從而允許3D封裝或3DIC的測試、探針及/或探針卡的使用及其類似者。驗證測試可對中間結構以及最終結構執行。另外，本文中所揭露的結構及方法可合併已知良好晶粒的中間驗證的測試方法結合使用，以提高產率及降低成本。
圖25B說明根據一些實施例的封裝550。封裝550包含 藉由連接件162A以及連接件166A接合至封裝400的第一封裝250。連接件162A以及連接件166A可為BGA球、C4凸塊或類似者。在一些實施例中，連接件162A以及連接件166A包括配置在導電柱162A(連接件162A)上的焊料蓋166A(連接件166A)。封裝550可實質上類似於封裝500(參見圖25A)，其中相同參考編號指示相同元件。然而，在封裝250，省略視情況選用之背側重佈線結構110以及穿孔112。此外，無記憶體模組(例如，類似於如圖25B中所說明的封裝300)接合至第一封裝250之與封裝400的相對側。在一些實施例中，如由上文所述之積體電路晶粒114B來提供封裝550之記憶體組件。儘管被稱作「晶粒」，積體電路晶粒114A及/或積體電路晶粒114B可為裸晶片或封裝晶片(例如，包括一或多個晶粒及/或重佈線構件)。
圖26A至圖27說明根據替代實施例的製造封裝502(參見圖27)的不同階段之橫截面視圖。參見圖26A及圖26B，描繪形成封裝502(參見圖27)之中間製程步驟。圖26B說明圖26A之區域604之詳細橫截面視圖。封裝502可實質上類似於封裝500(參見圖25A)，其中相同參考編號指示使用相同製程步驟形成的相同元件(例如，如上文關於圖1至圖11B所述)。類似於上述實施例，背側重佈線結構110及/或穿孔112為視情況選用的且可省略。然而，在封裝502中，省略介電層132(參見圖11A以及圖11B)，且金屬化圖案138直接形成於包封體130以及聚合物材料131上以電性互連積體電路晶粒114A之晶粒連接件126、積體電路晶粒114B之晶粒連接件126以及穿孔112。舉例而言，金屬化圖案138形成與包封體130以及聚合物材料131之界面。此外， 從平坦化聚合物材料131所得之CMP殘留物(所示為殘留物133)可配置在金屬化圖案138與聚合物材料131之間的界面處及/或金屬化圖案138與包封體130之間的界面處。如上文所論述，CMP殘留物(亦被稱作雜質)可包括在聚合物材料131之CMP期間使用的化學漿料之材料。舉例而言，當化學漿料包括氧化矽、氧化鋁、其組合或類似者時，CMP殘留物可同樣包括矽、鋁、氧、其組合或類似者之分子。圖27說明在例如藉由運用與上文關於圖12至圖25A相同之製程步驟之進一步處理之後的完成封裝502。在其他實施例中(例如，類似於圖25B)，尤其當省略視情況選用之背側重佈線結構110以及穿孔112時，可省略封裝300。
圖28A至圖34B說明根據替代實施例的製造封裝504(參見圖34A)及/或封裝506(參見圖34B)的不同階段的橫截面視圖。參考圖28A以及圖28B，描繪形成封裝504以及封裝506(參見圖34A以及圖34B)的中間製程步驟。圖28B說明圖28A之區域604之詳細橫截面視圖。圖28A以及圖28B之構件可實質上類似於上文關於圖6A以及圖6B說明及描述之構件，其中相同參考編號指示使用相同製程步驟形成的元件。類似於上述實施例，背側重佈線結構110及/或穿孔112為視情況選用的且可省略。
接下來，在圖29A以及圖29B中，圖案化導電通孔112以及晶粒連接件126。圖29B說明圖29A之區域604之詳細橫截面視圖。圖案化導電通孔112及晶粒連接件126可包含回蝕製程、去污製程(desmear process)、其組合或類似者以使導電通孔112及晶粒連接件126凹陷低於包封體130以及介電材料128之頂部表面。在一些實施例中，圖案化導電通孔112及晶粒連接件126移 除形成於導電通孔112及晶粒連接件126之頂部表面處的原生氧化物(例如，銅氧化物)。已觀察到，藉由移除此原生氧化物，可改良導電通孔112及晶粒連接件126之導電性。在一些實施例中，圖案化導電通孔112以及晶粒連接件126，導電通孔112以及晶粒連接件126之每一者之對應高度減小了一厚度T2(參見圖29B)，所述厚度可在約0.1μm至約20μm之範圍內。
接下來，聚合物材料131形成於如圖30A所說明之包封體130上。圖30B說明圖30A中區域604之詳細橫截面視圖。聚合物材料131可包括PBO、聚醯亞胺、BCB或類似者。在一些實施例中，聚合物材料131為感光性材料。形成聚合物材料131可包括塗佈製程，諸如旋塗製程。聚合物材料131可經塗佈以填充包封體130之頂部表面處的凹點及其他凹口。聚合物材料131可進一步填充由導電通孔112以及晶粒連接件126(參見圖29A/29B)之圖案化所定義之開口。舉例而言，聚合物材料131可進一步覆蓋晶粒連接件126以及穿孔112之頂部表面。
參考圖30B，聚合物材料131可填充填充物130A之任何暴露的中空核心130B(參見圖28B)。聚合物材料131可配給為厚度T1以提供包封體130之不平構形之充足覆蓋。在一些實施例中，聚合物層之厚度T1與填充物130A之平均直徑之比率可為至少約0.5。在一些實施例中，聚合物層之厚度T1為至少10μm。在一些實施例中，用於形成聚合物材料131連同包封體130之不平構形的塗佈製程可導致聚合物材料131之頂部表面為非平面的。舉例而言，在暴露的中空核心130B(參見圖28B)正上方的聚合物材料131之頂部表面之部分可為不平的。
接下來，在圖31A以及圖31B中，開口170在聚合物材料131中經圖案化以暴露穿孔112以及晶粒連接件126。圖31B說明圖31A中區域604之詳細橫截面視圖。圖案化可藉由可接受的製程，諸如當介電層為感光性材料時，藉由將聚合物材料131暴露於光線，或藉由使用例如非等向性蝕刻進行蝕刻。
在圖案化之後，可將固化製程(例如，退火)應用於聚合物材料131。在積體電路晶粒114A/114B之一或多者為溫感性(例如，記憶體晶粒)的實施例中，聚合物材料131可包括低溫聚合物，其在相對較低溫度(例如，小於約300℃)下固化，故不會損壞積體電路晶粒114A/114B。在其他實施例中，聚合物材料131可在任何適合溫度下固化。固化製程可硬化聚合物材料以允許用於後續處理步驟(例如，平坦化，參見圖32A、圖32B以及圖32C)的足夠硬度。儘管所述固化製程為在圖案化聚合物材料131之後執行，但在其他實施例中，固化聚合物材料131可在圖案化聚合物材料131之前執行(例如，當蝕刻製程用於圖案化聚合物材料131)。
在圖32A、圖32B以及圖32C中，平坦化製程應用於聚合物材料131。圖32B以及圖32C說明圖32A中區域604之詳細橫截面視圖。圖32B對應於根據一些實施例產生封裝504(參見圖34A)的平坦化製程。圖32C對應於根據一些替代實施例產生封裝506(參見圖34B)的平坦化製程。
平坦化製程提供具有高平面度之頂部表面用於在包封體130以及聚合物材料131上方形成額外構件(例如，金屬化圖案)。在一些實施例中，平坦化製程包括使用化學漿料的CMP，其以比 包封體130更高的速率選擇性地移除聚合物材料131。舉例而言，化學漿料可包括氧化矽、氧化鋁、其組合或類似者。平坦化可進一步為藉由定時來決定平坦化製程之終點的定時製程。
平坦化之後，可保持填充包封體130之頂部表面中的凹點以及其他凹口的聚合物材料131之部分。在一些實施例中(參見圖32B)，平坦化製程可移除聚合物材料131之其他部分，以暴露包封體130之區域(例如，圖32B中的區域130C)。舉例而言，在平坦化之後，聚合物材料131、包封體130以及介電材料128之最頂部表面可實質上為共平面的。在此等實施例中，在平坦化之後，聚合物材料131之厚度可發生變化，且跨越包封體130以及介電材料128之頂部表面可在0μm至約0.1μm之範圍內。
在其他實施例中(參見圖32C)，平坦化製程使聚合物材料131平坦化，而不暴露包封體130或介電材料128之任何部分。舉例而言，在平坦化之後，聚合物材料131充分覆蓋包封體130以及介電材料128之頂部表面。在此等實施例中，在平坦化之後，聚合物材料131之厚度可發生變化，且跨越包封體130以及介電材料128之頂部表面可在0.1μm至約30μm之範圍內。
此外，平坦化製程可導致CMP殘留物(例如，殘留物133，亦被稱作雜質133)留存於聚合物材料131及/或包封體130之頂部表面上。CMP殘留物(亦被稱作雜質)為不同於聚合物材料131之材料，且CMP殘留物可包括在CMP期間使用的化學漿料之材料。舉例而言，當化學漿料包括氧化矽、氧化鋁、其組合或類似者時，CMP殘留物可同樣包括矽、鋁、氧、其組合或類似者之分子。此外，在聚合物材料131之材料組成物內未發現CMP殘留物之材 料。
接下來，在圖33A、圖33B以及圖33C中，金屬化圖案138直接形成於聚合物材料131上以電性互連積體電路晶粒114A之晶粒連接件126、積體電路晶粒114B之晶粒連接件126以及穿孔112。圖33B以及圖33C說明圖33A中區域604之詳細橫截面視圖。圖33B對應於根據一些實施例形成產生封裝504(參見圖34A)的金屬化圖案。圖33C對應於根據一些替代實施例形成產生封裝506(參見圖34B)的金屬化圖案。
在一些實施例中(參見圖33B)，金屬化圖案138形成與包封體130、介電材料128以及聚合物材料131之界面。在此等實施例中，從平坦化聚合物材料131所得之CMP殘留物(所示為殘留物133)可配置在金屬化圖案138與聚合物材料131之間的界面處及/或金屬化圖案138與包封體130之間的界面處。如上文所論述，CMP殘留物可包括在聚合物材料131之CMP期間使用的化學漿料之材料。舉例而言，當化學漿料包括氧化矽、氧化鋁、其組合或類似者時，CMP殘留物可同樣包括矽、鋁、氧、其組合或類似者之分子。圖34A說明在例如藉由運用與上文關於圖12至圖25A相同之製程步驟之進一步處理之後的完成封裝504。在其他實施例中(例如，類似於圖25B)，尤其當省略視情況選用之背側重佈線結構110以及穿孔112時，可省略封裝300。
在一些實施例中(參見圖33C)，金屬化圖案138形成與聚合物材料131之界面，而不形成與包封體130或介電材料128之界面。在此等實施例中，從平坦化聚合物材料131所得之CMP殘留物(所示為殘留物133)可配置在金屬化圖案138與聚合物材 料131之間的界面處。如上文所論述，CMP殘留物可包括在聚合物材料131之CMP期間使用的化學漿料之材料。舉例而言，當化學漿料包括氧化矽、氧化鋁、其組合或類似者時，CMP殘留物可同樣包括矽、鋁、氧、其組合或類似者之分子。圖34B說明在例如藉由運用與上文關於圖12至圖25A相同之製程步驟之進一步處理之後的完成封裝506。在其他實施例中(例如，類似於圖25B)，尤其當省略視情況選用之背側重佈線結構110以及穿孔112時，可省略封裝300。
如上文所述之各種實施例提供額外的聚合物材料以填充及平坦化元件封裝中之包封體之不平的頂部表面。聚合物材料實質上不含填充物，相較於包括填充物的包封體，平坦化的聚合物材料具有改良的構型。已觀察到，藉由提供此聚合物材料，可減少隨後形成的構件(例如，金屬化圖案之導電線)之製造缺陷。
根據一實施例，一種方法包含：將半導體晶粒包封在包封體中；對所述包封體平坦化；將聚合物材料沈積在所述包封體上；對所述聚合物材料平坦化；以及將金屬化圖案形成於所述聚合物材料上。所述金屬化圖案將半導體晶粒之晶粒連接件電性連接至配置在半導體晶粒之外部的導電構件。在一實施例中，所述包封體包括填充物，且對包封體平坦化暴露填充物之中空核心，且其中沈積聚合物材料包括用聚合物材料填充所述中空核心。在一實施例中，所述方法更包含在聚合物材料與金屬化圖案之間形成聚合物層。在一實施例中，形成金屬化圖案包含形成與聚合物材料物理接觸的金屬化圖案。在一實施例中，所述方法更包含：圖案化第一開口穿透聚合物材料以暴露半導體晶粒之晶粒連接件；以及圖案化 第二開口穿透聚合物材料以暴露導電構件。形成所述金屬化圖案包含形成金屬化圖案之部分在第一開口及第二開口中。在一實施例中，在對聚合物材料平坦化之前執行圖案化第一開口以及圖案化第二開口。在一實施例中，在沈積聚合物材料之前，所述方法更包含使半導體晶粒之晶粒連接件凹陷低於包封體之頂部表面。在一實施例中，平坦化聚合物材料暴露包封體之一部分。
根據一實施例，一種方法包含：配置與第二積體電路晶粒相鄰的第一積體電路晶粒；將第一積體電路晶粒及第二積體電路晶粒包封在模製化合物中，所述模製化合物包括多個填充物；對所述模製化合物平坦化以暴露第一積體電路晶粒之第一晶粒連接件以及第二積體電路晶粒之第二晶粒連接件。平坦化模製化合物在模製化合物之頂部表面處定義出多個凹口。所述方法進一步包含：將聚合物材料沈積於模製化合物上方，所述聚合物材料配置在模製化合物之頂部表面處的多個凹口中；對所述聚合物材料平坦化；以及在聚合物材料上方形成金屬化圖案。所述金屬化圖案底將第一晶粒連接件電性連接至第二晶粒連接件。在一實施例中，所述方法更包含將聚合物層沈積於聚合物材料上方，且形成所述金屬化圖案包含在聚合物層上方形成金屬化圖案。在一實施例中，形成金屬化圖案包括形成與聚合物材料相接觸的金屬化圖案。在一實施例中，所述方法更包含第一晶粒連接件以及第二晶粒連接件低於圖案化模製化合物之頂部表面。在一實施例中，在對所述聚合物材料平坦化之後，聚合物材料、模製化合物、第一晶粒連接件以及第二晶粒連接件之頂部表面為共平面的。
根據一實施例，一種封裝包含：積體電路晶粒，包括晶粒 連接件；包封體，配置在所述積體電路晶粒周圍；聚合物材料，在所述包封體之至少一部分上方；雜質，配置在所述聚合物材料之頂部表面處，所述雜質之材料不同於所述聚合物材料；以及導電線，在所述聚合物材料上方。所述導電線將晶粒連接件電性連接至導電構件，且所述包封體之一部分配置在晶粒連接件與導電構件之間。在一實施例中，聚合物層配置在導電線與聚合物材料之間，且所述雜質配置在聚合物材料與聚合物層之間的界面處。在一實施例中，聚合物層進一步與包封體形成界面。在一實施例中，聚合物層覆蓋包封體之整個頂部表面。在一實施例中，所述雜質配置在導電線與聚合物材料之間的界面處。在一實施例中，晶粒連接件之頂部表面配置在包封體之頂部表面下方，且聚合物材料自包封體之頂部表面延伸至晶粒連接件之頂部表面。在一實施例中，雜質包含矽、鋁，或其一組合。
前文概述若干實施例之特徵，使得所屬領域中具通常知識者可更好地理解本發明之態樣。所屬領域中具通常知識者應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優點的其他處理程序及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本發明之精神以及範疇，且其可在不脫離本發明之精神以及範疇的情況下在本文中進行各種改變、替代以及更改。
114A、114B‧‧‧積體電路晶粒
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
130A‧‧‧填充物
130C‧‧‧區域
131‧‧‧聚合物材料
133‧‧‧殘留物
604‧‧‧區域

Claims (17)

  1. 一種形成半導體封裝的方法，包括：將半導體晶粒包封在包封體中；對所述包封體平坦化；將聚合物材料沈積在所述包封體上；對所述聚合物材料平坦化；以及將金屬化圖案形成於所述聚合物材料上，其中所述金屬化圖案將所述半導體晶粒之晶粒連接件電性連接至配置在所述半導體晶粒之外部的導電構件，其中對所述包封體進行所述平坦化時在所述包封體的頂部表面定義出多個凹口，且其中所述聚合物材料填入於所述多個凹口中。
  2. 如申請專利範圍第1項所述形成半導體封裝的方法，其中所述包封體包括填充物，其中對所述包封體平坦化暴露所述填充物之中空核心，且其中沈積所述聚合物材料包括用所述聚合物材料填充所述中空核心。
  3. 如申請專利範圍第1項所述形成半導體封裝的方法，更包括在所述聚合物材料與所述金屬化圖案之間形成聚合物層。
  4. 如申請專利範圍第1項所述形成半導體封裝的方法，其中形成所述金屬化圖案包括形成與所述聚合物材料物理接觸的所述金屬化圖案。
  5. 如申請專利範圍第4項所述形成半導體封裝的方法，更包括：圖案化第一開口穿透所述聚合物材料以暴露所述半導體晶粒 之所述晶粒連接件；以及圖案化第二開口穿透所述聚合物材料以暴露所述導電構件，其中形成所述金屬化圖案包括形成所述金屬化圖案之部分在所述第一開口及所述第二開口中。
  6. 如申請專利範圍第5項所述形成半導體封裝的方法，其中在對所述聚合物材料平坦化之前執行圖案化所述第一開口以及圖案化所述第二開口。
  7. 如申請專利範圍第1項所述形成半導體封裝的方法，更包括：在沈積所述聚合物材料之前，使所述半導體晶粒之所述晶粒連接件凹陷低於所述包封體之頂部表面。
  8. 如申請專利範圍第1項所述形成半導體封裝的方法，其中對所述聚合物材料平坦化暴露所述包封體之部分。
  9. 一種形成半導體封裝的方法，包括：配置與第二積體電路晶粒相鄰的第一積體電路晶粒；將所述第一積體電路晶粒及所述第二積體電路晶粒包封在模製化合物中，所述模製化合物包括多個填充物；對所述模製化合物平坦化以暴露所述第一積體電路晶粒之第一晶粒連接件以及所述第二積體電路晶粒之第二晶粒連接件，對所述模製化合物平坦化在所述模製化合物之頂部表面處定義出多個凹口；將聚合物材料沈積於所述模製化合物上方，所述聚合物材料配置在所述模製化合物之所述頂部表面處的所述多個凹口中；對所述聚合物材料平坦化；以及在所述聚合物材料上方形成金屬化圖案，所述金屬化圖案將 所述第一晶粒連接件電性連接至所述第二晶粒連接件。
  10. 如申請專利範圍第9項所述形成半導體封裝的方法，更包括將聚合物層沈積於所述聚合物材料上方，其中形成所述金屬化圖案包括在所述聚合物層上方形成所述金屬化圖案。
  11. 如申請專利範圍第9項所述形成半導體封裝的方法，其中在對所述聚合物材料平坦化之後，所述聚合物材料、所述模製化合物、所述第一晶粒連接件以及所述第二晶粒連接件之頂部表面為共平面的。
  12. 一種半導體封裝，包括：積體電路晶粒，包括晶粒連接件；包封體，配置在所述積體電路晶粒周圍，其中所述包封體的頂部表面定義有多個凹口；聚合物材料，在所述包封體之至少一部分上方，且填入於所述多個凹口中；雜質，配置在所述聚合物材料之頂部表面處，所述雜質之材料不同於所述聚合物材料；以及導電線，在所述聚合物材料上方，所述導電線將所述晶粒連接件電性連接至導電構件，且所述包封體之一部分配置在所述晶粒連接件與所述導電構件之間。
  13. 如申請專利範圍第12項所述的半導體封裝，更包括配置在所述導電線與所述聚合物材料之間的聚合物層，所述雜質配置在所述聚合物材料與所述聚合物層之間的界面處。
  14. 如申請專利範圍第13項所述的半導體封裝，其中所述聚合物層進一步與所述包封體形成界面。
  15. 如申請專利範圍第13項所述的半導體封裝，其中所述聚合物層覆蓋所述包封體之整個頂部表面。
  16. 如申請專利範圍第12項所述的半導體封裝，其中所述雜質配置在所述導電線與所述聚合物材料之間的界面處。
  17. 如申請專利範圍第12項所述的半導體封裝，其中所述晶粒連接件之頂部表面配置在所述包封體之頂部表面下方，所述聚合物材料自所述包封體之所述頂部表面延伸至所述晶粒連接件之所述頂部表面。
TW107123828A 2017-11-15 2018-07-10 半導體封裝及其形成方法 TWI683410B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762586558P 2017-11-15 2017-11-15
US62/586,558 2017-11-15
US15/908,520 US10522436B2 (en) 2017-11-15 2018-02-28 Planarization of semiconductor packages and structures resulting therefrom
US15/908,520 2018-02-28

Publications (2)

Publication Number Publication Date
TW201924014A TW201924014A (zh) 2019-06-16
TWI683410B true TWI683410B (zh) 2020-01-21

Family

ID=66431412

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107123828A TWI683410B (zh) 2017-11-15 2018-07-10 半導體封裝及其形成方法

Country Status (4)

Country Link
US (2) US10522436B2 (zh)
KR (1) KR102108236B1 (zh)
CN (1) CN109786268B (zh)
TW (1) TWI683410B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510704B2 (en) * 2018-01-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10658257B1 (en) * 2018-11-01 2020-05-19 Advanced Semiconductor Engineering, Inc. Semiconductor package structure, semiconductor wafer level package and semiconductor manufacturing process
JP2020142480A (ja) * 2019-03-08 2020-09-10 Tdk株式会社 積層体とセンサパッケージ及びそれらの製造方法
KR102574414B1 (ko) * 2019-05-21 2023-09-04 삼성전기주식회사 전자 부품 모듈
US11251099B2 (en) 2019-07-31 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of packages using embedded core frame
US11264314B2 (en) * 2019-09-27 2022-03-01 International Business Machines Corporation Interconnection with side connection to substrate
US11004819B2 (en) 2019-09-27 2021-05-11 International Business Machines Corporation Prevention of bridging between solder joints
US11145614B2 (en) * 2019-10-18 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11282772B2 (en) * 2019-11-06 2022-03-22 Advanced Semiconductor Engineering, Inc. Package structure, assembly structure and method for manufacturing the same
TWI777467B (zh) * 2020-03-30 2022-09-11 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
DE102021100338A1 (de) * 2020-05-20 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterbauelement und herstellungsverfahren
US11817426B2 (en) * 2021-01-13 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of fabricating the same
KR102502104B1 (ko) * 2021-02-25 2023-02-23 주식회사 아이에스시 전기 접속용 커넥터
KR20220128773A (ko) 2021-03-15 2022-09-22 삼성전자주식회사 몰드층을 포함하는 반도체 패키지 및 이의 제조 방법
US11735529B2 (en) 2021-05-21 2023-08-22 International Business Machines Corporation Side pad anchored by next adjacent via
TWI800190B (zh) * 2021-12-30 2023-04-21 欣興電子股份有限公司 玻璃載板保護結構及其製法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160247779A1 (en) * 2014-04-30 2016-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US20160284667A1 (en) * 2014-08-20 2016-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6596624B1 (en) 1999-07-31 2003-07-22 International Business Machines Corporation Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier
US20070090545A1 (en) 2005-10-24 2007-04-26 Condie Brian W Semiconductor device with improved encapsulation
US7458885B1 (en) 2007-08-15 2008-12-02 Rohm And Haas Electronic Materials Cmp Holdings, Inc. Chemical mechanical polishing pad and methods of making and using same
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US10096540B2 (en) * 2011-05-13 2018-10-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8815713B2 (en) 2012-11-07 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing pattern loading effect in epitaxy
US9263377B2 (en) * 2012-11-08 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures with dams encircling air gaps and methods for forming the same
US8778738B1 (en) * 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9847269B2 (en) 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US10062648B2 (en) * 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160247779A1 (en) * 2014-04-30 2016-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US20160284667A1 (en) * 2014-08-20 2016-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same

Also Published As

Publication number Publication date
KR102108236B1 (ko) 2020-05-11
CN109786268A (zh) 2019-05-21
US10522436B2 (en) 2019-12-31
CN109786268B (zh) 2020-09-08
TW201924014A (zh) 2019-06-16
KR20190055692A (ko) 2019-05-23
US20200006171A1 (en) 2020-01-02
US20190148250A1 (en) 2019-05-16
US11127644B2 (en) 2021-09-21

Similar Documents

Publication Publication Date Title
TWI683410B (zh) 半導體封裝及其形成方法
US11189603B2 (en) Semiconductor packages and methods of forming same
US11682655B2 (en) Semiconductor packages and methods of forming the same
US11101209B2 (en) Redistribution structures in semiconductor packages and methods of forming same
CN109786267B (zh) 半导体封装件和方法
TWI683378B (zh) 半導體封裝及其製造方法
TWI644402B (zh) 半導體封裝及其形成方法
US10529650B2 (en) Semiconductor package and method
TW201824486A (zh) 封裝結構
TWI697085B (zh) 半導體元件及其形成方法
TWI749088B (zh) 半導體裝置的製造方法
TWI724653B (zh) 半導體裝置及其形成方法
US20210225723A1 (en) Integrated Circuit Package and Method
TWI803310B (zh) 積體電路元件和其形成方法
TWI778691B (zh) 積體電路封裝及其製造方法
TWI777437B (zh) 半導體封裝體及其製造方法
TWI719670B (zh) 積體電路封裝體及其製造方法
US20230075602A1 (en) Semiconductor Packages
US11854994B2 (en) Redistribution structure for integrated circuit package and method of forming same
US20230335536A1 (en) Semiconductor Packages and Methods of Forming the Same