JP4339309B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4339309B2 JP4339309B2 JP2005367927A JP2005367927A JP4339309B2 JP 4339309 B2 JP4339309 B2 JP 4339309B2 JP 2005367927 A JP2005367927 A JP 2005367927A JP 2005367927 A JP2005367927 A JP 2005367927A JP 4339309 B2 JP4339309 B2 JP 4339309B2
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
積層される半導体装置であって、
第1及び第2の半導体素子と、
積層方向に対する上側に位置し前記第1の半導体素子が搭載される第1の面と、前記積層方向に対する下側に位置し該第2の半導体素子が搭載される第2の面とを有する再配線基板と、
前記再配線基板の前記第1の面上で、前記第1の半導体素子の周囲に配置された第1の電極パッドと、
前記再配線基板の前記第2の面上で、前記第2の半導体素子の周囲に配置された第2の電極パッドと、
前記第1の半導体素子と前記第1の電極パッドを電気的に接続する第1のワイヤと、
前記第2の半導体素子と前記第2の電極パッドを電気的に接続する第2のワイヤと、
前記第1の面上で前記第1の半導体素子及び前記第1のワイヤを封止する第1の封止樹脂と、
前記第2の面上で前記第2の半導体素子及び前記第2のワイヤを封止する第2の封止樹脂と、
積層された状態において、前記積層方向に対する最下段に位置する前記再配線基板の前記第2の電極パッドに設けられた第1の突起電極と、
積層された状態において、前記積層方向に対する上側に配設された前記再配線基板の前記第2の電極パッドと、前記積層方向に対する下側に配設された前記再配線基板の前記第1の電極パッドとの間に設けられた第2の突起電極とを有し、
前記第1の突起電極の高さを、前記最下段に位置する前記第2の封止樹脂の封止高さより高くし、
積層された状態において、前記積層方向に対する上側に配設された前記再配線基板の前記第2の封止樹脂の封止高さと、前記積層方向に対する下側に配設された前記再配線基板の前記第2の封止樹脂の封止高さとの総和よりも高くし、
前記第1及び第2の封止樹脂は、前記第1及び第2のワイヤを封止する部分以外の高さを、前記第1及び第2のワイヤを封止する部分の高さよりも低くし、
かつ、積層された状態において、前記積層方向に対する上側に配設された前記再配線基板の前記第2の半導体素子と、前記積層方向に対する下側に配設された前記再配線基板の前記第1の半導体素子との位置を相対的にずらし、前記第2の封止樹脂の前記第2のワイヤを封止した部分と、前記第1の封止樹脂の前記第1のワイヤを封止した部分が重ならないよう構成する。
次に、本発明の第1実施例について説明する。図19は本発明の第1実施例による半導体装置の断面図である。図19において、図3に示した構成部品と同じ部品には同じ符号を付し、その説明は省略する。
2 封止樹脂
3,3A,3−1,3−2 半導体チップ
4 Auワイヤ
5 ボンディングパッド
6 DB材
7,7A,7B,7C ハンダボール
8,8B ボールパッド
9 スルーホール
10 ソルダーレジスト
10A,10B レジスト
11 アンダーフィル材
12 突起電極
21a 開口
22 VIAホール
24 UVテープ
13,39 緩衝材
30 治具
31 緩衝部材
32 押圧部材
33A,33B モールド金型
34 ランナー
35A,35B ゲート
36 撓み防止ピン
37 UVテープ
38 基板
40 半導体装置
41 パッケージ供給テーブル
42 スタックヘッド
43A,43B フラック供給部
44A〜44E 転写ヘッド
45 カメラユニット
46A,46B キャリアステージ
50 フラックス
54A〜54C フラック塗布部
55 位置決め治具
57 クリップ部材
58 フラックス装填溝
Claims (1)
- 積層される半導体装置であって、
第1及び第2の半導体素子と、
積層方向に対する上側に位置し前記第1の半導体素子が搭載される第1の面と、前記積層方向に対する下側に位置し該第2の半導体素子が搭載される第2の面とを有する再配線基板と、
前記再配線基板の前記第1の面上で、前記第1の半導体素子の周囲に配置された第1の電極パッドと、
前記再配線基板の前記第2の面上で、前記第2の半導体素子の周囲に配置された第2の電極パッドと、
前記第1の半導体素子と前記第1の電極パッドを電気的に接続する第1のワイヤと、
前記第2の半導体素子と前記第2の電極パッドを電気的に接続する第2のワイヤと、
前記第1の面上で前記第1の半導体素子及び前記第1のワイヤを封止する第1の封止樹脂と、
前記第2の面上で前記第2の半導体素子及び前記第2のワイヤを封止する第2の封止樹脂と、
積層された状態において、前記積層方向に対する最下段に位置する前記再配線基板の前記第2の電極パッドに設けられた第1の突起電極と、
積層された状態において、前記積層方向に対する上側に配設された前記再配線基板の前記第2の電極パッドと、前記積層方向に対する下側に配設された前記再配線基板の前記第1の電極パッドとの間に設けられた第2の突起電極とを有し、
前記第1の突起電極の高さを、前記最下段に位置する前記第2の封止樹脂の封止高さより高くし、
積層された状態において、前記積層方向に対する上側に配設された前記再配線基板の前記第2の封止樹脂の封止高さと、前記積層方向に対する下側に配設された前記再配線基板の前記第2の封止樹脂の封止高さとの総和よりも高くし、
前記第1及び第2の封止樹脂は、前記第1及び第2のワイヤを封止する部分以外の高さを、前記第1及び第2のワイヤを封止する部分の高さよりも低くし、
かつ、積層された状態において、前記積層方向に対する上側に配設された前記再配線基板の前記第2の半導体素子と、前記積層方向に対する下側に配設された前記再配線基板の前記第1の半導体素子との位置を相対的にずらし、前記第2の封止樹脂の前記第2のワイヤを封止した部分と、前記第1の封止樹脂の前記第1のワイヤを封止した部分が重ならないよう構成してなる半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2005367927A JP4339309B2 (ja) | 1999-11-30 | 2005-12-21 | 半導体装置 |
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JP34081699 | 1999-11-30 | ||
JP2005367927A JP4339309B2 (ja) | 1999-11-30 | 2005-12-21 | 半導体装置 |
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JP2000068986A Division JP3798597B2 (ja) | 1999-11-30 | 2000-03-13 | 半導体装置 |
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JP2008242003A Division JP5024249B2 (ja) | 1999-11-30 | 2008-09-22 | 半導体装置の製造方法 |
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JP4339309B2 true JP4339309B2 (ja) | 2009-10-07 |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102169875A (zh) * | 2010-02-26 | 2011-08-31 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
US8519537B2 (en) | 2010-02-26 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US9564416B2 (en) | 2015-02-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US9653443B2 (en) | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9768090B2 (en) | 2014-02-14 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9935090B2 (en) | 2014-02-14 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10026671B2 (en) | 2014-02-14 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4751351B2 (ja) * | 2007-02-20 | 2011-08-17 | 株式会社東芝 | 半導体装置とそれを用いた半導体モジュール |
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- 2005-12-21 JP JP2005367927A patent/JP4339309B2/ja not_active Expired - Fee Related
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9780072B2 (en) | 2010-02-26 | 2017-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US10446520B2 (en) | 2010-02-26 | 2019-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
CN102169875A (zh) * | 2010-02-26 | 2011-08-31 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
US8865521B2 (en) | 2010-02-26 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
CN102169875B (zh) * | 2010-02-26 | 2013-04-17 | 台湾积体电路制造股份有限公司 | 半导体装置及其制造方法 |
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US8519537B2 (en) | 2010-02-26 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
US9935090B2 (en) | 2014-02-14 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9653443B2 (en) | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9768090B2 (en) | 2014-02-14 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10026671B2 (en) | 2014-02-14 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10714359B2 (en) | 2014-02-14 | 2020-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US10867949B2 (en) | 2014-02-14 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US11158614B2 (en) | 2014-02-14 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US9564416B2 (en) | 2015-02-13 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US9859267B2 (en) | 2015-02-13 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
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