WO2013114481A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2013114481A1
WO2013114481A1 PCT/JP2012/006052 JP2012006052W WO2013114481A1 WO 2013114481 A1 WO2013114481 A1 WO 2013114481A1 JP 2012006052 W JP2012006052 W JP 2012006052W WO 2013114481 A1 WO2013114481 A1 WO 2013114481A1
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WIPO (PCT)
Prior art keywords
wiring
semiconductor chip
semiconductor device
chip
semiconductor
Prior art date
Application number
PCT/JP2012/006052
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English (en)
French (fr)
Inventor
紀行 永井
茂史 土肥
Original Assignee
パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to CN201280031587.1A priority Critical patent/CN103620776B/zh
Priority to JP2013556043A priority patent/JP5973470B2/ja
Publication of WO2013114481A1 publication Critical patent/WO2013114481A1/ja
Priority to US14/140,653 priority patent/US9240391B2/en

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a CoC (Chip-on-Chip) type semiconductor device.
  • Patent Document 1 describes a CoC type semiconductor device.
  • the conventional semiconductor device described in Patent Document 1 includes a mother substrate, a first chip disposed on the mother substrate, and a second chip disposed on the first chip. .
  • the first chip and the second chip are connected via solder bumps.
  • the size of the second chip (upper chip) is larger than the size of the first chip (lower chip), and the peripheral edge of the second chip protrudes laterally from the side surface of the first chip. ing.
  • the protruding peripheral portion of the second chip is connected to the mother substrate via a solder electrode.
  • the function of the first chip is via solder bumps that connect the first chip and the second chip, wiring in the second chip, and solder electrodes that connect the second chip and the mother substrate. It is pulled out to the mother board.
  • the function of the second chip is drawn out to the mother substrate via a solder electrode that connects the second chip and the mother substrate.
  • the conventional semiconductor device has the following problems.
  • both the function of the first chip and the function of the second chip are drawn out to the mother substrate via the solder electrodes.
  • an object of the present invention is to improve the performance of a semiconductor device by increasing the wiring resources for extracting the function of the semiconductor chip in a CoC type semiconductor device.
  • a semiconductor device includes a first semiconductor chip and a second semiconductor chip that has a top surface opposite to the top surface of the first semiconductor chip and is smaller than the size of the first semiconductor chip.
  • the semiconductor chip, the extension formed outward from the side surface of the second semiconductor chip, the upper surface of the second semiconductor chip is disposed to face the upper surface of the first semiconductor chip, and the upper surface of the second semiconductor chip is And a wiring board disposed opposite to the lower surface, further comprising a first wiring formed on the lower surface of the second semiconductor chip and the lower surface of the extension portion and connected to the wiring substrate.
  • the wiring resource for extracting the function of the semiconductor chip is increased, so that the performance of the semiconductor device can be improved.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Modification 1 of the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Modification 2 of the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Modification 3 of the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Modification 1 of the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the third embodiment of the present invention.
  • FIG. 7 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Modification 1 of the third embodiment of the present invention.
  • FIG. 8 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Modification 2 of the third embodiment of the present invention.
  • FIG. 9 is a cross-sectional view schematically showing an example of a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 10 is a cross-sectional view schematically showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 10 is a cross-sectional view schematically showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view schematically showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 12 is a cross-sectional view schematically showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a part of the semiconductor device 100 according to the present embodiment.
  • the semiconductor device 100 includes a semiconductor chip 1 that is a first semiconductor chip, a semiconductor chip 2 that is a second semiconductor chip, an expansion unit 9, and a wiring substrate 3.
  • the semiconductor chip 2 is mounted on the wiring board 3.
  • the semiconductor chip 1 is stacked on the semiconductor chip 2 and mounted on the wiring board 3.
  • the semiconductor chip 1 and the semiconductor chip 2 are connected via bumps 4.
  • the semiconductor chip 1 and the wiring substrate 3 are connected via bumps 5.
  • the semiconductor chip 1 is formed on a silicon substrate and has a circuit 6 having an electrical characteristic function, and a redistribution layer (RDL, Re-Distribution layer) formed on the circuit 6 and connected to the circuit 6. 7).
  • the semiconductor chip 1 is formed on a peripheral portion on the upper surface, and is formed on a plurality of input / output pads 13 that are electrically connected to the wiring board 3, respectively, on a central portion on the upper surface, and each It further has a plurality of input / output pads (not shown) electrically connected to the semiconductor chip 2.
  • the “upper surface of the semiconductor chip 1” is a surface on the side where the RDL 7 is formed.
  • the function of the semiconductor chip 1 can be brought out to the wiring board 3 through the RDL 7, the input / output pad 13, and the bump 5.
  • the semiconductor chip 2 has a circuit 8 formed on a silicon substrate and having an electrical characteristic function.
  • the semiconductor chip 2 further includes a plurality of input / output pads (not shown) that are formed on the upper surface and are each electrically connected to the semiconductor chip 1.
  • the “upper surface of the semiconductor chip 2” is the surface on which the circuit 8 is formed.
  • the size of the semiconductor chip 2 is smaller than the size of the semiconductor chip 1.
  • the upper surface of the semiconductor chip 2 faces the upper surface of the semiconductor chip 1.
  • the extension portion 9 is in contact with the side surface of the semiconductor chip 2 and is formed outward from the side surface of the semiconductor chip 2.
  • the extended portion 9 is insulative and is made of, for example, resin.
  • the semiconductor chip 2 and the expansion unit 9 constitute an expansion semiconductor chip.
  • the size of the expandable semiconductor chip is smaller than the size of the semiconductor chip 1, and the peripheral edge of the semiconductor chip 1 protrudes laterally from the side surface of the expandable semiconductor chip.
  • the semiconductor device 100 further includes a wiring 10 that is a first wiring.
  • the wiring 10 is formed on the lower surface of the expansion type semiconductor chip (in other words, the lower surface of the semiconductor chip 2 and the lower surface of the expansion portion 9) from the periphery of the semiconductor chip 2 to the expansion portion 9.
  • the wiring 10 is connected to the wiring board 3.
  • the “lower surface of the expandable semiconductor chip” is a surface facing the wiring board 3.
  • the function of the semiconductor chip 2 can be extracted to the wiring board 3 via the bumps 4, the RDL 7, the input / output pads 13, and the bumps 5.
  • the wiring board 3 includes a plurality of lands 11 and 12 formed on the upper surface, a plurality of external terminals 15 and 17 formed on the lower surface, and a plurality of wiring paths 14 and 16 formed inside. Have.
  • the upper surface of the wiring board 3 faces the upper surface of the semiconductor chip 1 and faces the lower surface of the semiconductor chip 2.
  • the “upper surface of the wiring board 3” is a surface on which the lands 11 and 12 are formed.
  • the wiring path 14 connects the land 11 and the external terminal 15.
  • the wiring path 16 connects the land 12 and the external terminal 17.
  • the land 11 is connected to the input / output pad 13 of the semiconductor chip 1 through the bumps 5 and to a part of the wiring 10.
  • the land 12 is connected to a part of the wiring 10, specifically, a part different from the part connected to the land 11 in the wiring 10.
  • the lands 11 and 12 and the wiring 10 can be connected by, for example, applying a conductive paste (not shown) to the lands 11 and 12 or the wiring 10.
  • the connection between the lands 11 and 12 and the wiring 10 can be performed by applying vibration while the lands 11 and 12 and the wiring 10 are in contact with each other.
  • the functions of the semiconductor chips 1 and 2 are led out from the land 11 to the external terminal 15 through the wiring path 14 in the wiring board 3 and further from the land 12 through the wiring path 16 in the wiring board 3 to the outside. It can be pulled out to the terminal 17.
  • the semiconductor chip 1 RDL7 can be used in the semiconductor device in which the upper surfaces of the semiconductor chips 1 and 2 are arranged to face each other and the semiconductor chip 1 protrudes to the side of the semiconductor chip 2, the semiconductor chip 1 RDL7 can be used. Furthermore, the RDL 7 of the semiconductor chip 1 can also be used for extracting the functions of the semiconductor chip 2.
  • the RDL 7 is preferably formed in the state of a wafer before the semiconductor chip 1 is singulated. As a result, the RDL 7 can be formed more efficiently than when the RDL is formed after the semiconductor chip 1 is separated.
  • the wiring 10 can be used for the function extraction of the semiconductor chips 1 and 2.
  • the wiring resources are increased and the degree of freedom of the lead wiring can be improved.
  • the performance of the semiconductor device can be improved while satisfying the demands for reducing the size and thickness of the semiconductor device.
  • FIG. 2 is a cross-sectional view schematically showing the configuration of the semiconductor device 110 according to this modification.
  • reference numerals 1, 4 to 9, and 13 to 17 are omitted.
  • the semiconductor device 110 further includes bumps 18.
  • the bump 18 is interposed between the lands 11 and 12 of the wiring substrate 3 and the wiring 10.
  • the wiring board 3 and the wiring 10 are connected via the bumps 18.
  • the thickness of the semiconductor chip 2 can be reduced. Furthermore, the distance between the semiconductor chip 2 and the wiring substrate 3 is increased, and the semiconductor chip 2 is likely to dissipate heat. Further, the connection between the wiring 10 and the lands 11 and 12 can be stably maintained by the bumps 18.
  • FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor device 120 according to this modification.
  • reference numerals 1, 4 to 9, and 13 to 17 are omitted.
  • the semiconductor device 120 includes a wiring board 33 instead of the wiring board 3 of the first embodiment, and further includes bumps 38.
  • the wiring board 33 has lands 32 instead of the lands 12 of the first embodiment.
  • a step 19 is formed on the upper surface of the wiring board 33 so that the region where the land 32 is arranged (in other words, the region located under the semiconductor chip 2) is lower than the region where the land 11 is arranged. Yes.
  • a recess is formed in a region located below the semiconductor chip 2 on the upper surface of the wiring substrate 33.
  • a land 32 is formed on the bottom surface of the recess.
  • the bump 38 is interposed between the land 32 of the wiring board 33 and the wiring 10.
  • FIG. 4 is a cross-sectional view schematically showing the configuration of the semiconductor device 130 according to this modification.
  • the reference numerals 4, 6 to 10, 12, and 14 to 17 are omitted.
  • the semiconductor device 130 includes pillars 20 instead of the bumps 5 of the first embodiment.
  • the pillar 20 is interposed between the land 11 of the wiring board 3 and the input / output pad 13 of the semiconductor chip 1.
  • the wiring board 3 and the semiconductor chip 1 are connected via the pillar 20.
  • the width of the bonding member can be easily adjusted according to the area of the bonding portion of the land 11 and the area of the bonding portion of the input / output pad 13. It becomes easy to adjust the height of the joining member in accordance with the thickness of the semiconductor chip 2. Specifically, for example, when the thickness of the semiconductor chip 2 is reduced, it is easy to reduce only the height of the pillar 20 while maintaining the area of the junction of the land 11 and the area of the junction of the input / output pad 13. Therefore, the semiconductor device can be easily reduced in thickness.
  • the “joining portion of the land 11” is a portion that joins the joining member in the land 11.
  • the “joining portion of the input / output pad 13” is a portion that joins the joining member in the input / output pad 13.
  • the area of the junction of the land 11 and the area of the junction of the input / output pad 13 can be made smaller than when bumps are used, and the semiconductor device can be downsized.
  • FIG. 5 is a cross-sectional view schematically showing a partial configuration of the semiconductor device 200 according to the present embodiment.
  • the description of the configuration that is common to the semiconductor device 100 according to the first embodiment is omitted, and the differences will be described.
  • the semiconductor device 200 further includes a via 21 that is a first via and a wiring 22 that is a second wiring, and includes a wiring 50 instead of the wiring 10 of the first embodiment.
  • the via 21 is formed in the extended portion 9 and penetrates the extended portion 9 in a direction perpendicular to the upper surface of the wiring board 3.
  • the wiring 22 is formed on the upper surface of the expandable semiconductor chip (in other words, the upper surface of the semiconductor chip 2 and the upper surface of the extension portion 9) from the periphery of the semiconductor chip 2 to the extension portion 9.
  • the wiring 50 is formed on the lower surface of the extended semiconductor chip (in other words, the lower surface of the semiconductor chip 2 and the lower surface of the extended portion 9) from the peripheral portion of the semiconductor chip 2 to the extended portion 9.
  • the via 21 connects the wiring 50 and the wiring 22.
  • the wiring 22 is connected to input / output pads (not shown) of the semiconductor chip 2. Thereby, the wiring 22 can be used as a wiring for extracting the function of the semiconductor chip 2. Further, the wiring 22 is connected to the RDL 7 of the semiconductor chip 1 through the bumps 4. Thereby, the wiring 22 can be used as a wiring for extracting the function of the semiconductor chip 1.
  • the wiring 50 is connected to the land 12 of the wiring board 3.
  • the semiconductor device 200 further includes the via 21 and the wiring 22, and includes the wiring 50 instead of the wiring 10 of the first embodiment.
  • the number of paths through which the functions of the semiconductor chips 1 and 2 are extracted to the wiring board 3 is increased, so that the wiring resources are increased and the performance of the semiconductor device can be improved.
  • bumps may be interposed between the wiring 50 and the land 12 as in Modification 1 of the first embodiment. Thereby, the effect similar to the modification 1 of 1st Embodiment mentioned above can be exhibited.
  • a recess is formed in a region located below the semiconductor chip 2 on the upper surface of the wiring board, and the land and wiring formed on the bottom surface of the recess are formed. Bumps may be interposed between the two. Thereby, the effect similar to the modification 2 of 1st Embodiment mentioned above can be exhibited.
  • pillars may be used instead of bumps, as in Modification 3 of the first embodiment. Thereby, the effect similar to the modification 3 of 1st Embodiment mentioned above can be exhibited.
  • FIG. 6 is a cross-sectional view schematically showing a partial configuration of the semiconductor device 300 according to the present embodiment.
  • the description of the configuration common to the semiconductor device 200 according to the second embodiment is omitted, and differences will be described.
  • the semiconductor device 300 further includes a via 23 that is a second via and a wiring 24 that is a third wiring, and instead of the extension 9 in the second embodiment, an extension 69 and a second embodiment.
  • a wiring 60 is provided instead of the wiring 50, and a bump 4 is further provided between the wiring 24 and the input / output pad 13.
  • the extended portion 69 and the semiconductor chip 2 constitute an extended semiconductor chip.
  • the via 23 is formed in the extended portion 69 and penetrates the extended portion 69 in a direction perpendicular to the upper surface of the wiring board 3.
  • the via 23 is located outside the via 21.
  • the wiring 24 is formed on the upper surface of the extended portion 69.
  • the wiring 24 is preferably formed simultaneously with the wiring 22.
  • the extension part 69 protrudes to the side from the extension part 9 of the second embodiment.
  • the wiring 60 is formed on the lower surface of the extended semiconductor chip (in other words, the lower surface of the semiconductor chip 2 and the lower surface of the extended portion 69) from the periphery of the semiconductor chip 2 to the extended portion 69.
  • the via 21 connects the wiring 60 and the wiring 22.
  • the via 23 connects the wiring 60 and the wiring 24.
  • the wiring 60 is connected to the lands 11 and 12 of the wiring board 3.
  • the wiring 24 and the input / output pad 13 of the semiconductor chip 1 are connected via bumps 4.
  • the input / output pads 13 of the semiconductor chip 1 and the lands 11 of the wiring board 3 are connected via the bumps 5.
  • the input / output pad 13 of the semiconductor chip 1 and the land 11 of the wiring substrate 3 are connected via the bump 4, the wiring 24, the via 23, and the wiring 60. Therefore, the semiconductor device 300 according to the present embodiment does not have the bumps 5 of the second embodiment.
  • the vias 23 can be used instead of the bumps for extracting the functions of the semiconductor chips 1 and 2. This eliminates the need to form bumps and simplifies the process. Furthermore, the semiconductor device can be downsized by making the width of the via 23 smaller than the width of the bump.
  • FIG. 7 is a cross-sectional view schematically showing the configuration of the semiconductor device 310 according to this modification.
  • reference numerals 1, 3, 4, 6 to 8, and 13 to 17 are omitted.
  • the semiconductor device 310 further includes a wiring 25 that is a fourth wiring, and includes a wiring 70 instead of the wiring 60 of the third embodiment.
  • the wiring 25 is formed on the lower surface of the extended portion 69.
  • the wiring 70 is formed on the lower surface of the extended semiconductor chip (in other words, the lower surface of the semiconductor chip 2 and the lower surface of the extended portion 69) from the periphery of the semiconductor chip 2 to the extended portion 69.
  • the via 21 connects the wiring 70 and the wiring 22.
  • the via 23 connects the wiring 25 and the wiring 24.
  • the wiring 70 is connected to the land 12 of the wiring board 3.
  • the wiring 25 is connected to the land 11 of the wiring board 3.
  • each of the land 11 and the land 12 serves as a separate extraction path, so that the degree of freedom of the output path is improved and the characteristics of the semiconductor device are improved.
  • FIG. 8 is a cross-sectional view schematically showing the configuration of the semiconductor device 320 according to this modification.
  • reference numerals 1, 4, 6 to 8, 13 to 17, 21 to 24, and 69 are omitted.
  • the semiconductor device 320 further includes bumps 88.
  • the bump 88 is interposed between the lands 11 and 12 of the wiring board 3 and the wiring 60.
  • the wiring board 3 and the wiring 60 are connected via the bumps 88.
  • an input / output pad (not shown) formed on the upper surface is provided, and a wiring 10 is formed on the lower surface from the periphery of the semiconductor chip 2 to the extended portion 9.
  • the extended semiconductor chip 92 thus prepared is prepared.
  • a wiring board 3 is prepared in which lands 11 and 12 are formed on the upper surface, external terminals 15 and 17 are formed on the lower surface, and wiring paths 14 and 16 are formed inside.
  • the expandable semiconductor chip 92 is mounted on the wiring board 3 so that the wiring 10 is connected to the lands 11 and 12.
  • An adhesive member may be inserted between the expandable semiconductor chip 92 and the wiring board 3 to fix the expandable semiconductor chip 92 to the wiring board 3.
  • bumps 5 are formed on the lands 11 of the wiring board 3. At this time, the bump 5 is formed so that the uppermost point of the bump 5 is located above the upper surface of the semiconductor chip 2.
  • a method for forming the bump 5 for example, electrolytic plating, mounting or printing can be considered.
  • the resin sheet material 101 is applied on the upper surface of the expandable semiconductor chip 92.
  • the input / output pad 13 faces the bump 5 and the bump 4 faces the input / output pad (not shown) of the semiconductor chip 2 above the wiring substrate 3 on which the expandable semiconductor chip 92 is mounted.
  • the semiconductor chip 1 is disposed.
  • the semiconductor chip 1 is stacked on the extended semiconductor chip 92 and mounted on the wiring board 3.
  • the input / output pads 13 of the semiconductor chip 1 and the bumps 5 are joined.
  • the land 11 of the wiring board 3 and the input / output pad 13 of the semiconductor chip 1 are connected via the bump 5.
  • the bump 4 and the input / output pad (not shown) of the semiconductor chip 2 are joined.
  • the input / output pads (not shown) of the semiconductor chip 1 and the input / output pads (not shown) of the semiconductor chip 2 are connected via the bumps 4.
  • This CoC junction is formed by C4 (Controlled Collapse Chip Connection) method or scrubbing.
  • the semiconductor device 100 can be manufactured.
  • the RDL 7 and the wirings 10, 50, 60, 70, 22, 25 are finely configured by diffusion in the circuits 6, 8 of the semiconductor chips 1, 2. It may be formed wider and thicker than the wiring. In this case, for example, the thicknesses of the RDL 7 and the wirings 10, 50, 60, 70, 22, 25 are 3 ⁇ m to 20 ⁇ m. With this configuration, since the resistance of the RDL 7 and the wirings 10, 50, 60, 70, 22, 25 can be made smaller than the resistance of the fine wiring, the RDL 7 and / or the wirings 10, 50, 60, 70, 22, 25, 25 Can be used as power supply wiring, more stable power supply is possible.
  • the bump 4 is made of, for example, a metal such as solder, copper (Cu), or nickel (Ni).
  • the bumps 5 and pillars 20 are made of a metal such as Cu, for example.
  • the land 11 of the wiring board 3 is disposed directly below the input / output pad 13 of the semiconductor chip 1. From the viewpoint of improving the degree of freedom of wiring, it is desirable that the lands 12 of the wiring board 3 are all disposed directly below the semiconductor chip 2.
  • the expansion parts 9 and 69 are made of, for example, an epoxy resin.
  • the vias 21 and 23 are formed by, for example, forming a through hole in the extended portion by laser irradiation and then embedding solder or Cu in the through hole.
  • the present invention can improve the performance of a semiconductor device due to an increase in wiring resources, and can be widely applied to electronic devices using a CoC type semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

　半導体装置は、第１の半導体チップ１と、上面が第１の半導体チップ１の上面と向かい合って配置され、第１の半導体チップ１のサイズよりも小さい第２の半導体チップ２と、第２の半導体チップ２の側面から外方に向かって形成された拡張部９と、上面が第１の半導体チップ１の上面と向かい合って配置され、かつ、上面が第２の半導体チップ２の下面と向かい合って配置された配線基板３とを備えている。半導体装置は、第２の半導体チップ２の下面および拡張部９の下面の上に形成され、配線基板３と接続された第１の配線１０をさらに備えている。

Description

半導体装置
　本発明は、半導体装置に関し、特にＣｏＣ（Chip on Chip）型の半導体装置に関する。
　半導体装置において、小型化および薄型化に加えて、高性能化を合わせて実現する必要性が高まっている。その事例として、チップの機能面同士をバンプ等の接合部材を介して接合するＣｏＣ型の半導体装置が広く普及している。ＣｏＣ型の半導体装置の場合、上下チップ間の信号制御の高速化、および異種プロセスにて構成されたチップ同士の組合せが可能となり、半導体装置の汎用性が向上する。
　特許文献１には、ＣｏＣ型の半導体装置が記載されている。
　特許文献１に記載の従来の半導体装置は、マザー基板と、マザー基板の上に配置された第１のチップと、第１のチップの上に配置された第２のチップとを有している。
　第１のチップと第２のチップとは、はんだバンプを介して接続されている。第２のチップ（上側のチップ）のサイズは、第１のチップ（下側のチップ）のサイズよりも大きく、第２のチップの周縁部は、第１のチップの側面よりも側方に突出している。突出した第２のチップの周縁部は、はんだ電極を介してマザー基板に接続されている。
　第１のチップの機能は、第１のチップと第２のチップとを接続するはんだバンプ、第２のチップ内の配線、および第２のチップとマザー基板とを接続するはんだ電極を介して、マザー基板に引き出される。第２のチップの機能は、第２のチップとマザー基板とを接続するはんだ電極を介して、マザー基板に引き出される。
特開２００４－１４６７２８号公報
　しかしながら、従来の半導体装置では、以下の問題がある。
　従来の半導体装置では、第１のチップの機能および第２のチップの機能の両方が、はんだ電極を介して、マザー基板に引き出される。
　しかしながら、マザー基板の配線リソースは少なく、配線自由度が小さい。このため、引き出された第１のチップの機能および第２のチップの機能の両方に対応するだけの十分な配線を、マザー基板に形成できず、半導体装置の性能が低下するという問題がある。
　前記に鑑み、本発明の目的は、ＣｏＣ型の半導体装置において、半導体チップの機能を引き出す配線リソースの増加により、半導体装置の性能を向上することである。
　前記の目的を達成するため、本発明に係る半導体装置は、第１の半導体チップと、上面が第１の半導体チップの上面と向かい合って配置され、第１の半導体チップのサイズよりも小さい第２の半導体チップと、第２の半導体チップの側面から外方に向かって形成された拡張部と、上面が第１の半導体チップの上面と向かい合って配置され、かつ、上面が第２の半導体チップの下面と向かい合って配置された配線基板とを備え、第２の半導体チップの下面および拡張部の下面の上に形成され、配線基板と接続された第１の配線をさらに備えていることを特徴とする。
　本発明によれば、ＣｏＣ型の半導体装置において、半導体チップの機能を引き出す配線リソースが増加するため、半導体装置の性能を向上することができる。
図１は、本発明の第１の実施形態に係る半導体装置の構成を模式的に示す断面図である。 図２は、本発明の第１の実施形態の変形例１に係る半導体装置の構成を模式的に示す断面図である。 図３は、本発明の第１の実施形態の変形例２に係る半導体装置の構成を模式的に示す断面図である。 図４は、本発明の第１の実施形態の変形例３に係る半導体装置の構成を模式的に示す断面図である。 図５は、本発明の第２の実施形態に係る半導体装置の構成を模式的に示す断面図である。 図６は、本発明の第３の実施形態に係る半導体装置の構成を模式的に示す断面図である。 図７は、本発明の第３の実施形態の変形例１に係る半導体装置の構成を模式的に示す断面図である。 図８は、本発明の第３の実施形態の変形例２に係る半導体装置の構成を模式的に示す断面図である。 図９は、本発明の第１の実施形態に係る半導体装置の製造工程の一例を模式的に示す断面図である。 図１０は、本発明の第１の実施形態に係る半導体装置の製造工程の一例を模式的に示す断面図である。 図１１は、本発明の第１の実施形態に係る半導体装置の製造工程の一例を模式的に示す断面図である。 図１２は、本発明の第１の実施形態に係る半導体装置の製造工程の一例を模式的に示す断面図である。
　本発明に係る半導体装置について図面を用いて説明する。全ての図面において共通する構成要素には同じ符号を付し、適宜説明を省略する。
　（第１の実施形態）
　図１は、本実施形態に係る半導体装置１００の一部の構成を模式的に示す断面図である。
　半導体装置１００は、第１の半導体チップである半導体チップ１と、第２の半導体チップである半導体チップ２と、拡張部９と、配線基板３とを備えている。半導体チップ２は、配線基板３の上に搭載されている。半導体チップ１は、半導体チップ２の上に積層され、かつ、配線基板３の上に搭載されている。半導体チップ１と半導体チップ２とは、バンプ４を介して接続されている。半導体チップ１と配線基板３とは、バンプ５を介して接続されている。
　半導体チップ１は、シリコン基板の上に形成され、かつ、電気特性機能を有する回路６と、回路６の上に形成され、かつ、回路６と接続された再配線層（ＲＤＬ、Re-Distribustion Layer）７とを有する。半導体チップ１は、上面における周縁部の上に形成され、かつ、各々が配線基板３と電気的に接続する複数の入出力パッド１３と、上面における中央部の上に形成され、かつ、各々が半導体チップ２と電気的に接続する複数の入出力パッド（図示省略）とをさらに有する。本明細書において、「半導体チップ１の上面」とは、ＲＤＬ７が形成された側の面である。
　上記構成により、半導体チップ１の機能は、ＲＤＬ７と入出力パッド１３とバンプ５とを介して配線基板３に引き出すことができる。
　半導体チップ２は、シリコン基板の上に形成され、かつ、電気特性機能を有する回路８を有する。半導体チップ２は、上面の上に形成され、かつ、各々が半導体チップ１と電気的に接続する複数の入出力パッド（図示省略）をさらに有する。本明細書において、「半導体チップ２の上面」とは、回路８が形成された側の面である。
　半導体チップ２のサイズは、半導体チップ１のサイズよりも小さい。半導体チップ２の上面は、半導体チップ１の上面と向かい合っている。
　拡張部９は、半導体チップ２の側面に接触し、かつ、半導体チップ２の側面から外方に向かって形成されている。拡張部９は、絶縁性であり、例えば、樹脂からなる。半導体チップ２と拡張部９とから、拡張型半導体チップが構成されている。拡張型半導体チップのサイズは、半導体チップ１のサイズよりも小さく、半導体チップ１の周縁部は、拡張型半導体チップの側面よりも側方に突出している。
　半導体装置１００は、第１の配線である配線１０をさらに備えている。配線１０は、拡張型半導体チップの下面（言い換えれば、半導体チップ２の下面および拡張部９の下面）の上に、半導体チップ２の周縁部から拡張部９に亘って形成されている。配線１０は、配線基板３と接続されている。本明細書において、「拡張型半導体チップの下面」とは、配線基板３と向かい合う面である。
　上記構成により、半導体チップ２の機能は、バンプ４とＲＤＬ７と入出力パッド１３とバンプ５とを介して配線基板３に引き出すことができる。
　配線基板３は、上面の上に形成された複数のランド１１，１２と、下面の上に形成された複数の外部端子１５，１７と、内部に形成された複数の配線経路１４，１６とを有する。
　配線基板３の上面は、半導体チップ１の上面と向かい合っているとともに、半導体チップ２の下面と向かい合っている。本明細書において、「配線基板３の上面」とは、ランド１１，１２が形成された面である。
　配線経路１４は、ランド１１と外部端子１５とを接続している。配線経路１６は、ランド１２と外部端子１７とを接続している。
　ランド１１は、バンプ５を介して、半導体チップ１の入出力パッド１３と接続されているとともに、配線１０の一部と接続されている。ランド１２は、配線１０の一部、具体的には、配線１０におけるランド１１と接続する部分とは異なる部分と接続されている。ランド１１，１２と配線１０との接続は、例えば、導電性のペースト（図示省略）をランド１１，１２または配線１０に塗布することにより行うことが可能である。その他に例えば、ランド１１，１２と配線１０との接続は、ランド１１，１２と配線１０とを接触させた状態で振動を与えることにより行うことも可能である。
　上記構成により、半導体チップ１，２の機能を、ランド１１から配線基板３内の配線経路１４を介して外部端子１５へ引き出し、さらに、ランド１２から配線基板３内の配線経路１６を介して外部端子１７へ引き出すことができる。
　本実施形態によると、半導体チップ１，２の上面同士が互いに向かい合って配置され、半導体チップ２よりも半導体チップ１が側方に突出した半導体装置において、半導体チップ１の機能引き出しに、半導体チップ１のＲＤＬ７を使用することができる。さらに、半導体チップ２の機能引き出しにも、半導体チップ１のＲＤＬ７を使用することができる。ＲＤＬ７は、半導体チップ１が個片化される前のウエハの状態で形成されることが好ましい。これにより、半導体チップ１を個片化した後にＲＤＬを形成する場合と比べて、ＲＤＬ７を効率的に形成することができる。
　さらに、半導体チップ１，２の機能引き出しに、配線１０を使用することが可能になる。これにより、配線リソースが増加し、引き出し配線の自由度の向上を実現できる。このような配線リソースの増加および引き出し配線の自由度の向上により、半導体装置の小型化および薄型化の要求を満たしつつ、半導体装置の性能を向上することができる。
　（第１の実施形態の変形例１）
　図２は、本変形例に係る半導体装置１１０の構成を模式的に示す断面図である。なお、図２において、簡略的に図示する為に、符号１，４～９，１３～１７の図示を省略している。
　図２に示すように、半導体装置１１０は、バンプ１８をさらに有する。バンプ１８は、配線基板３のランド１１，１２と配線１０との間に介在している。バンプ１８を介して、配線基板３と配線１０とが接続されている。
　この構成により、半導体チップ２の厚みを薄くすることが可能である。さらに、半導体チップ２と配線基板３との距離が大きくなり、半導体チップ２が放熱しやすくなる。さらに、配線１０とランド１１，１２との接続をバンプ１８により安定的に保つことができる。
　（第１の実施形態の変形例２）
　図３は、本変形例に係る半導体装置１２０の構成を模式的に示す断面図である。なお、図３において、簡略的に図示する為に、符号１，４～９，１３～１７の図示を省略している。
　図３に示すように、半導体装置１２０は、第１の実施形態の配線基板３の代わりに、配線基板３３を備え、バンプ３８をさらに有する。配線基板３３は、第１の実施形態のランド１２の代わりに、ランド３２を有する。
　配線基板３３の上面には、ランド１１が配置された領域よりもランド３２が配置された領域（言い換えれば、半導体チップ２の下に位置する領域）が低くなるように、段差１９が形成されている。配線基板３３の上面における半導体チップ２の下に位置する領域には、凹部が形成されている。凹部の底面の上には、ランド３２が形成されている。バンプ３８は、配線基板３３のランド３２と配線１０との間に介在している。
　この構成により、半導体チップ２と配線基板３３との距離が大きくなり、半導体チップ２が放熱しやすくなるため、放熱性を高めることができる。さらに、放熱部材を取り付けることで、放熱性をさらに高めることも可能である。
　（第１の実施形態の変形例３）
　図４は、本変形例に係る半導体装置１３０の構成を模式的に示す断面図である。なお、図４において、簡略的に図示する為に、符号４，６～１０，１２，１４～１７の図示を省略している。
　図４に示すように、半導体装置１３０は、第１の実施形態のバンプ５の代わりに、ピラー２０を有する。ピラー２０は、配線基板３のランド１１と半導体チップ１の入出力パッド１３との間に介在している。ピラー２０を介して、配線基板３と半導体チップ１とが接続されている。
　接合部材として、バンプではなく柱状のピラー２０を用いることにより、接合部材の幅を、ランド１１の接合部の面積および入出力パッド１３の接合部の面積に応じて調整することが容易になるとともに、接合部材の高さを、半導体チップ２の厚みに応じて調整することが容易になる。具体的には例えば、半導体チップ２の厚みを薄くした場合、ランド１１の接合部の面積および入出力パッド１３の接合部の面積は保ったままで、ピラー２０の高さのみを低くすることが容易になり、半導体装置の薄型化が容易に実現できる。本明細書において、「ランド１１の接合部」とは、ランド１１における接合部材と接合する部分である。「入出力パッド１３の接合部」とは、入出力パッド１３における接合部材と接合する部分である。
　さらに、ランド１１の接合部の面積および入出力パッド１３の接合部の面積を、バンプを用いる場合と比べて、小さくすることが可能であり、半導体装置の小型化が実現できる。
　（第２の実施形態）
　図５は、本実施形態に係る半導体装置２００の一部の構成を模式的に示す断面図である。本実施形態に係る半導体装置２００について、第１の実施形態に係る半導体装置１００と共通する構成についての説明は省略し、相違点について説明する。
　半導体装置２００は、第１のビアであるビア２１と、第２の配線である配線２２とをさらに備え、第１の実施形態の配線１０の代わりに、配線５０を備えている。
　ビア２１は、拡張部９に形成され、かつ、配線基板３の上面に対して垂直な方向に拡張部９を貫通している。配線２２は、拡張型半導体チップの上面（言い換えれば、半導体チップ２の上面および拡張部９の上面）の上に、半導体チップ２の周縁部から拡張部９に亘って形成されている。配線５０は、拡張型半導体チップの下面（言い換えれば、半導体チップ２の下面および拡張部９の下面）の上に、半導体チップ２の周縁部から拡張部９に亘って形成されている。
　ビア２１は、配線５０と配線２２とを接続している。配線２２は、半導体チップ２の入出力パッド（図示省略）と接続されている。これにより、配線２２を、半導体チップ２の機能を引き出す配線として利用できる。さらに、配線２２は、バンプ４を介して、半導体チップ１のＲＤＬ７と接続されている。これにより、配線２２を、半導体チップ１の機能を引き出す配線として利用できる。配線５０は、配線基板３のランド１２と接続されている。
　本実施形態によると、半導体装置２００が、ビア２１および配線２２をさらに備え、第１の実施形態の配線１０の代わりに、配線５０を備えている。これにより、半導体チップ１，２の機能を配線基板３に引き出す経路が増加するため、配線リソースが増加し、半導体装置の性能を向上することができる。
　さらに、配線リソースの増加により、小型化および薄型化の制約となる配線を削除するなどして、半導体装置のさらなる小型化および薄型化を達成できる。
　本実施形態では、第１の実施形態の変形例１のように、配線５０とランド１２との間に、バンプを介在させてもよい。これにより、上述した第１の実施形態の変形例１と同様の効果を発揮することができる。
　本実施形態では、第１の実施形態の変形例２のように、配線基板の上面における半導体チップ２の下に位置する領域に凹部を形成し、凹部の底面の上に形成されたランドと配線５０との間にバンプを介在させてもよい。これにより、上述した第１の実施形態の変形例２と同様の効果を発揮することができる。
　本実施形態では、第１の実施形態の変形例３のように、バンプの代わりに、ピラーを用いてもよい。これにより、上述した第１の実施形態の変形例３と同様の効果を発揮することができる。
　（第３の実施形態）
　図６は、本実施形態に係る半導体装置３００の一部の構成を模式的に示す断面図である。本実施形態に係る半導体装置３００について、第２の実施形態に係る半導体装置２００と共通する構成についての説明は省略し、相違点について説明する。
　半導体装置３００は、第２のビアであるビア２３と、第３の配線である配線２４とをさらに備え、第２の実施形態の拡張部９の代わりに拡張部６９と、第２の実施形態の配線５０の代わりに配線６０とを備え、配線２４と入出力パッド１３との間にバンプ４をさらに有している。拡張部６９と半導体チップ２とから、拡張型半導体チップが構成されている。
　ビア２３は、拡張部６９に形成され、かつ、配線基板３の上面に対して垂直な方向に拡張部６９を貫通している。ビア２３は、ビア２１よりも外側に位置している。配線２４は、拡張部６９の上面の上に形成されている。配線２４は、配線２２と同時に形成されることが好ましい。
　拡張部６９は、第２の実施形態の拡張部９よりも側方に突出している。配線６０は、拡張型半導体チップの下面（言い換えれば、半導体チップ２の下面および拡張部６９の下面）の上に、半導体チップ２の周縁部から拡張部６９に亘って形成されている。
　ビア２１は、配線６０と配線２２とを接続している。ビア２３は、配線６０と配線２４とを接続している。配線６０は、配線基板３のランド１１，１２と接続されている。配線２４と半導体チップ１の入出力パッド１３とは、バンプ４を介して接続されている。
　上述の第２の実施形態では、バンプ５を介して、半導体チップ１の入出力パッド１３と、配線基板３のランド１１とが接続されている。これに対し、本実施形態では、バンプ４、配線２４、ビア２３及び配線６０を介して、半導体チップ１の入出力パッド１３と、配線基板３のランド１１とが接続されている。よって、本実施形態に係る半導体装置３００は、第２の実施形態のバンプ５を有さない。
　本実施形態によると、半導体チップ１，２の機能の引き出しに、バンプではなく、ビア２３を用いることができる。これにより、バンプを形成する必要がなくなり、工程が簡略化される。さらに、バンプの幅よりもビア２３の幅を小さくすることで、半導体装置を小型化できる。
　（第３の実施形態の変形例１）
　図７は、本変形例に係る半導体装置３１０の構成を模式的に示す断面図である。なお、図７において、簡略的に図示する為に、符号１，３，４，６～８，１３～１７の図示を省略している。
　図７に示すように、半導体装置３１０は、第４の配線である配線２５をさらに備え、第３の実施形態の配線６０の代わりに配線７０を備えている。
　配線２５は、拡張部６９の下面の上に形成されている。配線７０は、拡張型半導体チップの下面（言い換えれば、半導体チップ２の下面および拡張部６９の下面）の上に、半導体チップ２の周縁部から拡張部６９に亘って形成されている。
　ビア２１は、配線７０と配線２２とを接続している。ビア２３は、配線２５と配線２４とを接続している。配線７０は、配線基板３のランド１２と接続されている。配線２５は、配線基板３のランド１１と接続されている。
　この構成により、ランド１１とランド１２とがそれぞれ個別の引き出し経路となるため、出力経路の自由度が向上し、半導体装置の特性が向上する。
　（第３の実施形態の変形例２）
　図８は、本変形例に係る半導体装置３２０の構成を模式的に示す断面図である。なお、図８において、簡略的に図示する為に、符号１，４，６～８，１３～１７，２１～２４，６９の図示を省略している。
　図８に示すように、半導体装置３２０は、バンプ８８をさらに有する。バンプ８８は、配線基板３のランド１１，１２と配線６０との間に介在している。バンプ８８を介して、配線基板３と配線６０とが接続されている。
　この構成により、半導体チップ２と配線基板３との距離が大きくなり、半導体チップ２が放熱しやすくなるため、放熱性を高めることができる。さらに、放熱部材を取り付けることで、放熱性をさらに高めることも可能である。
　＜第１の実施形態に係る半導体装置の製造方法＞
　図９～１２は、第１の実施形態に係る半導体装置１００の製造方法の一例を示す図である。
　まず、図９に示すように、上面の上に形成された入出力パッド（図示省略）を有し、かつ、下面の上に半導体チップ２の周縁部から拡張部９に亘って配線１０が形成された拡張型半導体チップ９２を準備する。
　上面の上にランド１１，１２が形成され、下面の上に外部端子１５，１７が形成され、内部に配線経路１４，１６が形成された配線基板３を準備する。
　次に、図１０に示すように、配線１０がランド１１，１２に接続するように、拡張型半導体チップ９２を配線基板３の上に搭載する。拡張型半導体チップ９２と配線基板３との間に接着部材を挿入して、拡張型半導体チップ９２を配線基板３に固着してもよい。
　次に、図１１に示すように、配線基板３と電気的に接続するための複数の入出力パッド１３と、半導体チップ２と電気的に接続するための複数の入出力パッド（図示省略）とを有し、かつ、図示を省略した入出力パッドの上にバンプ４が形成された半導体チップ１を準備する。
　次に、配線基板３のランド１１の上に、バンプ５を形成する。このとき、バンプ５の最上点が半導体チップ２の上面よりも上に位置するように、バンプ５を形成する。バンプ５の形成方法としては、例えば、電解めっき、搭載または印刷などが考えられる。
　次に、拡張型半導体チップ９２の上面の上に、樹脂シート材１０１を塗布する。
　次に、入出力パッド１３がバンプ５と対向すると共に、バンプ４が半導体チップ２の入出力パッド（図示省略）と対向するように、拡張型半導体チップ９２が搭載された配線基板３の上方に、半導体チップ１を配置する。
　最後に、図１２に示すように、半導体チップ１を、拡張型半導体チップ９２の上に積層するとともに、配線基板３の上に搭載する。このとき、半導体チップ１の入出力パッド１３とバンプ５とが接合される。これにより、バンプ５を介して、配線基板３のランド１１と半導体チップ１の入出力パッド１３とが接続される。さらに、このとき、バンプ４と半導体チップ２の入出力パッド（図示省略）とが接合する。これにより、バンプ４を介して、半導体チップ１の入出力パッド（図示省略）と半導体チップ２の入出力パッド（図示省略）とが接続される。このＣｏＣ接合は、Ｃ４（Controlled Collapse Chip Connection）工法またはスクラブなどで形成される。
　以上のようにして、半導体装置１００を製造することができる。
　なお、半導体チップ１を搭載する前に、拡張型半導体チップ９２の上面の上に樹脂シート材１０１を形成する代わりに、半導体チップ１を搭載した後に、半導体チップ１と半導体チップ２との間にアンダーフィル樹脂を注入してもよい。
　第１～第３の実施形態およびそれらの変形例において、ＲＤＬ７および配線１０，５０，６０，７０，２２，２５は、半導体チップ１，２の回路６，８内に拡散にて構成されたファイン配線よりも、幅広で厚く形成されていてもよい。この場合、例えば、ＲＤＬ７および配線１０，５０，６０，７０，２２，２５の厚みは、３μｍ～２０μｍである。この構成により、ＲＤＬ７および配線１０，５０，６０，７０，２２，２５の抵抗をファイン配線の抵抗よりも小さくすることができるため、ＲＤＬ７および／または配線１０，５０，６０，７０，２２，２５を電源供給用の配線として用いる際に、より安定した電源供給が可能である。
　また、複数のバンプ４は、１００μｍ以下のピッチで配置されるのが望ましい。バンプ４は、例えば、はんだ、銅（Ｃｕ）またはニッケル（Ｎｉ）などの金属からなる。
　また、バンプ５およびピラー２０は、例えば、Ｃｕなどの金属からなる。
　また、接続信頼性確保の観点から、配線基板３のランド１１は、半導体チップ１の入出力パッド１３の真下に配置されることが望ましい。配線自由度向上の観点から、配線基板３のランド１２は、ランド１２の全部が半導体チップ２の真下に配置されることが望ましい。
　また、拡張部９，６９は、例えば、エポキシ樹脂からなる。
　また、ビア２１，２３は、例えば、レーザー照射により、拡張部に貫通穴を形成した後、貫通穴内にはんだまたはＣｕを埋め込んで形成される。
　以上、本発明を、第１～第３の実施形態およびそれらの変形例に基づいて詳細に説明したが、本発明は、上述した実施形態等に限られるものではない。本発明の主旨を逸脱しない限りにおいて変形または変更が可能である。例えば、複数の実施形態を組み合わせたもの、および構成要素の一部を実施形態等に記載されていない代替物に置き換えたものも、本発明の範疇とする。
　本発明は、配線リソースの増加により、半導体装置の性能を向上することができ、ＣｏＣ型の半導体装置を用いた電子機器に幅広く適用できる。
１　半導体チップ（第１の半導体チップ）
２　半導体チップ（第２の半導体チップ）
３，３３　配線基板
４　バンプ
５　バンプ
６　回路
７　再配線層（ＲＤＬ）
８　回路
９，６９　拡張部
１０，５０，６０，７０　配線（第１の配線）
１１　ランド
１２，３２　ランド
１３　入出力パッド
１４　配線経路
１５　外部端子
１６　配線経路
１７　外部端子
１８，３８，８８　バンプ
１９　段差
２０　ピラー
２１　ビア（第１のビア）
２２　配線（第２の配線）
２３　ビア（第２のビア）
２４　配線（第３の配線）
２５　配線（第４の配線）
９２　拡張型半導体チップ
１００，１１０，１２０，１３０，２００，３００，３１０，３２０　半導体装置
１０１　樹脂シート材

Claims (8)

  1. 　第１の半導体チップと、
    　上面が前記第１の半導体チップの上面と向かい合って配置され、前記第１の半導体チップのサイズよりも小さい第２の半導体チップと、
    　前記第２の半導体チップの側面から外方に向かって形成された拡張部と、
    　上面が前記第１の半導体チップの上面と向かい合って配置され、かつ、上面が前記第２の半導体チップの下面と向かい合って配置された配線基板とを備え、
    　前記第２の半導体チップの下面および前記拡張部の下面の上に形成され、前記配線基板と接続された第１の配線をさらに備えていることを特徴とする半導体装置。
  2. 　前記第１の配線と前記配線基板とは、バンプを介して接続されていることを特徴とする請求項１に記載の半導体装置。
  3. 　前記配線基板の上面における前記第２の半導体チップの下に位置する領域には、凹部が形成されていることを特徴とする請求項１または２に記載の半導体装置。
  4. 　前記第１の半導体チップと前記配線基板とは、ピラーを介して接続されていることを特徴とする請求項１～３のうちいずれか１項に記載の半導体装置。
  5. 　前記拡張部に形成され、前記拡張部を貫通する第１のビアと、
    　前記第２の半導体チップの上面および前記拡張部の上面の上に形成され、バンプを介して前記第１の半導体チップと接続された第２の配線とをさらに備え、
    　前記第１のビアは、前記第１の配線と前記第２の配線とを接続していることを特徴とする請求項１に記載の半導体装置。
  6. 　前記拡張部に形成され、前記拡張部を貫通する第２のビアと、
    　前記拡張部の上面の上に形成され、バンプを介して前記第１の半導体チップと接続された第３の配線とをさらに備え、
    　前記第２のビアは、前記第１の配線と前記第３の配線とを接続していることを特徴とする請求項１または５に記載の半導体装置。
  7. 　前記拡張部に形成され、前記拡張部を貫通する第２のビアと、
    　前記拡張部の上面の上に形成され、バンプを介して前記第１の半導体チップと接続された第３の配線と、
    　前記拡張部の下面の上に形成され、前記配線基板と接続された第４の配線とをさらに備え、
    　前記第２のビアは、前記第３の配線と前記第４の配線とを接続していることを特徴とする請求項５に記載の半導体装置。
  8. 　前記第１の配線と前記配線基板とは、バンプを介して接続されていることを特徴とする請求項６に記載の半導体装置。
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