CN103620776B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN103620776B
CN103620776B CN201280031587.1A CN201280031587A CN103620776B CN 103620776 B CN103620776 B CN 103620776B CN 201280031587 A CN201280031587 A CN 201280031587A CN 103620776 B CN103620776 B CN 103620776B
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mentioned
semiconductor chip
wiring
extension
circuit board
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CN201280031587.1A
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CN103620776A (zh
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永井纪行
土肥茂史
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

半导体装置具备：第1半导体芯片(1)；上表面与第1半导体芯片(1)的上表面相向配置，比第1半导体芯片(1)的尺寸小的第2半导体芯片(2)；从第2半导体芯片(2)的侧面朝向外侧而形成的扩展部(9)；和上表面与第1半导体芯片(1)的上表面相向配置，并且上表面与第2半导体芯片(2)的下表面相向配置的布线基板(3)。半导体装置还具备第1布线(10)，该第1布线(10)形成于第2半导体芯片(2)的下表面以及扩展部(9)的下表面上，与布线基板(3)连接。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别是涉及CoC(Chip on Chip)型的半导体装置。
背景技术
在半导体装置中，除了实现小型化以及轻薄化，同时实现高性能化的必要性在不断提高。作为其事例，经由凸起等的接合构件将芯片的功能面彼此接合的CoC型的半导体装置正广泛普及。在CoC型的半导体装置的情况下，能实现上下芯片间的信号控制的高速化、以及由不同种类工艺构成的芯片彼此的组合，半导体装置的通用性得到提高。
专利文献1记载了CoC型的半导体装置。
专利文献1记载的以往的半导体装置具有母基板、在母基板之上配置的第1芯片和在第1芯片之上配置的第2芯片。
第1芯片与第2芯片经由焊锡凸起连接。第2芯片(上侧的芯片)的尺寸比第1芯片(下侧的芯片)的尺寸大，第2芯片的周边部与第1芯片的侧面相比进一步向侧方突出。突出的第2芯片的周边部经由焊锡电极而与母基板连接。
第1芯片的功能经由将第1芯片与第2芯片连接的焊锡凸起、第2芯片内的布线、以及将第2芯片与母基板连接的焊锡电极，被引出到母基板。第2芯片的功能经由将第2芯片与母基板连接的焊锡电极，被引出到母基板。
在先技术文献
专利文献
专利文献1：特开2004-146728号公报
发明内容
发明要解决的课题
然而，在以往的半导体装置中存在以下问题。
在以往的半导体装置中，第1芯片的功能以及第2芯片的功能双方经由焊锡电极被引出到母基板。
然而，母基板的布线资源少，布线自由度小。因此，存在如下问题：在母基板上无法形成与被引出的第1芯片的功能以及第2芯片的功能双方对应的足够的布线，半导体装置的性能降低。
鉴于上述，本发明的目的在于，在CoC型的半导体装置中，通过增加引出半导体芯片的功能的布线资源，来提高半导体装置的性能。
用于解决课题的手段
为了达到上述目的，本发明所涉及的半导体装置，其特征在于具备：第1半导体芯片；第2半导体芯片，其上表面与第1半导体芯片的上表面相向配置，比第1半导体芯片的尺寸小；扩展部，其从第2半导体芯片的侧面朝向外侧而形成；和布线基板，其上表面与第1半导体芯片的上表面相向配置，并且上表面与第2半导体芯片的下表面相向配置，半导体装置还具备第1布线，该第1布线形成在第2半导体芯片的下表面以及扩展部的下表面上，并与布线基板连接。
发明效果
根据本发明，在CoC型的半导体装置中，由于引出半导体芯片功能的布线资源增加，所以能提高半导体装置的性能。
附图说明
图1是示意性表示本发明的第1实施方式所涉及的半导体装置的构成的剖面图。
图2是示意性表示本发明的第1实施方式的变形例1所涉及的半导体装置的构成的剖面图。
图3是示意性表示本发明的第1实施方式的变形例2所涉及的半导体装置的构成的剖面图。
图4是示意性表示本发明的第1实施方式的变形例3所涉及的半导体装置的构成的剖面图。
图5是示意性表示本发明的第2实施方式所涉及的半导体装置的构成的剖面图。
图6是示意性表示本发明的第3实施方式所涉及的半导体装置的构成的剖面图。
图7是示意性表示本发明的第3实施方式的变形例1所涉及的半导体装置的构成的剖面图。
图8是示意性表示本发明的第3实施方式的变形例2所涉及的半导体装置的构成的剖面图。
图9是示意性表示本发明的第1实施方式所涉及的半导体装置的制造工序的一个例子的剖面图。
图10是示意性表示本发明的第1实施方式所涉及的半导体装置的制造工序的一个例子的剖面图。
图11是示意性表示本发明的第1实施方式所涉及的半导体装置的制造工序的一个例子的剖面图。
图12是示意性表示本发明的第1实施方式所涉及的半导体装置的制造工序的一个例子的剖面图。
具体实施方式
利用附图对本发明所涉及的半导体装置进行说明。对在全部的附图中共用的构成要素标记相同的附图标记，并适当地省略说明。
(第1实施方式)
图1是示意性表示本实施方式所涉及的半导体装置100的一部分构成的剖面图。
半导体装置100具备作为第1半导体芯片的半导体芯片1、作为第2半导体芯片的半导体芯片2、扩展部9和布线基板3。半导体芯片2被搭载于布线基板3之上。半导体芯片1被层叠于半导体芯片2之上，并且被搭载于布线基板3之上。半导体芯片1与半导体芯片2经由凸起4连接。半导体芯片1与布线基板3经由凸起5连接。
半导体芯片1具有：形成在硅基板之上，并且具有电气特性功能的电路6；和形成在电路6之上，并且与电路6连接的再布线层(RDL，Re-Distribustion Layer)7。半导体芯片1还具有：形成在上表面的周边部之上，并且分别与布线基板3电连接的多个输入输出焊盘13；和形成在上表面的中央部之上，并且分别与半导体芯片2电连接的多个输入输出焊盘(省略图示)。在本说明书中，“半导体芯片1的上表面”是形成有RDL7一侧的面。
通过上述构成，半导体芯片1的功能能够经由RDL7、输入输出焊盘13与凸起5而被引出到布线基板3。
半导体芯片2具有电路8，该电路8被形成在硅基板之上，并且具有电气特性功能。半导体芯片2还具有被形成在上表面上并且分别与半导体芯片1电连接的多个输入输出焊盘(省略图示)。在本说明书中，“半导体芯片2的上表面”是形成有电路8一侧的面。
半导体芯片2的尺寸比半导体芯片1的尺寸小。半导体芯片2的上表面与半导体芯片1的上表面相向。
扩展部9与半导体芯片2的侧面接触，并且从半导体芯片2的侧面朝向外侧而形成。扩展部9是绝缘性的，例如由树脂构成。由半导体芯片2与扩展部9构成扩展型半导体芯片。扩展型半导体芯片的尺寸比半导体芯片1的尺寸小，半导体芯片1的周边部与扩展型半导体芯片的侧面相比进一步向侧方突出。
半导体装置100还具备作为第1布线的布线10。布线10在扩展型半导体芯片的下表面(换句话说，半导体芯片2的下表面以及扩展部9的下表面)之上，从半导体芯片2的周边部开始遍及扩展部9而形成。布线10与布线基板3连接。在本说明书中，“扩展型半导体芯片的下表面”是与布线基板3相向的面。
通过上述构成，半导体芯片2的功能经由凸起4、RDL7、输入输出焊盘13与凸起5而引出到布线基板3。
布线基板3具有在上表面上形成的多个连接盘(land)11、12、在下表面上形成的多个外部端子15、17和在内部形成的多个布线路径14、16。
布线基板3的上表面与半导体芯片1的上表面相向，并且与半导体芯片2的下表面相向。在本说明书中，“布线基板3的上表面”是形成有连接盘11、12的面。
布线路径14将连接盘11与外部端子15连接。布线路径16将连接盘12与外部端子17连接。
连接盘11经由凸起5，与半导体芯片1的输入输出焊盘13连接，并且与布线10的一部分连接。连接盘12与布线10的一部分连接，具体地说与布线10中与连接于连接盘11连接的部分不同的部分连接。连接盘11、12与布线10的连接例如可以通过将导电性的膏剂(省略图示)涂覆于连接盘11、12或者布线10来进行。此外，连接盘11、12与布线10的连接例如还可以在使连接盘11、12与布线10接触的状态下施加振动来进行。
通过上述构成，能将半导体芯片1、2的功能从连接盘11经由布线基板3内的布线路径14向外部端子15引出，进而从连接盘12经由布线基板3内的布线路径16向外部端子17引出。
根据本实施方式，在半导体芯片1、2的上表面彼此相互相向配置、半导体芯片1与半导体芯片2相比进一步向侧方突出的半导体装置中，能将半导体芯片1的RDL7用于引出半导体芯片1的功能。进而，也能将半导体芯片1的RDL7用于引出半导体芯片2的功能。RDL7优选在半导体芯片1被单片化前的晶片的状态下形成。由此，与在将半导体芯片1单片化后形成RDL的情况相比，能高效地形成RDL7。
进而，能将布线10用于引出半导体芯片1、2的功能。由此，布线资源增加，能实现引出布线的自由度的提高。通过这样的布线资源的增加以及引出布线的自由度的提高，能满足半导体装置的小型化以及轻薄化的要求，同时能提高半导体装置的性能。
(第1实施方式的变形例1)
图2是示意性表示本变形例所涉及的半导体装置110的构成的剖面图。此外，在图2中为了简化图示而省略了附图标记1、4～9、13～17的图示。
如图2所示，半导体装置110还具有凸起18。凸起18介于布线基板3的连接盘11、12与布线10之间。经由凸起18，将布线基板3与布线10连接。
通过该构成，能使半导体芯片2的厚度变薄。进而，半导体芯片2与布线基板3的距离变大，半导体芯片2容易散热。进而，能借助凸起18稳定地保持布线10与连接盘11、12的连接。
(第1实施方式的变形例2)
图3是示意性表示本变形例所涉及的半导体装置120的构成的剖面图。此外，在图3中为了省略图示而省略了附图标记1、4～9、13～17的图示。
如图3所示，半导体装置120取代第1实施方式的布线基板3而具有布线基板33，还具有凸起38。布线基板33取代第1实施方式的连接盘12而具有连接盘32。
在布线基板33的上表面，按照配置有连接盘32的区域(换句话说，位于半导体芯片2之下的区域)低于配置有连接盘11的区域的方式，形成有阶梯差19。在布线基板33的上表面的位于半导体芯片2之下的区域形成有凹部。在凹部的底面之上形成有连接盘32。凸起38介于布线基板33的连接盘32与布线10之间。
通过该构成，由于半导体芯片2与布线基板33的距离变大，半导体芯片2变得容易散热，所以能提高散热性。进而，通过安装散热构件，从而也能进一步提高散热性。
(第1实施方式的变形例3)
图4是示意性表示本变形例所涉及的半导体装置130的构成的剖面图。此外，在图4中，为了省略图示，省略了附图标记4、6～10、12、14～17的图示。
如图4所示，半导体装置130取代第1实施方式的凸起5而具有支柱20。支柱20介于布线基板3的连接盘11与半导体芯片1的输入输出焊盘13之间。经由支柱20，布线基板3与半导体芯片1被连接起来。
作为接合构件，通过采用柱状的支柱20而不是凸起，从而根据连接盘11的接合部的面积以及输入输出焊盘13的接合部的面积来调整接合构件的宽度变得容易，并且根据半导体芯片2的厚度来调整接合构件的高度变得容易。具体地说，例如，在将半导体芯片2的厚度变薄了的情况下，在连接盘11的接合部的面积以及输入输出焊盘13的接合部的面积保持不变的状态下，仅降低支柱20的高度变得容易，能容易地实现半导体装置的轻薄化。在本说明书中，“连接盘11的接合部”是连接盘11中的与接合构件接合的部分。“输入输出焊盘13的接合部”是输入输出焊盘13中的与接合构件接合的部分。
进而，与使用凸起的情况相比，能减小连接盘11的接合部的面积以及输入输出焊盘13的接合部的面积，能实现半导体装置的小型化。
(第2实施方式)
图5是示意性表示本实施方式所涉及的半导体装置200的一部分构成的剖面图。关于本实施方式所涉及的半导体装置200，省略了与第1实施方式所涉及的半导体装置100共用的构成的说明，对不同点进行说明。
半导体装置200还具备作为第1过孔的过孔21和作为第2布线的布线22，并且取代第1实施方式的布线10而具有布线50。
过孔21形成于扩展部9，并且在与布线基板3的上表面垂直的方向上贯通扩展部9。布线22在扩展型半导体芯片的上表面(换句话说，半导体芯片2的上表面以及扩展部9的上表面)之上，从半导体芯片2的周边部开始遍及扩展部9而形成。布线50在扩展型半导体芯片的下表面(换句话说，半导体芯片2的下表面以及扩展部9的下表面)上，从半导体芯片2的周边部开始遍及扩展部9而形成。
过孔21将布线50与布线22连接。布线22与半导体芯片2的输入输出焊盘(省略图示)连接。由此，能将布线22用作引出半导体芯片2的功能的布线。进而，布线22经由凸起4而与半导体芯片1的RDL7连接。由此，能将布线22用作引出半导体芯片1的功能的布线。布线50与布线基板3的连接盘12连接。
根据本实施方式，半导体装置200还具备过孔21以及布线22，并且取代第1实施方式的布线10而具有布线50。由此，由于将半导体芯片1、2的功能引出到布线基板3的路径增加，所以布线资源增加，能提高半导体装置的性能。
进而，通过布线资源的增加，能消除成为小型化以及轻薄化的制约的布线等，能实现半导体装置的进一步小型化以及轻薄化。
在本实施方式中，也可以如第1实施方式的变形例1那样，使凸起介于布线50与连接盘12之间。由此，能发挥与上述的第1实施方式的变形例1相同的效果。
在本实施方式中，也可以如第1实施方式的变形例2那样，在布线基板的上表面的位于半导体芯片2之下的区域形成凹部，使凸起介于凹部的底面之上形成的连接盘与布线50之间。由此，能发挥与上述的第1实施方式的变形例2相同的效果。
在本实施方式中，也可以如第1实施方式的变形例3那样，取代凸起而使用支柱。由此，能发挥与上述的第1实施方式的变形例3相同的效果。
(第3实施方式)
图6是示意性表示本实施方式所涉及的半导体装置300的一部分构成的剖面图。关于本实施方式所涉及的半导体装置300，省略与第2实施方式所涉及的半导体装置200共用的构成的说明，对不同点进行说明。
半导体装置300还具备作为第2过孔的过孔23和作为第3布线的布线24，并且取代第2实施方式的扩展部9而具有扩展部69、取代第2实施方式的布线50而具有布线60，在布线24与输入输出焊盘13之间还具有凸起4。由扩展部69与半导体芯片2构成扩展型半导体芯片。
过孔23形成于扩展部69，并且在与布线基板3的上表面垂直的方向上贯通扩展部69。过孔23位于过孔21的外侧。布线24形成在扩展部69的上表面上。布线24优选与布线22同时形成。
扩展部69与第2实施方式的扩展部9相比进一步向侧方突出。布线60在扩展型半导体芯片的下表面(换句话说，半导体芯片2的下表面以及扩展部69的下表面)上，从半导体芯片2的周边部开始遍及扩展部69而形成。
过孔21将布线60与布线22连接。过孔23将布线60与布线24连接。布线60与布线基板3的连接盘11、12连接。布线24与半导体芯片1的输入输出焊盘13经由凸起4连接。
在上述的第2实施方式中，经由凸起5，半导体芯片1的输入输出焊盘13、布线基板3的连接盘11被连接起来。与此相对，在本实施方式中，经由凸起4、布线24、过孔23以及布线60，将半导体芯片1的输入输出焊盘13、布线基板3的连接盘11连接起来。由此，本实施方式所涉及的半导体装置300不具有第2实施方式的凸起5。
根据本实施方式，不使用凸起，而是使用过孔23来引出半导体芯片1、2的功能。由此，不需要形成凸起，从而简化工序。进而，通过与凸起的宽度相比减小过孔23的宽度，从而能使半导体装置小型化。
(第3实施方式的变形例1)
图7是示意性表示本变形例所涉及的半导体装置310的构成的剖面图。此外，在图7中，为了省略图示而省略了附图标记1、3、4、6～8、13～17的图示。
如图7所示，半导体装置310还具有作为第4布线的布线25，取代第3实施方式的布线60而具有布线70。
布线25被形成于扩展部69的下表面上。布线70在扩展型半导体芯片的下表面(换句话说，半导体芯片2的下表面以及扩展部69的下表面)上，从半导体芯片2的周边部开始遍及扩展部69而形成。
过孔21将布线70与布线22连接。过孔23将布线25与布线24连接。布线70与布线基板3的连接盘12连接。布线25与布线基板3的连接盘11连接。
通过该构成，由于连接盘11与连接盘12分别成为分开的引出路径，所以输出路径的自由度提高，半导体装置的特性提高。
(第3实施方式的变形例2)
图8是示意性表示本变形例所涉及的半导体装置320的构成的剖面图。此外，在图8中，为了省略图示，省略了附图标记1、4、6～8、13～17、21～24、69的图示。
如图8所示，半导体装置320还具有凸起88。凸起88介于布线基板3的连接盘11、12与布线60之间。经由凸起88，将布线基板3与布线60连接。
通过该构成，由于半导体芯片2与布线基板3的距离变大，半导体芯片2容易散热，所以能提高散热性。进而通过安装散热构件，从而也能进一步提高散热性。
<第1实施方式所涉及的半导体装置的制造方法>
图9～12是表示第1实施方式所涉及的半导体装置100的制造方法的一个例子的图。
首先，如图9所示，准备扩展型半导体芯片92，该扩展型半导体芯片92具有形成在上表面上的输入输出焊盘(省略图示)，并且在下表面上从半导体芯片2的周边部开始遍及扩展部9而形成了布线10。
准备布线基板3，该布线基板3在上表面上形成了连接盘11、12，在下表面上形成了外部端子15、17，在内部形成了布线路径14、16。
接下来，如图10所示，按照布线10与连接盘11、12连接的方式，将扩展型半导体芯片92安装于布线基板3之上。也可以在扩展型半导体芯片92与布线基板3之间插入粘接构件，将扩展型半导体芯片92固定于布线基板3。
接下来，如图11所示，准备半导体芯片1，该半导体芯片1具有用于与布线基板3电连接的多个输入输出焊盘13、和用于与半导体芯片2电连接的多个输入输出焊盘(省略图示)，并且在省略了图示的输入输出焊盘之上形成了凸起4。
接下来，在布线基板3的连接盘11之上形成凸起5。此时，按照凸起5的最上点位于半导体芯片2的上表面上方的方式形成凸起5。作为凸起5的形成方法，可以考虑例如电解电镀、搭载或者印刷等。
接下来，在扩展型半导体芯片92的上表面上，涂覆树脂片材101。
接下来，按照输入输出焊盘13与凸起5对置，并且凸起4与半导体芯片2的输入输出焊盘(省略图示)对置的方式，在搭载了扩展型半导体芯片92的布线基板3的上方，配置半导体芯片1。
最后，如图12所示，将半导体芯片1层叠于扩展型半导体芯片92之上，并且搭载于布线基板3之上。此时，半导体芯片1的输入输出焊盘13与凸起5被接合。由此，经由凸起5，布线基板3的连接盘11与半导体芯片1的输入输出焊盘13被连接。进而，此时，凸起4与半导体芯片2的输入输出焊盘(省略图示)接合。由此，经由凸起4，半导体芯片1的输入输出焊盘(省略图示)与半导体芯片2的输入输出焊盘(省略图示)被连接。该CoC接合利用C4(ControlledCollapse Chip Connection)方法或者擦刷等形成。
像以上那样，能制造出半导体装置100。
此外，也可以取代搭载半导体芯片1前在扩展型半导体芯片92的上表面上形成树脂片材101，而是在搭载了半导体芯片1后，在半导体芯片1与半导体芯片2之间注入底层填料树脂。
在第1～第3实施方式以及它们的变形例中，RDL7以及布线10、50、60、70、22、25也可以与在半导体芯片1、2的电路6、8内通过扩散构成的细丝布线相比，形成为宽度更宽、更厚。在该情况下，例如，RDL7以及布线10、50、60、70、22、25的厚度是3μm～20μm。通过该构成，能使RDL7以及布线10、50、60、70、22、25的电阻比细丝布线的电阻更小，所以在将RDL7以及/或者布线10、50、60、70、22、25用作电源供给用的布线之际，能提供更稳定的电源。
另外，多个凸起4优选以100μm以下的间距配置。凸起4例如由焊锡、铜(Cu)或者镍(Ni)等的金属构成。
另外，凸起5以及支柱20例如由Cu等的金属构成。
另外，从确保连接可靠性的观点出发，优选布线基板3的连接盘11配置在半导体芯片1的输入输出焊盘13的正下。从提高布线自由度的观点出发，关于布线基板3的连接盘12，优选连接盘12全部配置在半导体芯片2的正下。
另外，扩展部9、69例如由环氧树脂构成。
另外，过孔21、23例如通过激光照射而在扩展部形成了贯通孔后，在贯通孔内埋入焊锡或者Cu来形成。
以上，基于第1～第3实施方式以及它们的变形例对本发明详细地进行了说明，但本发明并不限定于上述的实施方式等。只要在不脱离本发明的主旨的情况下可以进行变形或者变更。例如，组合多个实施方式而得到的方案、以及将构成要素的一部分置换为实施方式等没有记载的代替物而得到的方案，均属于本发明的范畴。
工业实用性
本发明通过增加布线资源，从而能提高半导体装置的性能，能广泛适用于采用了CoC型半导体装置的电子设备。
-符号说明-
1 半导体芯片(第1半导体芯片)
2 半导体芯片(第2半导体芯片)
3、33 布线基板
4 凸起
5 凸起
6 电路
7 再布线层(RDL)
8 电路
9、69 扩展部
10、50、60、70 布线(第1布线)
11 连接盘
12、32 连接盘
13 输入输出焊盘
14 布线路径
15 外部端子
16 布线路径
17 外部端子
18、38、88 凸起
19 阶梯差
20 支柱
21 过孔(第1过孔)
22 布线(第2布线)
23 过孔(第2过孔)
24 布线(第3布线)
25 布线(第4布线)
92 扩展型半导体芯片
100、110、120、130、200、300、310、320 半导体装置
101 树脂片材

Claims (8)

1.一种半导体装置，其特征在于具备：
第1半导体芯片；
第2半导体芯片，其上表面与上述第1半导体芯片的上表面相向配置，比上述第1半导体芯片的尺寸小；
扩展部，其从上述第2半导体芯片的侧面朝向外侧而形成；和
布线基板，其上表面与上述第1半导体芯片的上表面相向配置，并且上表面与上述第2半导体芯片的下表面相向配置，
上述半导体装置还具备第1布线，该第1布线形成为自上述第2半导体芯片的下表面的周边部之上开始遍及上述扩展部的下表面之上且横跨上述第2半导体芯片的下表面及上述扩展部的下表面，并与上述布线基板连接，
上述第1布线经由形成在上述布线基板上的相异的多个连接盘而与上述布线基板连接。
2.根据权利要求1所述的半导体装置，其特征在于，
在上述布线基板的上表面的位于上述第2半导体芯片下的区域形成有凹部。
3.根据权利要求1所述的半导体装置，其特征在于，
上述第1半导体芯片与上述布线基板经由支柱而连接。
4.根据权利要求1所述的半导体装置，其特征在于，
上述第1布线与上述布线基板经由凸起连接。
5.根据权利要求1所述的半导体装置，其特征在于，
还具备：
第1过孔，其形成于上述扩展部，并贯通上述扩展部；和
第2布线，其形成于上述第2半导体芯片的上表面以及上述扩展部的上表面上，经由凸起而与上述第1半导体芯片连接，
上述第1过孔将上述第1布线与上述第2布线连接。
6.一种半导体装置，其特征在于，具备：
第1半导体芯片；
第2半导体芯片，其上表面与上述第1半导体芯片的上表面相向配置，比上述第1半导体芯片的尺寸小；
扩展部，其从上述第2半导体芯片的侧面朝向外侧而形成；
布线基板，其上表面与上述第1半导体芯片的上表面相向配置，并且上表面与上述第2半导体芯片的下表面相向配置；
第1布线，该第1布线形成为自上述第2半导体芯片的下表面的周边部之上开始遍及上述扩展部的下表面之上且横跨上述第2半导体芯片的下表面及上述扩展部的下表面，并与上述布线基板连接；
第2布线，其形成于上述第2半导体芯片的上表面以及上述扩展部的上表面上，经由凸起而与上述第1半导体芯片连接；
第3布线，其形成于上述扩展部的上表面上，经由凸起而与上述第1半导体芯片连接；
第4布线，其形成于上述扩展部的下表面上，与上述布线基板连接；
第1过孔，其形成于上述扩展部，并贯通上述扩展部；和
第2过孔，其形成于上述扩展部，并贯通上述扩展部，
上述第1过孔将上述第1布线与上述第2布线连接，
上述第2过孔将上述第3布线与上述第4布线连接。
7.一种半导体装置，其特征在于，具备：
第1半导体芯片；
第2半导体芯片，其上表面与上述第1半导体芯片的上表面相向配置，比上述第1半导体芯片的尺寸小；
扩展部，其从上述第2半导体芯片的侧面朝向外侧而形成；
布线基板，其上表面与上述第1半导体芯片的上表面相向配置，并且上表面与上述第2半导体芯片的下表面相向配置；
第1布线，该第1布线形成为自上述第2半导体芯片的下表面的周边部之上开始遍及上述扩展部的下表面之上且横跨上述第2半导体芯片的下表面及上述扩展部的下表面，并与上述布线基板连接；
第2布线，其形成于上述第2半导体芯片的上表面以及上述扩展部的上表面上，经由凸起而与上述第1半导体芯片连接；
第3布线，其形成于上述扩展部的上表面上，经由凸起而与上述第1半导体芯片连接；
第1过孔，其形成于上述扩展部，并贯通上述扩展部；和
第2过孔，其形成于上述扩展部，并贯通上述扩展部，
上述第1过孔将上述第1布线与上述第2布线连接，
上述第2过孔将上述第1布线与上述第3布线连接。
8.根据权利要求7所述的半导体装置，其特征在于，
上述第1布线与上述布线基板经由凸起而连接。
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