WO2012005352A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2012005352A1
WO2012005352A1 PCT/JP2011/065693 JP2011065693W WO2012005352A1 WO 2012005352 A1 WO2012005352 A1 WO 2012005352A1 JP 2011065693 W JP2011065693 W JP 2011065693W WO 2012005352 A1 WO2012005352 A1 WO 2012005352A1
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WO
WIPO (PCT)
Prior art keywords
bump
semiconductor device
layer
electrode pad
post
Prior art date
Application number
PCT/JP2011/065693
Other languages
English (en)
French (fr)
Inventor
弘守 奥村
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to US13/809,211 priority Critical patent/US9070673B2/en
Publication of WO2012005352A1 publication Critical patent/WO2012005352A1/ja
Priority to US14/722,895 priority patent/US9508672B2/en
Priority to US15/347,861 priority patent/US10068823B2/en

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Definitions

  • the present invention relates to a semiconductor device.
  • a semiconductor device provided with a semiconductor chip is known (see, for example, Patent Document 1).
  • a plurality of bumps are formed in a ball grid type semiconductor device such as a chip size package (CSP) or a ball grid array (BGA).
  • the semiconductor device is mounted on the mounting substrate (electrically and mechanically connected to the mounting substrate) by bonding a plurality of bumps to the mounting pad formed on the mounting substrate.
  • An object of the present invention is to provide a semiconductor device which has been conceived under the above-described circumstances and which is suitable for suppressing malfunction.
  • a semiconductor chip a first electrode pad stacked on the semiconductor chip, an intermediate layer exhibiting a rectangular shape defined by the first edge and the second edge, and And a plurality of bumps arranged to sandwich the intermediate layer together with the semiconductor chip, wherein the first edge extends in a first direction intersecting the thickness direction of the semiconductor chip, and the second edge is And extending in a second direction intersecting with both the thickness direction and the first direction, any one of the plurality of bumps being a first bump electrically connected to the first electrode pad, One of the bumps is a second bump electrically connected to the first electrode pad, and the first bump is disposed at one end in the first direction and one end in the second direction among the plurality of bumps.
  • a semiconductor device is provided.
  • the semiconductor chip further includes a second electrode pad stacked on the semiconductor chip, and the semiconductor chip includes a wiring layer electrically connecting the first electrode pad and the second electrode pad, and the second bump includes the second bump. It is conducted with the first electrode pad via the two-electrode pad.
  • a coating film for exposing the first electrode pad and the second electrode pad is further provided, and the intermediate layer is laminated on the stress relieving layer laminated on the coating film and the stress relieving layer.
  • a coating film for exposing the first electrode pad and the second electrode pad is further provided, and the intermediate layer is laminated on the stress relieving layer laminated on the coating film and the stress relieving layer.
  • a rewiring layer the rewiring layer electrically connecting the first bump and the second bump.
  • the semiconductor device further comprises a covering film for exposing the first electrode pad, and the intermediate layer includes a stress relieving layer laminated on the covering film and a redistribution layer laminated on the stress relieving layer.
  • the rewiring layer electrically connects the first bump and the second bump.
  • the intermediate layer includes a first post extending in the thickness direction of the semiconductor chip, and a second post extending in the thickness direction of the semiconductor chip, and the first post includes the first post.
  • the second post is in contact with the bump, and the second post is in contact with the second bump.
  • the bonding area between the first post and the first bump is larger than the bonding area between the second post and the second bump.
  • the cross-sectional area of the first post due to the plane extending in the first direction and the second direction is larger than the cross-sectional area of the second post due to the plane extending in the first direction and the second direction.
  • the first post has a cylindrical shape extending in the thickness direction with a first dimension as a diameter
  • the second post has a cylindrical shape extending in the thickness direction with a second dimension smaller than the first dimension. It is.
  • the first dimension is 1.1 to 1.5 times the second dimension.
  • the intermediate layer includes a base having a main surface and a back surface, a main surface wiring layer formed on the main surface, and a back surface wiring layer formed on the back surface, and the back surface is the main
  • the semiconductor chip is mounted on the main surface, the back surface wiring layer is electrically connected to the main surface wiring layer, and the back surface wiring layer is formed of the first bump and the first surface. It touches any of 2 bumps.
  • the volumes of the first bump and the second bump are the same.
  • the plurality of bumps are 25 or more.
  • the first bump has a circular shape having a first length as a diameter in the thickness direction
  • the second bump has a second length smaller than the first length in the thickness direction. It is a circular shape.
  • the first length is 1.1 times to 1.5 times the second length.
  • the second bump is the closest to the first bump among the plurality of bumps.
  • the first bump and the second bump are both functional pins.
  • one of the plurality of bumps arranged in a square is the first bump.
  • FIG. 1 is a bottom view of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a side view of a semiconductor device according to a first embodiment of the present invention. It is principal part sectional drawing which follows the II-II line of FIG. 1A.
  • FIG. 3 is a cross-sectional view of essential parts along the line IIIA-IIIA of FIG. 2;
  • FIG. 3 is a cross-sectional view of main parts along the line IIIB-IIIB in FIG. 2;
  • FIG. 1 is a side view of a semiconductor device according to a first embodiment of the present invention mounted on a mounting substrate. It is principal part sectional drawing of the semiconductor device concerning 1st Embodiment of this invention mounted in the mounting substrate.
  • FIG. 1 is a bottom view of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a side view of a semiconductor device according to a first embodiment of the present invention. It is principal part sectional drawing which follows the II-I
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a main-portion cross-sectional view showing a process of manufacturing the semiconductor device according to the first embodiment of the present invention; It is principal part sectional drawing of the semiconductor device concerning 2nd Embodiment of this invention. It is principal part sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention. It is a bottom view of the semiconductor device concerning a 4th embodiment of the present invention. It is a side view (partially transparent) of the semiconductor device concerning a 4th embodiment of the present invention. It is principal part sectional drawing which follows the XX-XX line of FIG. 19A.
  • FIG. 21 is a cross-sectional view of main parts along the line XXI-XXI of FIG.
  • FIG. 1A is a bottom view of the semiconductor device according to the present embodiment
  • FIG. 1B is a side view of the semiconductor device according to the present embodiment
  • FIG. 2 is a cross-sectional view of essential parts along the line II-II in FIG. 1A
  • 3A is a cross-sectional view of main parts along the line IIIA-IIIA in FIG. 2
  • FIG. 3B is a cross-sectional view of main parts along the line IIIB-IIIB in FIG.
  • a semiconductor device A1 shown in these figures includes a semiconductor chip 1, a plurality of electrode pads 2, a covering film 3, an intermediate layer 4, a plurality of bumps 5, and a resin coat 85.
  • the semiconductor device A1 is a semiconductor device to which a CSP (Chip Size Package) technology is applied.
  • CSP Chip Size Package
  • the semiconductor chip 1 is an LSI chip and has a multilayer wiring structure.
  • the semiconductor chip 1 includes a semiconductor substrate 11, wiring layers 12 and 13, insulating layers 14 and 15, and a plurality of through vias 181, 182 and 183.
  • the semiconductor substrate 11 is mainly made of a semiconductor material such as silicon.
  • an integrated circuit such as a logic circuit is formed on the semiconductor substrate 11.
  • This integrated circuit has a plurality of terminals not shown.
  • a resin coat 85 made of insulating resin is laminated on the semiconductor substrate 11.
  • Wiring layers 12 and 13 are each made of, for example, a conductive material such as copper or aluminum. Each of the wiring layers 12 and 13 is formed in a designed pattern shape. The thickness (dimension in the direction z) of the wiring layers 12 and 13 is, for example, 0.5 to 3.0 ⁇ m, respectively.
  • the insulating layers 14 and 15 are each made of, for example, an insulating material such as silicon oxide or silicon nitride. The thickness (dimension in the direction z) of the insulating layers 14 and 15 is, for example, 1.0 to 3.0 ⁇ m, respectively.
  • the wiring layer 12 is stacked on the semiconductor substrate 11.
  • the insulating layer 14 is stacked on the semiconductor substrate 11 and covers the wiring layer 12.
  • the wiring layer 13 is stacked on the insulating layer 14.
  • the insulating layer 15 is stacked on the insulating layer 14.
  • the insulating layer 15 covers the wiring layer 13.
  • Each through via 181, 182, 183 is made of, for example, a conductive material such as copper or aluminum.
  • Each through via 181 penetrates the insulating layer 14.
  • Each through via 181 is in contact with the wiring layer 12 and the wiring layer 13. Thereby, the wiring layer 12 and the wiring layer 13 are conducted.
  • the through vias 182 and 183 penetrate the insulating layer 15.
  • Each through via 182 is in contact with the wiring layer 13 and a first electrode pad 21 described later. Thereby, the wiring layer 13 and the first electrode pad 21 are conducted.
  • Each through via 183 is in contact with the wiring layer 13 and a second electrode pad 22 described later. Thereby, the wiring layer 13 and the second electrode pad 22 are conducted.
  • Each electrode pad 2 (in the drawing, only the first electrode pad 21 and the second electrode pad 22 among the plurality of electrode pads 2 are shown) is formed on the semiconductor chip 1. Specifically, each electrode pad 2 is formed in the insulating layer 15. Each electrode pad 2 is electrically connected to the terminal of the above-described integrated circuit formed on the semiconductor substrate 11. The respective electrode pads 2 are arranged at mutually different positions in the z direction. Each electrode pad 2 is made of, for example, aluminum. The thickness (dimension in the direction z) of each electrode pad 2 is, for example, 0.5 to 3.0 ⁇ m.
  • the covering film 3 is laminated on the insulating layer 15.
  • the covering film 3 is made of, for example, an insulating material such as silicon oxide or silicon nitride.
  • the thickness (dimension in the direction z) of the covering film 3 is, for example, 0.5 to 2.0 ⁇ m.
  • the electrode pad 2 is exposed from the coating film 3.
  • the intermediate layer 4 is stacked on the semiconductor chip 1 with the covering film 3 interposed therebetween.
  • the middle layer 4 includes a stress relaxation layer 41, a resin layer 42, rewiring layers 43a, 43b, 43c, and a plurality of posts 44a, 44b.
  • the intermediate layer 4 in the direction z, has a rectangular shape defined by a first edge 49a extending in the direction x and a second edge 49b extending in the direction y.
  • the side surface of the intermediate layer 4 is formed flush with the side surface of the semiconductor chip 1.
  • the semiconductor device A1 has a substantially rectangular parallelepiped shape whose size in the direction z is equal to the size of the semiconductor chip 1.
  • the stress relaxation layer 41 is laminated on the covering film 3.
  • the stress relieving layer 41 is made of, for example, an insulating material such as polyimide.
  • the thickness (dimension in the direction z) of the stress relaxation layer 41 is, for example, 8 ⁇ m.
  • the resin layer 42 is laminated on the stress relieving layer 41.
  • the resin layer 42 is made of, for example, an insulating resin such as an epoxy resin.
  • the thickness (dimension in the direction z) of the resin layer 42 is, for example, 90 ⁇ m.
  • the redistribution layer 43a has a base layer 431a and a metal layer 432a.
  • the redistribution layer 43a has a portion overlapping the first bump 51 described later in the z direction.
  • a part of the underlayer 431 a penetrates the stress relieving layer 41.
  • a part of the base layer 431 a is stacked on the stress relaxation layer 41.
  • the underlayer 431 a is in contact with the first electrode pad 21.
  • the underlayer 431 a has a function of preventing the first electrode pad 21 from being corroded.
  • the base layer 431a is made of, for example, a metal such as titanium, nickel, titanium tungsten or the like.
  • the metal layer 432a is stacked on the base layer 431a.
  • the metal layer 432a is made of, for example, a metal such as copper.
  • the post 44a is provided upright on the redistribution layer 43a.
  • the post 44 a is for relieving stress applied to a first bump 51 described later.
  • the post 44a is in contact with the redistribution layer 43a.
  • the cross-sectional area S1 of the post 44a according to a plane extending in the directions x and y shown in FIG. 3A is, for example, 17671 to 196350 ⁇ m 2 .
  • the post 44a has a cylindrical shape extending in the direction z with the dimension L1 as a diameter.
  • the dimension L1 is, for example, 150 to 500 ⁇ m.
  • the post 44a may have a square pole shape.
  • the post 44a is made of, for example, copper.
  • the redistribution layer 43b includes a base layer 431b and a metal layer 432b.
  • the redistribution layer 43 b has a portion overlapping the second bump 52 described later in the z-direction.
  • the redistribution layer 43b is separated from the redistribution layer 43a.
  • a part of the underlayer 431 b penetrates the stress relieving layer 41.
  • a part of the base layer 431 b is stacked on the stress relaxation layer 41.
  • the underlayer 431 b is in contact with the second electrode pad 22.
  • the underlayer 431 b has a function of preventing the second electrode pad 22 from being corroded.
  • the underlayer 431 b is made of, for example, a metal such as titanium, nickel, titanium tungsten or the like.
  • the metal layer 432 b is stacked on the base layer 431 b.
  • the metal layer 432 b is made of, for example, a metal such as copper.
  • the post 44b is erected on the redistribution layer 43b.
  • the post 44 b is for relieving stress applied to a second bump 52 described later.
  • the post 44b is in contact with the redistribution layer 43b.
  • the cross-sectional area S2 of the post 44b in a plane extending in the directions x and y shown in FIG. 3A is preferably smaller than the cross-sectional area S1 of the post 44a (ie, the cross-sectional area S1 is larger than the cross-sectional area S2).
  • the cross-sectional area S2 is, for example, 7854 to 125664 ⁇ m 2 .
  • the post 44b has a cylindrical shape extending in the direction z with the dimension L2 as a diameter.
  • the post 44b may have a square pole shape. It is preferable that the dimension L1 be larger than the dimension L2.
  • the dimension L1 is preferably, for example, 1.1 to 1.5 times the dimension L2.
  • the dimension L2 is, for example, 100 to 400 ⁇ m.
  • the post 44b is made of, for example, copper.
  • the redistribution layer 43c includes a base layer 431c and a metal layer 432c. As shown in FIG. 2, the redistribution layer 43c is located between the redistribution layer 43a and the redistribution layer 43b. The redistribution layer 43c is insulated from both of the redistribution layers 43a and 43b. A part of the base layer 431c penetrates the stress relieving layer 41 outside the figure. As shown in FIG. 2, a part of the base layer 431 c is stacked on the stress relaxation layer 41. The base layer 431 c is in contact with the electrode pad 2 not shown.
  • the base layer 431c is made of, for example, a metal such as titanium, nickel, titanium tungsten or the like.
  • the metal layer 432c is stacked on the base layer 431c.
  • the metal layer 432c is made of, for example, a metal such as copper.
  • the plurality of bumps 5 are disposed on the opposite side to the side on which the semiconductor chip 1 is disposed with the intermediate layer 4 interposed therebetween. That is, the plurality of bumps 5 are disposed so as to sandwich the intermediate layer 4 together with the semiconductor chip 1.
  • the plurality of bumps 5 are arranged in the shape of a grid in the z-direction view.
  • Each bump 5 is substantially spherical, and is made of, for example, solder.
  • the volumes of the bumps 5 are identical to one another.
  • the volume of each bump 5 is, for example, 1407 ⁇ 10 3 to 10390 ⁇ 10 3 ⁇ m 3 .
  • the number of bumps 5 is preferably 5 or more in the direction x, 5 or more in the direction y, or 25 or more in total.
  • first bump 51 and a second bump 52 two of the plurality of bumps 5 are used as a first bump 51 and a second bump 52.
  • the first bumps 51 and the second bumps 52 are both functional pins.
  • the first bump 51 is disposed at one end in the direction x and at one end in the direction y.
  • the first bump 51 is joined to the post 44 a.
  • the bonding area S3 (see FIG. 3B) between the first bump 51 and the post 44a is, for example, 17671 to 196350 ⁇ m 2 .
  • the first bump 51 has a circular shape whose diameter is a length L3 (see FIG. 3B) in the z-direction.
  • the length L3 is, for example, 150 to 550 ⁇ m.
  • the first bump 51 is electrically connected to the wiring layer 13 via the post 44 a, the rewiring layer 43 a, the first electrode pad 21, and the through via 182.
  • the second bump 52 is bonded to the post 44 b.
  • the second bump 52 is adjacent to the first bump 51 among the plurality of bumps 5.
  • the second bumps 52 are not limited to those adjacent to the first bumps 51, and may be disposed substantially at the center of the plurality of bumps 5, for example. It is preferable that the above-mentioned bonding area S3 be larger than the bonding area S4 (see FIG. 3B) between the second bump 52 and the post 44b.
  • the bonding area S4 is, for example, 7854 to 125664 ⁇ m 2 .
  • the second bumps 52 have a circular shape whose diameter is L4 (see FIG. 3B) in the z direction. It is preferable that the length L3 be larger than the length L4.
  • the length L3 is 1.1 to 1.5 times the length L4.
  • the length L4 is, for example, 100 to 460 ⁇ m.
  • the second bump 52 is electrically connected to the wiring layer 13 via the post 44 b, the redistribution layer 43 b, the second electrode pad 22, and the through via 183.
  • the wiring layer 13 electrically connects the first bump 51 and the second bump 52.
  • one of the plurality of bumps 5 other than the first bump 51 and the second bump 52 is electrically connected to the redistribution layer 43c.
  • FIG. 4 and 5 show a state in which the semiconductor device A1 is mounted on the mounting substrate 8.
  • FIG. 8 When the semiconductor device A ⁇ b> 1 is mounted on the mounting substrate 8, each bump 5 is bonded to the mounting pad 81 on the mounting substrate 8.
  • the terminal (not shown) of the integrated circuit formed on the semiconductor substrate 11 is electrically connected to the mounting pad 81.
  • the mounting pad 811 to which the first bump 51 is bonded among the plurality of mounting pads 81 and the mounting pad 812 to which the second bump 52 is bonded among the plurality of mounting pads 81 are the wiring 82 on the mounting substrate 8 (see FIG. They are mutually connected via 4).
  • the wires 82 are conductive to each other.
  • all of the plurality of bumps 5 arranged in a square may have the same configuration as the first bump 51.
  • the first bump 51 is disposed at one end in the direction x and at one end in the direction y.
  • stress is likely to be applied to the first bump 51 among the plurality of bumps 5. Therefore, the first bump 51 is susceptible to fatigue failure.
  • the current path from the first electrode pad 21 to the mounting pad 811 via the first bump 51 is cut off.
  • the semiconductor device A1 the first electrode pad 21 is electrically connected to the mounting pad 811 via the second bump 52. Therefore, even if the path of the current from the first electrode pad 21 to the mounting pad 811 via the first bump 51 is interrupted, the first electrode pad 21 passes through the second bump 52 and the mounting pad 811. It can be conducted. Therefore, the semiconductor device A ⁇ b> 1 is suitable for suppressing an operation failure due to the interruption of the current path from the first electrode pad 21 to the mounting pad 811 via the first bump 51.
  • the bonding area S3 (see FIG. 3B) between the post 44a and the first bump 51 is larger than the bonding area S4 (see FIG. 3B) between the post 44b and the second bump 52.
  • Such a configuration is suitable for reducing the stress applied to the first bump 51. Therefore, the semiconductor device A1 is suitable for suppressing the fatigue failure of the first bump 51. Therefore, the semiconductor device A1 is further suitable for suppressing the above-mentioned malfunction.
  • the cross-sectional area S1 is larger than the cross-sectional area S2.
  • Such a configuration is also suitable for reducing the stress applied to the first bump 51.
  • the configuration is also suitable for reducing the resistance of the post 44a.
  • the semiconductor device A1 includes a second electrode pad 22 stacked on the semiconductor chip 1 and electrically connected to the second bump 52. Further, the wiring layer 13 electrically connects the first electrode pad 21 and the second electrode pad 22. In the semiconductor device A1, even if the rewiring layer 43a and the rewiring layer 43b are separated from each other, the first electrode pad 21 and the second bump 52 pass through the wiring layer 13 and the second electrode pad 22. It can be conducted. Therefore, even if it is necessary to form the rewiring layer 43c insulated with any of the rewiring layers 43a and 43b between the rewiring layer 43a and the rewiring layer 43b, the first electrode pad 21 can not be formed. The two bumps 52 can be conducted.
  • a substrate 7 in which a plurality of semiconductor chips are formed is prepared.
  • a plurality of electrode pads 2 (in the figure, a first electrode pad 21 and a second electrode pad 22 are shown) are formed on the substrate 7. Further, substantially the entire area of the surface of the substrate 7 is covered with a covering film 3 ′. The electrode pad 2 is exposed from the coating film 3 ′.
  • a stress relaxation layer 41 ' is formed on the covering film 3'. In the stress relieving layer 41 ′, an opening 411 for exposing the electrode pad 2 is formed.
  • the base layer 431 is formed.
  • the underlayer 431 covers the electrode pad 2 and the stress relieving layer 41 ′.
  • a metal layer 432 (including metal layers 432a, 432b, and 432c) is formed.
  • the metal layer 432 is formed by performing resist patterning (not shown) on the base layer 431 and then plating the base layer 431.
  • the posts 44 (the posts 44a and 44b are shown in the figure) are formed.
  • the post 44 is formed by patterning a dry film covering a part of the metal layer 432 and the stress relieving layer 41 ′ and then plating the metal layer 432.
  • the base layer 431 is etched.
  • the base layers 431a, 431b, and 431c are formed.
  • the groove 49 is formed by half cut dicing.
  • a resin layer 42 ' is formed.
  • the resin layer 42 ' is formed by printing.
  • the resin layer 42 ' is ground to expose the posts 44 from the resin layer 42'.
  • the lower surface of the semiconductor substrate 11 is ground (not shown in the description according to the present embodiment).
  • a resin coat 85 is formed on the back surface of the semiconductor substrate 11.
  • the bumps 5 are formed.
  • solder is printed on the posts 44 and then reflow is performed.
  • the semiconductor substrate 11, the resin layer 42 ′, and the like are collectively diced along a line 99 passing through the groove 49. Thereby, the semiconductor device A1 shown in FIG. 2 is manufactured.
  • FIG. 17 is a cross-sectional view of main parts of the semiconductor device according to the second embodiment of the present invention.
  • a semiconductor device A2 shown in the figure includes a semiconductor chip 1, a plurality of electrode pads 2, a covering film 3, an intermediate layer 4, a plurality of bumps 5, and a resin coat 85.
  • the semiconductor device A2 differs from the above-described semiconductor device A1 in that the semiconductor device A2 does not include the redistribution layers 43a, 43b, and 43c and includes the redistribution layer 43e.
  • the first electrode pad 21 and the second bump 52 are electrically connected not only to the wiring layer 13 but also to the rewiring layer 43e.
  • the configurations of the semiconductor chip 1, the plurality of electrode pads 2, the covering film 3, and the plurality of bumps 5 in the present embodiment are the same as the configurations in the above-described embodiment, and therefore the description thereof is omitted.
  • the intermediate layer 4 includes a stress relieving layer 41, a resin layer 42, a redistribution layer 43e, and posts 44a and 44b.
  • the stress relieving layer 41 and the resin layer 42 are the same as the configurations in the above-described embodiment, and therefore the description thereof is omitted.
  • the redistribution layer 43e has a base layer 431e and a metal layer 432e.
  • a part of the underlayer 431 e penetrates the stress relieving layer 41.
  • a part of the base layer 431 e is stacked on the stress relaxation layer 41.
  • the underlayer 431 e is in contact with both of the first electrode pads 21 and 22.
  • the underlayer 431 e has a function of preventing the first electrode pads 21 and 22 from being corroded.
  • the underlayer 431 e is made of, for example, a metal such as titanium, nickel, titanium tungsten or the like.
  • the metal layer 432 e is stacked on the base layer 431 e.
  • the metal layer 432 e is made of, for example, a metal such as copper.
  • both of the posts 44a and 44b are erected on the redistribution layer 43e.
  • the first bump 51 is disposed at one end in the direction x and at one end in the direction y.
  • stress is likely to be applied to the first bump 51 among the plurality of bumps 5. Therefore, the first bump 51 is susceptible to fatigue failure.
  • the current path from the first electrode pad 21 to the mounting pad 811 (not shown in this embodiment, see the first embodiment) via the first bump 51 is cut off.
  • the semiconductor device A2 the first electrode pad 21 is electrically connected to the mounting pad 811 via the second bump 52. Therefore, even if the path of the current from the first electrode pad 21 to the mounting pad 811 via the first bump 51 is interrupted, the first electrode pad 21 passes through the second bump 52 and the mounting pad 811. It can be conducted. Therefore, the semiconductor device A2 is suitable for suppressing the operation failure due to the interruption of the current path from the first electrode pad 21 to the mounting pad 811 via the first bump 51.
  • the bonding area S3 between the post 44a and the first bump 51 is larger than the bonding area S4 between the post 44b and the second bump 52.
  • Such a configuration is suitable for reducing the stress applied to the first bump 51. Therefore, the semiconductor device A2 is suitable for suppressing the fatigue failure of the first bump 51. Therefore, the semiconductor device A2 is further suitable for suppressing the above-mentioned malfunction.
  • the cross-sectional area S1 of the post 44a is larger than the cross-sectional area S2 of the post 44b.
  • Such a configuration is also suitable for reducing the stress applied to the first bump 51.
  • the configuration is also suitable for reducing the resistance of the post 44a.
  • FIG. 18 is a cross-sectional view of main parts of a semiconductor device according to a third embodiment of the present invention.
  • a semiconductor device A3 shown in the figure includes a semiconductor chip 1, a plurality of electrode pads 2, a covering film 3, an intermediate layer 4, a plurality of bumps 5, and a resin coat 85.
  • the semiconductor device A3 is different from the above-described semiconductor device A2 in that the first electrode pad 21 and the second bump 52 are not conducted by the wiring layer 13 but by only the rewiring layer 43e. .
  • the first electrode pad 21 is connected to the mounting pad 811 (not shown in the present embodiment, see the first embodiment) via the first bump 51. Even if the current path is interrupted, the first electrode pad 21 can be electrically connected to the mounting pad 811 via the second bump 52. Therefore, the semiconductor device A3 is suitable for suppressing the operation failure due to the interruption of the current path from the first electrode pad 21 to the mounting pad 811 via the first bump 51.
  • the bonding area S3 between the post 44a and the first bump 51 is larger than the bonding area S4 between the post 44b and the second bump 52.
  • Such a configuration is suitable for reducing the stress applied to the first bump 51. Therefore, the semiconductor device A3 is suitable for suppressing the fatigue failure of the first bump 51. Therefore, the semiconductor device A3 is further suitable for suppressing the above-mentioned malfunction.
  • the rewiring layer 43e does not connect the first electrode pad 21 and the first electrode pad 21.
  • the two bumps 52 can be conducted.
  • the design freedom of the shape pattern of the redistribution layer 43e is high. Therefore, a configuration in which the first electrode pad 21 and the second bump 52 are electrically connected can be easily obtained.
  • the cross-sectional area S1 of the post 44a is larger than the cross-sectional area S2 of the post 44b.
  • Such a configuration is also suitable for reducing the stress applied to the first bump 51.
  • the configuration is also suitable for reducing the resistance of the post 44a.
  • FIG. 19A is a bottom view of the semiconductor device according to the present embodiment
  • FIG. 19B is a side view (partially transparent) of the semiconductor device according to the present embodiment
  • FIG. 20 is a cross-sectional view of essential parts along the line XX-XX in FIG. 19A
  • FIG. 21 is a cross-sectional view of essential parts along the line XXI-XXI in FIG.
  • a semiconductor device A4 shown in these figures includes a semiconductor chip 1, a plurality of electrode pads 2, an intermediate layer 4, a plurality of bumps 5, a plurality of wires 87, and a sealing resin 88.
  • the semiconductor device A4 is a BGA (Ball Grid Array) type semiconductor device.
  • the intermediate layer 4 is a wiring board.
  • the intermediate layer 4 at least includes a base 71, a main surface wiring layer 72, a back surface wiring layer 73, and a through hole electrode 74.
  • the intermediate layer 4 mounts the semiconductor chip 1.
  • the intermediate layer 4 in the direction z, has a rectangular shape defined by a first edge 49a extending in the direction x and a second edge 49b extending in the direction y.
  • the substrate 71 is made of, for example, an epoxy resin.
  • the base 71 has a main surface 711 and a back surface 712 facing away from the main surface 711.
  • the main surface interconnection layer 72, the back surface interconnection layer 73, and the through hole electrode 74 are made of, for example, copper.
  • the main surface wiring layer 72 is formed on the main surface 711.
  • the back surface wiring layer 73 is formed on the back surface 712.
  • the through hole electrode 74 penetrates the base 71 from the main surface 711 to the back surface 712. Through-hole electrode 74 is in contact with both main surface wiring layer 72 and back surface wiring layer 73. Thereby, the main surface wiring layer 72 and the back surface wiring layer 73 are conducted to each other.
  • the plurality of wires 87 are made of, for example, copper, aluminum or gold. As shown in FIG. 20, one of the plurality of wires 87 is in contact with the first electrode pad 21 and the main surface wiring layer 72. Thereby, the first electrode pad 21 and the main surface wiring layer 72 are electrically connected.
  • the sealing resin 88 covers the semiconductor chip 1, the main surface wiring layer 72, the wires 87 and the like.
  • the sealing resin 88 is made of, for example, an epoxy resin.
  • the plurality of bumps 5 is disposed on the opposite side of the intermediate layer 4 from the side on which the semiconductor chip 1 is disposed. That is, the plurality of bumps 5 are disposed so as to sandwich the intermediate layer 4 together with the semiconductor chip 1. As shown in FIG. 19A, in the present embodiment, the plurality of bumps 5 are arranged in a grid pattern in the z-direction. The arrangement of the bumps 5 is the same as that of the above-described embodiment, and thus the description thereof is omitted.
  • two of the plurality of bumps 5 are the first bump 53 and the second bump 54.
  • the first bump 53 is disposed at one end in the direction x and at one end in the direction y.
  • the first bump 53 is bonded to the back surface wiring layer 73.
  • the bonding area S5 (see FIG. 21) of the first bump 53 and the back surface wiring layer 73 is, for example, 17671 to 196350 ⁇ m 2 .
  • the first bump 53 has a circular shape whose diameter is a length L5 (see FIG. 21) in the z-direction.
  • the length L5 is, for example, 150 to 500 ⁇ m.
  • the first bump 53 is electrically connected to the first electrode pad 21 via the back surface wiring layer 73, the through hole electrode 74, the main surface wiring layer 72, and the wire 87.
  • the second bump 54 is bonded to the back surface wiring layer 73.
  • the second bump 54 is adjacent to the first bump 53 among the plurality of bumps 5.
  • the second bump 54 is not limited to one adjacent to the first bump 53, and may be disposed substantially at the center of the plurality of bumps 5, for example.
  • the bonding area S6 (see FIG. 21) of the second bump 54 and the back surface wiring layer 73 is, for example, 7854 to 125664 ⁇ m 2 .
  • the bonding area S5 is preferably larger than the bonding area S6.
  • the bonding area S5 is preferably 1.1 to 1.5 times the bonding area S6.
  • the second bump 54 has a circular shape whose diameter is a length L6 (see FIG. 21) in the z-direction.
  • the length L5 be larger than the length L6.
  • the length L6 is preferably 1.1 to 1.5 times the length L5.
  • the length L6 is, for example, 100 to 400 ⁇ m.
  • the second bump 54 is electrically connected to the first electrode pad 21 via the back surface wiring layer 73, the through hole electrode 74, the main surface wiring layer 72, and the wire 87.
  • the back surface wiring layer 73 electrically connects the first bump 53 and the second bump 54.
  • FIG. 22 and FIG. 23 are diagrams showing a state in which the semiconductor device A4 is mounted on the mounting substrate 8.
  • each bump 5 is bonded to the mounting pad 81 on the mounting substrate 8.
  • the terminal (not shown) of the integrated circuit formed on the semiconductor substrate 11 is electrically connected to the mounting pad 81.
  • the mounting pad 811 to which the first bump 53 is bonded among the plurality of mounting pads 81 and the mounting pad 812 to which the second bump 54 is bonded among the plurality of mounting pads 81 are the wiring 82 on the mounting substrate 8 (see FIG. They are mutually connected via 22). Therefore, main surface wiring layer 72, back surface wiring layer 73, through hole electrode 74, wire 87 shown in FIG. 23, first electrode pad 21, first bump 53, second bump 54, mounting pad 811, 812 and wiring 82 are in conduction with each other.
  • all of the plurality of bumps 5 arranged in a square may have the same configuration as the first bump 53.
  • the first bump 53 is disposed at one end in the direction x and at one end in the direction y.
  • stress is likely to be applied to the first bump 53 among the plurality of bumps 5. Therefore, the first bump 53 is prone to fatigue failure.
  • the first bump 53 is subject to fatigue failure, the current path from the first electrode pad 21 to the mounting pad 811 via the first bump 53 is cut off.
  • the semiconductor device A4 the first electrode pad 21 is electrically connected to the mounting pad 811 via the second bump 54. Therefore, even if the path of the current from the first electrode pad 21 to the mounting pad 811 via the first bump 53 is interrupted, the first electrode pad 21 and the mounting pad 811 via the second bump 54 It can be conducted. Therefore, the semiconductor device A4 is suitable for suppressing the operation failure due to the interruption of the current path from the first electrode pad 21 to the mounting pad 811 via the first bump 53.
  • the junction area S5 is larger than the junction area S6.
  • the semiconductor device A4 is suitable for suppressing the fatigue failure of the first bump 53. Therefore, the semiconductor device A4 is further suitable for suppressing the above-mentioned malfunction.
  • the semiconductor chip 1 is disposed on the main surface 711 of the base 71.
  • the wire 87 needs to be connected to the main surface wiring layer 72. Therefore, the degree of freedom of the shape of main surface wiring layer 72 is relatively low.
  • the bumps 5 are only formed on the back surface wiring layer 73. Therefore, the shape of the back surface wiring layer 73 can be determined relatively freely. Therefore, according to the semiconductor device A4, the first bumps 53 and the second bumps 54 can be conducted relatively easily.
  • FIG. 24 is a cross-sectional view of essential parts showing a semiconductor device according to a fifth embodiment of the present invention.
  • a semiconductor device A5 shown in the figure is different from the above-described semiconductor device A4 in that the main surface wiring layer 72 electrically connects the first bump 53 and the second bump 54. With such a configuration as well, the above-mentioned malfunction can be suppressed for the same reason as described for the semiconductor device A4.
  • the dimension L1 is preferably larger than the dimension L2, the dimension L1 may be equal to or less than the dimension L2 as long as the first bump 51 and the second bump 52 are electrically connected to the first electrode pad 21.
  • the length L3 may be equal to or less than the length L4.
  • the length L5 may be equal to or less than the length L6.
  • the area S1 may be equal to or less than the area S2.
  • the area S3 may be equal to or less than the area S4.
  • the area S5 may be equal to or less than the area S6.
  • the plurality of bumps 5 there may be a plurality of bumps having the same function as the second bump 52 or the second bump 54.

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Abstract

【課題】　動作不良を抑制するのに適する半導体装置を提供すること。 【解決手段】　半導体チップ１と、半導体チップ１に積層された第１電極パッド２１と、第１の縁４９ａと、第２の縁とに規定された矩形状を呈する中間層４と、半導体チップ１とともに中間層４を挟むように配置された複数のバンプ５と、を備え、第１の縁４９ａは、方向ｘに延び、上記第２の縁は、方向ｙに延び、複数のバンプ５のいずれか一つは、第１電極パッド２１に導通する第１バンプ５１であり、複数のバンプ５のいずれか一つは、第１電極パッド２１に導通する第２バンプ５２であり、上記第１バンプ５１は、複数のバンプ５のうち、方向ｘの一端且つ方向ｙの一端に配置されたものである。

Description

半導体装置
　本発明は、半導体装置に関する。
　従来から半導体チップを備える半導体装置が知られている（たとえば、特許文献１参照）。ＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ）やＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）等のボールグリッドタイプの半導体装置には、複数のバンプが形成されている。当該半導体装置は、複数のバンプを実装基板に形成された実装パッドに接合することにより、実装基板に実装（実装基板に対する電気的および機械的な接続）される。
　このような半導体装置が実装基板に実装された際には、各バンプには応力が集中することがある。バンプに応力が集中すると疲労破壊を起こし、半導体チップと実装基板における実装パッドとの導通が確保できなくなりうる。このようなことでは、半導体装置の動作不良を招来するおそれがあり、好ましくない。
特開２００８－１５９９４９号公報
　本発明は、上記した事情のもとで考え出されたものであって、動作不良を抑制するのに適する半導体装置を提供することをその課題とする。
　本発明の第１の側面によると、半導体チップと、上記半導体チップに積層された第１電極パッドと、第１の縁と第２の縁とに規定された矩形状を呈する中間層と、上記半導体チップとともに上記中間層を挟むように配置された複数のバンプと、を備え、上記第１の縁は、上記半導体チップの厚さ方向に交差する第１方向に延び、上記第２の縁は、上記厚さ方向および上記第１方向のいずれにも交差する第２方向に延び、上記複数のバンプのいずれか一つは、上記第１電極パッドに導通する第１バンプであり、上記複数のバンプのいずれか一つは、上記第１電極パッドに導通する第２バンプであり、上記第１バンプは、上記複数のバンプのうち、上記第１方向の一端且つ上記第２方向の一端に配置されたものである、半導体装置が提供される。
　好ましくは、上記半導体チップに積層された第２電極パッドを更に備え、上記半導体チップは、上記第１電極パッドおよび上記第２電極パッドを導通させる配線層を含み、上記第２バンプは、上記第２電極パッドを経由して上記第１電極パッドと導通している。
　好ましくは、上記第１電極パッドおよび上記第２電極パッドを露出させる被覆膜を更に備え、上記中間層は、上記被覆膜に積層された応力緩和層と、上記応力緩和層に積層された第１再配線層と、上記応力緩和層に積層された第２再配線層と、を含み、上記第１再配線層は、上記厚さ方向視において上記第１バンプと重なる部位を有し、上記第２再配線層は、上記厚さ方向視において上記第２バンプと重なる部位を有し、上記第１再配線層と上記第２再配線層とは互いに離間している。
　好ましくは、上記第１電極パッドおよび上記第２電極パッドを露出させる被覆膜を更に備え、上記中間層は、上記被覆膜に積層された応力緩和層と、上記応力緩和層に積層された再配線層と、を含み、上記再配線層は、上記第１バンプおよび上記第２バンプを導通させている。
　好ましくは、上記第１電極パッドを露出させる被覆膜を更に備え、上記中間層は、上記被覆膜に積層された応力緩和層と、上記応力緩和層に積層された再配線層と、を含み、上記再配線層は、上記第１バンプおよび上記第２バンプを導通させている。
　好ましくは、上記中間層は、上記半導体チップの厚さ方向に延びる第１ポストと、上記半導体チップの厚さ方向に向かって延びる第２ポストと、を含み、上記第１ポストは、上記第１バンプに接し、上記第２ポストは、上記第２バンプに接する。
　好ましくは、上記第１ポストと上記第１バンプとの接合面積は、上記第２ポストと上記第２バンプとの接合面積より大きい。
　好ましくは、上記第１方向および上記第２方向に広がる平面による上記第１ポストの断面積は、上記第１方向および上記第２方向に広がる平面による上記第２ポストの断面積より大きい。
　好ましくは、上記第１ポストは第１寸法を直径として上記厚さ方向に延びる円柱状であり、上記第２ポストは上記第１寸法より小さい第２寸法を直径として上記厚さ方向に延びる円柱状である。
　好ましくは、上記第１寸法は、上記第２寸法の１．１倍～１．５倍である。
　好ましくは、上記中間層は、主面および裏面を有する基材と、上記主面に形成された主面配線層と、上記裏面に形成された裏面配線層と、を含み、上記裏面は上記主面の反対側を向き、上記主面には、上記半導体チップが搭載されており、上記裏面配線層は、上記主面配線層と導通し、上記裏面配線層は、上記第１バンプおよび上記第２バンプのいずれにも接する。
　好ましくは、上記第１バンプおよび上記第２バンプの体積はいずれも同一である。
　好ましくは、上記複数のバンプは、２５個以上である。
　好ましくは、上記厚さ方向視において上記第１バンプは第１長さを直径とする円形状であり、上記厚さ方向視において上記第２バンプは上記第１長さより小さい第２長さを直径とする円形状である。
　好ましくは、上記第１長さは、上記第２長さの１．１倍～１．５倍である。
　好ましくは、上記第２バンプは、上記複数のバンプのうち上記第１バンプに最も隣接しているものである。
　好ましくは、上記第１バンプおよび上記第２バンプはいずれも機能ピンである。
　好ましくは、上記複数のバンプのうち四角に配置されたものは上記第１バンプである。
　本発明のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。
本発明の第１実施形態にかかる半導体装置の底面図である。 本発明の第１実施形態にかかる半導体装置の側面図である。 図１ＡのＩＩ－ＩＩ線に沿う要部断面図である。 図２のＩＩＩＡ－ＩＩＩＡ線に沿う要部断面図である。 図２のＩＩＩＢ－ＩＩＩＢ線に沿う要部断面図である。 実装基板に実装された、本発明の第１実施形態にかかる半導体装置の側面図である。 実装基板に実装された、本発明の第１実施形態にかかる半導体装置の要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第１実施形態にかかる半導体装置の製造工程の一工程を示す要部断面図である。 本発明の第２実施形態にかかる半導体装置の要部断面図である。 本発明の第３実施形態にかかる半導体装置の要部断面図である。 本発明の第４実施形態にかかる半導体装置の底面図である。 本発明の第４実施形態にかかる半導体装置の側面図（一部透視化）である。 図１９ＡのＸＸ－ＸＸ線に沿う要部断面図である。 図２０のＸＸＩ－ＸＸＩ線に沿う要部断面図である。 実装基板に実装された、本発明の第４実施形態にかかる半導体装置の側面図である。 実装基板に実装された、本発明の第４実施形態にかかる半導体装置の要部断面図である。 本発明の第５実施形態にかかる半導体装置の要部断面図である。

　以下、本発明の実施の形態につき、図面を参照して具体的に説明する。
　図１Ａ～図１６を用いて本発明の第１実施形態について説明する。図１Ａは、本実施形態にかかる半導体装置の底面図であり、図１Ｂは、本実施形態にかかる半導体装置の側面図である。図２は、図１ＡのＩＩ－ＩＩ線に沿う要部断面図である。図３Ａは、図２のＩＩＩＡ－ＩＩＩＡ線に沿う要部断面図であり、図３Ｂは、図２のＩＩＩＢ－ＩＩＩＢ線に沿う要部断面図である。
　これらの図に示す半導体装置Ａ１は、半導体チップ１と、複数の電極パッド２と、被覆膜３と、中間層４と、複数のバンプ５と、樹脂コート８５とを備える。半導体装置Ａ１は、ＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ）技術が適用された半導体装置である。
　半導体チップ１は、ＬＳＩチップであり、多層配線構造を有する。半導体チップ１は、半導体基板１１と、配線層１２，１３と、絶縁層１４，１５と、複数の貫通ビア１８１，１８２，１８３とを備える。
　半導体基板１１は、主として、シリコンなどの半導体材料よりなる。半導体基板１１には、たとえば、ロジック回路などの集積回路が形成されている。この集積回路は、図示しない複数の端子を有する。半導体基板１１には、絶縁性の樹脂よりなる樹脂コート８５が積層されている。
　配線層１２，１３はそれぞれ、たとえば、銅、アルミニウムなどの導電性材料よりなる。配線層１２，１３はそれぞれ、設計されたパターン形状に形成されている。配線層１２，１３の厚さ（方向ｚにおける寸法）は、それぞれ、たとえば、０．５～３．０μｍである。絶縁層１４，１５はそれぞれ、たとえば、酸化シリコン、窒化シリコンなどの絶縁材料よりなる。絶縁層１４，１５の厚さ（方向ｚにおける寸法）は、それぞれ、たとえば、１．０～３．０μｍである。
　配線層１２は、半導体基板１１に積層されている。絶縁層１４は、半導体基板１１に積層され、且つ、配線層１２を被覆している。配線層１３は、絶縁層１４に積層されている。絶縁層１５は、絶縁層１４に積層されている。絶縁層１５は、配線層１３を被覆している。
　各貫通ビア１８１，１８２，１８３は、たとえば、銅、アルミニウムなどの導電性材料よりなる。各貫通ビア１８１は、絶縁層１４を貫通している。各貫通ビア１８１は、配線層１２および配線層１３に接している。これにより、配線層１２および配線層１３が導通している。各貫通ビア１８２，１８３は、絶縁層１５を貫通している。各貫通ビア１８２は、配線層１３および後述の第１電極パッド２１に接している。これにより、配線層１３および第１電極パッド２１が導通している。各貫通ビア１８３は、配線層１３および後述の第２電極パッド２２に接している。これにより、配線層１３および第２電極パッド２２が導通している。
　各電極パッド２（図では、複数の電極パッド２のうち第１電極パッド２１、第２電極パッド２２のみを示す）は、半導体チップ１に形成されている。具体的には各電極パッド２は、絶縁層１５に形成されている。各電極パッド２は、半導体基板１１に形成された上述の集積回路の端子と導通している。各電極パッド２は方向ｚ視において、互いに異なる位置に配置されている。各電極パッド２は、たとえば、アルミニウムよりなる。各電極パッド２の厚さ（方向ｚにおける寸法）は、たとえば、０．５～３．０μｍである。
　被覆膜３は、絶縁層１５に積層されている。被覆膜３は、たとえば、酸化シリコン、窒化シリコンなどの絶縁材料よりなる。被覆膜３の厚さ（方向ｚにおける寸法）は、たとえば、０．５～２．０μｍである。被服膜３から電極パッド２が露出している。
　中間層４は、被覆膜３を挟んで、半導体チップ１に積層されている。中間層４は、応力緩和層４１と、樹脂層４２と、再配線層４３ａ，４３ｂ，４３ｃと、複数のポスト４４ａ，４４ｂとを含む。図１Ａに示すように、中間層４は、方向ｚ視において、方向ｘに延びる第１の縁４９ａと、方向ｙに延びる第２の縁４９ｂとにより規定される矩形状を呈する。中間層４の側面は、半導体チップ１の側面と面一に形成されている。これにより、半導体装置Ａ１は、方向ｚ視におけるサイズが半導体チップ１のサイズと等しい略直方体形状を呈している。
　応力緩和層４１は、被覆膜３に積層されている。応力緩和層４１は、たとえば、ポリイミドなどの絶縁材料よりなる。応力緩和層４１の厚さ（方向ｚにおける寸法）は、たとえば、８μｍである。応力緩和層４１は、半導体装置Ａ１に応力が加わったとき、その応力を吸収して緩和するために設けられている。
　樹脂層４２は、応力緩和層４１に積層されている。樹脂層４２は、たとえば、エポキシ樹脂などの絶縁性樹脂よりなる。樹脂層４２の厚さ（方向ｚにおける寸法）は、たとえば、９０μｍである。
　再配線層４３ａは、下地層４３１ａと、金属層４３２ａとを有する。再配線層４３ａは、方向ｚ視において、後述の第１バンプ５１と重なる部位を有する。下地層４３１ａの一部は応力緩和層４１を貫通している。また、下地層４３１ａの一部は、応力緩和層４１に積層されている。下地層４３１ａは、第１電極パッド２１に接する。下地層４３１ａは、第１電極パッド２１が腐食するのを防止する機能を担う。下地層４３１ａは、たとえば、チタン、ニッケル、チタンタングステンなどの金属よりなる。金属層４３２ａは、下地層４３１ａに積層されている。金属層４３２ａは、たとえば、銅などの金属よりなる。
　ポスト４４ａは、再配線層４３ａに立設されている。ポスト４４ａは、後述の第１バンプ５１にかかる応力を緩和するためのものである。ポスト４４ａは、再配線層４３ａに接する。図３Ａに示す、方向ｘおよび方向ｙに広がる平面によるポスト４４ａの断面積Ｓ１は、たとえば、１７６７１～１９６３５０μｍ2である。本実施形態では、ポスト４４ａは、寸法Ｌ１を直径として方向ｚに延びる円柱状である。寸法Ｌ１は、たとえば、１５０～５００μｍである。ポスト４４ａは、四角柱状であってもかまわない。ポスト４４ａは、たとえば、銅よりなる。
　再配線層４３ｂは、再配線層４３ａと同様に、下地層４３１ｂと、金属層４３２ｂとを有する。再配線層４３ｂは、方向ｚ視において、後述の第２バンプ５２と重なる部位を有する。再配線層４３ｂは、再配線層４３ａと離間している。下地層４３１ｂの一部は応力緩和層４１を貫通している。また、下地層４３１ｂの一部は、応力緩和層４１に積層されている。下地層４３１ｂは、第２電極パッド２２に接する。下地層４３１ｂは、第２電極パッド２２が腐食するのを防止する機能を担う。下地層４３１ｂは、たとえば、チタン、ニッケル、チタンタングステンなどの金属よりなる。金属層４３２ｂは、下地層４３１ｂに積層されている。金属層４３２ｂは、たとえば、銅などの金属よりなる。
　ポスト４４ｂは、再配線層４３ｂに立設されている。ポスト４４ｂは、後述の第２バンプ５２にかかる応力を緩和するためのものである。ポスト４４ｂは、再配線層４３ｂに接する。図３Ａに示す、方向ｘおよび方向ｙに広がる平面によるポスト４４ｂの断面積Ｓ２は、ポスト４４ａの断面積Ｓ１より小さいこと（すなわち、断面積Ｓ１が断面積Ｓ２より大きいこと）が好ましい。断面積Ｓ２は、たとえば、７８５４～１２５６６４μｍ2である。本実施形態では、ポスト４４ｂは、寸法Ｌ２を直径として方向ｚに延びる円柱状である。ポスト４４ｂは、四角柱状であってもかまわない。寸法Ｌ２よりも寸法Ｌ１が大きい方が好ましい。寸法Ｌ１は、たとえば、寸法Ｌ２の１．１～１．５倍であることが好ましい。寸法Ｌ２は、たとえば、１００～４００μｍである。ポスト４４ｂは、たとえば、銅よりなる。
　再配線層４３ｃは、再配線層４３ａ，４３ｂと同様に、下地層４３１ｃと、金属層４３２ｃとを有する。図２に示すように、再配線層４３ｃは、再配線層４３ａと再配線層４３ｂとの間に位置する。再配線層４３ｃは、再配線層４３ａ，４３ｂのいずれとも絶縁されている。下地層４３１ｃの一部は、図外において、応力緩和層４１を貫通している。図２に示すように、下地層４３１ｃの一部は、応力緩和層４１に積層されている。下地層４３１ｃは、図外の電極パッド２に接する。下地層４３１ｃは、たとえば、チタン、ニッケル、チタンタングステンなどの金属よりなる。金属層４３２ｃは、下地層４３１ｃに積層されている。金属層４３２ｃは、たとえば、銅などの金属よりなる。
　図２に示すように、複数のバンプ５は、中間層４を挟んで半導体チップ１が配置された側と反対側に配置されている。すなわち、複数のバンプ５は、半導体チップ１とともに中間層４を挟むように配置されている。図１Ａに示すように、本実施形態では方向ｚ視において、複数のバンプ５は、碁盤の目状に配置されている。各バンプ５は、略球状であり、たとえば、ハンダよりなる。本実施形態では、各バンプ５の体積は、互いに同一である。各バンプ５の体積は、たとえば、１４０７×１０3～１０３９０×１０3μｍ3である。バンプ５の個数は、方向ｘに５個以上、方向ｙに５個以上、全体で２５個以上であることが好ましい。
　図１Ａ～図３Ｂに示すように、複数のバンプ５のうち２つを、第１バンプ５１、第２バンプ５２としている。第１バンプ５１および第２バンプ５２はいずれも機能ピンである。図１Ａに示すように、第１バンプ５１は、方向ｘの一端且つ方向ｙの一端に配置されている。図２に示すように、第１バンプ５１は、ポスト４４ａに接合されている。第１バンプ５１とポスト４４ａとの接合面積Ｓ３（図３Ｂ参照）は、たとえば、１７６７１～１９６３５０μｍ2である。第１バンプ５１は、方向ｚ視において、長さＬ３（図３Ｂ参照）を直径とする円形状である。長さＬ３は、たとえば、１５０～５５０μｍである。第１バンプ５１は、ポスト４４ａ、再配線層４３ａ、第１電極パッド２１、および貫通ビア１８２を経由して、配線層１３と導通している。
　第２バンプ５２は、ポスト４４ｂに接合されている。本実施形態では、第２バンプ５２は、複数のバンプ５のうち第１バンプ５１に隣接しているものである。第２バンプ５２は、第１バンプ５１に隣接しているものに限られず、たとえば、複数のバンプ５のうち略中央に配置されたものであってもよい。第２バンプ５２とポスト４４ｂとの接合面積Ｓ４（図３Ｂ参照）よりも、上述の接合面積Ｓ３が大きい方が好ましい。接合面積Ｓ４は、たとえば、７８５４～１２５６６４μｍ2である。第２バンプ５２は、方向ｚ視において、長さＬ４（図３Ｂ参照）を直径とする円形状である。長さＬ４よりも長さＬ３が大きい方が好ましい。好ましくは、長さＬ３は、長さＬ４の１．１倍～１．５倍である。長さＬ４は、たとえば、１００～４６０μｍである。第２バンプ５２は、ポスト４４ｂ、再配線層４３ｂ、第２電極パッド２２、および貫通ビア１８３を経由して、配線層１３と導通している。本実施形態においては、第１バンプ５１と第２バンプ５２とを、配線層１３が導通させている。
　図には示していないが、複数のバンプ５のうち第１バンプ５１、第２バンプ５２以外のいずれかは、再配線層４３ｃと導通している。
　図４、図５は、半導体装置Ａ１を実装基板８に実装した状態を示す。半導体装置Ａ１が実装基板８に実装されるとき、各バンプ５が実装基板８における実装パッド８１に接合される。これにより、半導体基板１１に形成された集積回路の端子（図示略）が実装パッド８１と導通する。複数の実装パッド８１のうち第１バンプ５１が接合される実装パッド８１１と、複数の実装パッド８１のうち第２バンプ５２が接合される実装パッド８１２とは、実装基板８上における配線８２（図４では略）を介して、互いに導通している。そのため、配線層１２，１３、貫通ビア１８１～１８３、第１電極パッド２１，２２、再配線層４３ａ，４３ｂ、ポスト４４ａ，４４ｂ、第１バンプ５１、第２バンプ５２、実装パッド８１１，８１２、および、配線８２は、互いに導通している。
　なお、複数のバンプ５のうち四角に配置されたもの全てを、第１バンプ５１と同様の構成としてもよい。
　次に、半導体装置Ａ１の作用効果について説明する。
　半導体装置Ａ１においては、図１Ａに示したように、第１バンプ５１は方向ｘの一端且つ方向ｙの一端に配置されている。半導体装置Ａ１が実装基板８に実装された状態では、複数のバンプ５のうち第１バンプ５１に応力がかかりやすい。そのため、第１バンプ５１が疲労破壊しやすい。第１バンプ５１が疲労破壊すると、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１に至る電流の経路が遮断される。
　半導体装置Ａ１においては、第１電極パッド２１は、第２バンプ５２を経由して、実装パッド８１１と導通している。そのため、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１に至る電流の経路が遮断されても、第１電極パッド２１は、第２バンプ５２を経由して、実装パッド８１１と導通しうる。そのため、半導体装置Ａ１は、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１に至る電流の経路が遮断することに起因する動作不良を、抑制するのに適する。
　半導体装置Ａ１においては、ポスト４４ａと第１バンプ５１との接合面積Ｓ３（図３Ｂ参照）は、ポスト４４ｂと第２バンプ５２との接合面積Ｓ４（図３Ｂ参照）より大きい。このような構成は、第１バンプ５１にかかる応力を小さくするのに適する。そのため、半導体装置Ａ１は、第１バンプ５１の疲労破壊を抑制するのに適する。したがって、半導体装置Ａ１は、上述の動作不良を抑制するのに更に適する。
　半導体装置Ａ１においては、図３Ａに示したように、断面積Ｓ１は、断面積Ｓ２より大きい。このような構成も第１バンプ５１にかかる応力を小さくするのに適する。さらに、当該構成はポスト４４ａの抵抗を小さくするのにも好適である。
　半導体装置Ａ１は、半導体チップ１に積層され且つ第２バンプ５２に導通する第２電極パッド２２を備える。また、第１電極パッド２１と第２電極パッド２２とを配線層１３が導通させている。半導体装置Ａ１においては、再配線層４３ａと再配線層４３ｂとが互いに離間していても、第１電極パッド２１は、配線層１３および第２電極パッド２２を経由して、第２バンプ５２と導通しうる。そのため、再配線層４３ａおよび再配線層４３ｂとの間に再配線層４３ａ，４３ｂのいずれとも絶縁された再配線層４３ｃを形成しなければならない場合であっても、第１電極パッド２１を第２バンプ５２と導通させることができる。
　次に、図６～図１６を用いて、半導体装置Ａ１の製造方法の一例について簡単に説明する。
　まず、図６に示すように、複数の半導体チップが作りこまれた基板７を用意する。基板７には、複数の電極パッド２（図では第１電極パッド２１、第２電極パッド２２を示す）が形成されている。また、基板７の表面の略全域は被覆膜３’により覆われている。被覆膜３’から電極パッド２が露出している。次に、同図に示すように、被覆膜３’上に応力緩和層４１’を形成する。応力緩和層４１’には、電極パッド２を露出させる開口４１１が形成されている。
　次に、図７に示すように、下地層４３１を形成する。下地層４３１は、電極パッド２および応力緩和層４１’を被覆している。次に、図８に示すように、金属層４３２（金属層４３２ａ，４３２ｂ，４３２ｃを含む）を形成する。金属層４３２を形成するには、下地層４３１上に図示しないレジストパターニングを行った後に、下地層４３１上にメッキを施すことにより行う。
　次に、図９に示すように、ポスト４４（図ではポスト４４ａ，４４ｂを示す）を形成する。ポスト４４を形成するには、金属層４３２の一部と応力緩和層４１’とを覆うドライフィルムをパターニングした後に、金属層４３２上にメッキを施すことにより行う。
　次に、図１０に示すように、下地層４３１をエッチングする。これにより、下地層４３１ａ，４３１ｂ，４３１ｃが形成される。次に、図１１に示すように、ハーフカットダイシングすることにより溝４９を形成する。次に、図１２に示すように、樹脂層４２’を形成する。樹脂層４２’の形成は印刷により行う。次に、図１３に示すように、樹脂層４２’を研削し、ポスト４４を樹脂層４２’から露出させる。次に、半導体基板１１の図の下面を研削する（本実施形態にかかる説明では図示せず）。次に、図１４に示すように、半導体基板１１の裏面に樹脂コート８５を形成する。次に、図１５に示すように、バンプ５を形成する。バンプ５を形成するには、ポスト４４にハンダを印刷した後に、リフローを施すことにより行う。次に、図１６に示すように、溝４９を通る線９９に沿って、半導体基板１１や樹脂層４２’等を一括してダイシングする。これにより、図２に示した半導体装置Ａ１が製造される。
　図１７～図２３は、本発明の他の実施形態を示している。なお、これらの図において、上記実施形態と同一または類似の要素には、上記実施形態と同一の符号を付している。
　図１７は、本発明の第２実施形態にかかる半導体装置の要部断面図である。同図に示す半導体装置Ａ２は、半導体チップ１と、複数の電極パッド２と、被覆膜３と、中間層４と、複数のバンプ５と、樹脂コート８５とを備える。半導体装置Ａ２は、再配線層４３ａ，４３ｂ，４３ｃを備えておらず再配線層４３ｅを備えている点において、上述の半導体装置Ａ１と異なる。半導体装置Ａ２では、第１電極パッド２１と第２バンプ５２とを、配線層１３のみならず再配線層４３ｅが導通させている。本実施形態における半導体チップ１、複数の電極パッド２、被覆膜３、および、複数のバンプ５の各構成は、上述の実施形態における構成と同様であるから説明を省略する。
　本実施形態において中間層４は、応力緩和層４１と、樹脂層４２と、再配線層４３ｅと、ポスト４４ａ，４４ｂとを含む。応力緩和層４１および樹脂層４２は、上述の実施形態における構成と同様であるから説明を省略する。
　再配線層４３ｅは、下地層４３１ｅと、金属層４３２ｅとを有する。下地層４３１ｅの一部は応力緩和層４１を貫通している。また、下地層４３１ｅの一部は、応力緩和層４１に積層されている。下地層４３１ｅは、第１電極パッド２１，２２のいずれにも接する。下地層４３１ｅは、第１電極パッド２１，２２が腐食するのを防止する機能を担う。下地層４３１ｅは、たとえば、チタン、ニッケル、チタンタングステンなどの金属よりなる。金属層４３２ｅは、下地層４３１ｅに積層されている。金属層４３２ｅは、たとえば、銅などの金属よりなる。本実施形態では、ポスト４４ａ，４４ｂはいずれも、再配線層４３ｅに立設されている。
　次に、半導体装置Ａ２の作用効果について説明する。
　半導体装置Ａ２においては、半導体装置Ａ１と同様に、第１バンプ５１は方向ｘの一端且つ方向ｙの一端に配置されている。半導体装置Ａ２が実装基板８（本実施形態では図示略、第１実施形態参照）に実装された状態では、複数のバンプ５のうち第１バンプ５１に応力がかかりやすい。そのため、第１バンプ５１が疲労破壊しやすい。第１バンプ５１が疲労破壊すると、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１（本実施形態では図示略、第１実施形態参照）に至る電流の経路が遮断される。
　半導体装置Ａ２においては、第１電極パッド２１は、第２バンプ５２を経由して、実装パッド８１１と導通している。そのため、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１に至る電流の経路が遮断されても、第１電極パッド２１は、第２バンプ５２を経由して、実装パッド８１１と導通しうる。そのため、半導体装置Ａ２は、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１に至る電流の経路が遮断することに起因する動作不良を抑制するのに適する。
　半導体装置Ａ２においては、半導体装置Ａ１と同様に、ポスト４４ａと第１バンプ５１との接合面積Ｓ３は、ポスト４４ｂと第２バンプ５２との接合面積Ｓ４より大きい。このような構成は、第１バンプ５１にかかる応力を、小さくするのに適する。そのため、半導体装置Ａ２は、第１バンプ５１の疲労破壊を抑制するのに適する。したがって、半導体装置Ａ２は、上述の動作不良を抑制するのに、更に適する。
　半導体装置Ａ２においては、半導体装置Ａ１と同様に、ポスト４４ａの断面積Ｓ１は、ポスト４４ｂの断面積Ｓ２より大きい。このような構成も第１バンプ５１にかかる応力を小さくするのに適する。更に、当該構成はポスト４４ａの抵抗を小さくするのにも好適である。
　図１８は、本発明の第３実施形態にかかる半導体装置の要部断面図である。同図に示す半導体装置Ａ３は、半導体チップ１と、複数の電極パッド２と、被覆膜３と、中間層４と、複数のバンプ５と、樹脂コート８５を備える。半導体装置Ａ３は、第１電極パッド２１と第２バンプ５２とを、配線層１３が導通させているのではなく再配線層４３ｅのみが導通させている点において、上述の半導体装置Ａ２と相違する。
　半導体装置Ａ３においては、半導体装置Ａ２に関して述べたのと同様に、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１（本実施形態では図示略、第１実施形態参照）に至る電流の経路が遮断されても、第１電極パッド２１は、第２バンプ５２を経由して、実装パッド８１１と導通しうる。そのため、半導体装置Ａ３は、第１電極パッド２１から第１バンプ５１を経由して実装パッド８１１に至る電流の経路が遮断することに起因する動作不良を抑制するのに適する。
　半導体装置Ａ３においては、半導体装置Ａ１，Ａ２と同様に、ポスト４４ａと第１バンプ５１との接合面積Ｓ３は、ポスト４４ｂと第２バンプ５２との接合面積Ｓ４より大きい。このような構成は、第１バンプ５１にかかる応力を、小さくするのに適する。そのため、半導体装置Ａ３は、第１バンプ５１の疲労破壊を抑制するのに適する。したがって、半導体装置Ａ３は、上述の動作不良を抑制するのに、更に適する。
　半導体装置Ａ３においては、半導体装置Ａ１や半導体装置Ａ２のように配線層１３が第１電極パッド２１と第２バンプ５２とを導通させなくても、再配線層４３ｅが第１電極パッド２１と第２バンプ５２とを導通させることができる。再配線層４３ｅの形状パターンの設計自由度は高い。したがって、第１電極パッド２１と第２バンプ５２とが導通する構成を簡単に得ることができる。
　半導体装置Ａ３においては、半導体装置Ａ１，Ａ２と同様に、ポスト４４ａの断面積Ｓ１は、ポスト４４ｂの断面積Ｓ２より大きい。このような構成も第１バンプ５１にかかる応力を小さくするのに適する。更に、当該構成はポスト４４ａの抵抗を小さくするのにも好適である。
　図１９Ａ～図２２を用いて本発明の第４実施形態について説明する。図１９Ａは、本実施形態にかかる半導体装置の底面図であり、図１９Ｂは、本実施形態にかかる半導体装置の側面図（一部透視化）である。図２０は、図１９ＡのＸＸ－ＸＸ線に沿う要部断面図である。図２１は、図２０のＸＸＩ－ＸＸＩ線に沿う要部断面図である。
　これらの図に示す半導体装置Ａ４は、半導体チップ１と、複数の電極パッド２と、中間層４と、複数のバンプ５と、複数のワイヤ８７と、封止樹脂８８とを備える。半導体装置Ａ４は、ＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）タイプの半導体装置である。
　半導体チップ１および電極パッド２の各構成は、第３実施形態にて説明したとおりであるから、本実施形態ではこれらの説明を省略する。
　本実施形態において中間層４は、配線基板である。中間層４は、基材７１と、主面配線層７２と、裏面配線層７３と、スルーホール電極７４とを少なくとも含む。中間層４は、半導体チップ１を搭載している。図１９Ａに示すように、中間層４は、方向ｚ視において、方向ｘに延びる第１の縁４９ａと、方向ｙに延びる第２の縁４９ｂとにより規定される矩形状を呈する。
　基材７１は、たとえばエポキシ樹脂よりなる。基材７１は、主面７１１と主面７１１とは反対側を向く裏面７１２とを有する。
　主面配線層７２、裏面配線層７３、およびスルーホール電極７４は、たとえば、銅よりなる。主面配線層７２は、主面７１１に形成されている。裏面配線層７３は、裏面７１２に形成されている。スルーホール電極７４は、主面７１１から裏面７１２にわたって、基材７１を貫通している。スルーホール電極７４は、主面配線層７２および裏面配線層７３のいずれとも接している。これにより、主面配線層７２と裏面配線層７３とは互いに導通している。
　複数のワイヤ８７は、たとえば、銅、アルミニウム、もしくは金よりなる。図２０に示すように、複数のワイヤ８７のうちの一つは、第１電極パッド２１と主面配線層７２とに接する。これにより、第１電極パッド２１と主面配線層７２とは導通している。封止樹脂８８は、半導体チップ１、主面配線層７２、ワイヤ８７などを覆っている。封止樹脂８８は、たとえば、エポキシ樹脂よりなる。
　本実施形態においても、複数のバンプ５は、中間層４を挟んで半導体チップ１が配置された側と反対側に配置されている。すなわち、複数のバンプ５は、半導体チップ１とともに中間層４を挟むように配置されている。図１９Ａに示すように、本実施形態では、方向ｚ視において、複数のバンプ５は、碁盤の目状に配置されている。各バンプ５の配置態様は、上述の実施形態と同様であるから、説明を省略する。
　図１９Ａ～図２１に示すように、複数のバンプ５のうち２つを、第１バンプ５３、第２バンプ５４としている。図１９Ａに示すように、第１バンプ５３は、方向ｘの一端且つ方向ｙの一端に配置されている。図２０に示すように、第１バンプ５３は、裏面配線層７３に接合されている。第１バンプ５３と裏面配線層７３との接合面積Ｓ５（図２１参照）は、たとえば、たとえば、１７６７１～１９６３５０μｍ2である。第１バンプ５３は、方向ｚ視において、長さＬ５（図２１参照）を直径とする円形状である。長さＬ５は、たとえば、１５０～５００μｍである。第１バンプ５３は、裏面配線層７３、スルーホール電極７４、主面配線層７２、およびワイヤ８７を経由して、第１電極パッド２１と導通している。
　第２バンプ５４は、裏面配線層７３に接合されている。第２バンプ５４は、複数のバンプ５のうち第１バンプ５３に隣接しているものである。第２バンプ５４は第１バンプ５３に隣接しているものに限られず、たとえば、複数のバンプ５のうち略中央に配置されたものであってもよい。第２バンプ５４と裏面配線層７３との接合面積Ｓ６（図２１参照）は、たとえば、７８５４～１２５６６４μｍ2である。接合面積Ｓ６よりも接合面積Ｓ５の方が大きいことが好ましい。たとえば、接合面積Ｓ５は、接合面積Ｓ６よりも１．１倍～１．５倍であることが好ましい。第２バンプ５４は、方向ｚ視において、長さＬ６（図２１参照）を直径とする円形状である。長さＬ６よりも長さＬ５が大きい方が好ましい。たとえば、長さＬ６は、長さＬ５の１．１倍～１．５倍であることが好ましい。長さＬ６は、たとえば、１００～４００μｍである。第２バンプ５４は、裏面配線層７３、スルーホール電極７４、主面配線層７２、およびワイヤ８７を経由して、第１電極パッド２１と導通している。本実施形態においては、第１バンプ５３と第２バンプ５４とを、裏面配線層７３が導通させている。
　図２２、図２３は、半導体装置Ａ４が実装基板８に実装された状態を示す図である。半導体装置Ａ４が実装基板８に実装されるとき、各バンプ５が実装基板８における実装パッド８１に接合される。これにより、半導体基板１１に形成された集積回路の端子（図示略）が実装パッド８１と導通する。複数の実装パッド８１のうち第１バンプ５３が接合される実装パッド８１１と、複数の実装パッド８１のうち第２バンプ５４が接合される実装パッド８１２とは、実装基板８上における配線８２（図２２では略）を介して、互いに導通している。そのため、主面配線層７２、裏面配線層７３、スルーホール電極７４、図２３に示すワイヤ８７、第１電極パッド２１、第１バンプ５３、第２バンプ５４、実装パッド８１１，８１２、および、配線８２は、互いに導通している。
　なお、本実施形態においても、複数のバンプ５のうち四角に配置されたもの全てを、第１バンプ５３と同様の構成としてもよい。
　次に、半導体装置Ａ４の作用効果について説明する。
　半導体装置Ａ４においては、第１バンプ５３は方向ｘの一端且つ方向ｙの一端に配置されている。半導体装置Ａ４が実装基板８に実装された状態では、複数のバンプ５のうち第１バンプ５３に応力がかかりやすい。そのため、第１バンプ５３が疲労破壊しやすい。第１バンプ５３が疲労破壊すると、第１電極パッド２１から第１バンプ５３を経由して実装パッド８１１に至る電流の経路が遮断される。
　半導体装置Ａ４においては、第１電極パッド２１は、第２バンプ５４を経由して、実装パッド８１１と導通している。そのため、第１電極パッド２１から第１バンプ５３を経由して実装パッド８１１に至る電流の経路が遮断されても、第１電極パッド２１は、第２バンプ５４を経由して、実装パッド８１１と導通しうる。そのため、半導体装置Ａ４は、第１電極パッド２１から第１バンプ５３を経由して実装パッド８１１に至る電流の経路が遮断することに起因する動作不良を、抑制するのに適する。
　半導体装置Ａ４においては、図２１に示したように、接合面積Ｓ５は、接合面積Ｓ６より大きい。このような構成は、第１バンプ５３にかかる応力を小さくするのに適する。そのため、半導体装置Ａ４は、第１バンプ５３の疲労破壊を抑制するのに適する。したがって、半導体装置Ａ４は、上述の動作不良を抑制するのに更に適する。
　基材７１の主面７１１には、半導体チップ１が配置されている。また、主面配線層７２には、ワイヤ８７を接続する必要もある。そのため、主面配線層７２の形状の自由度は比較的低い。一方、裏面配線層７３にはバンプ５を形成するのみである。そのため、裏面配線層７３の形状は比較的自由に決定することができる。そのため、半導体装置Ａ４によると、第１バンプ５３と第２バンプ５４とを比較的簡単に導通させることができる。
　図２４は、本発明の第５実施形態にかかる半導体装置を示す要部断面図である。同図に示す半導体装置Ａ５は、主面配線層７２が第１バンプ５３と第２バンプ５４とを導通させている点において、上述の半導体装置Ａ４と相違する。このような構成によっても、半導体装置Ａ４に関して述べたのと同様の理由により、上述の動作不良を抑制することができる。
　本発明の範囲は、上述した実施形態に限定されるものではない。本発明の各部の具体的な構成は、種々に設計変更自在である。寸法Ｌ１が寸法Ｌ２より大きいことが好ましいが、第１バンプ５１および第２バンプ５２が第１電極パッド２１に導通していれば、寸法Ｌ１は寸法Ｌ２以下でもよい。同様に、長さＬ３は長さＬ４以下でもよい。同様に、長さＬ５は長さＬ６以下でもよい。同様に、面積Ｓ１は面積Ｓ２以下でもよい。同様に、面積Ｓ３は面積Ｓ４以下でもよい。同様に、面積Ｓ５は面積Ｓ６以下でもよい。
　複数のバンプ５のうち、第２バンプ５２や第２バンプ５４と同様の機能を有するものが複数あってもよい。

Claims (18)

  1. 　半導体チップと、
    　上記半導体チップに積層された第１電極パッドと、
    　第１の縁と第２の縁とに規定された矩形状を呈する中間層と、
    　上記半導体チップとともに上記中間層を挟むように配置された複数のバンプと、を備え、
    　上記第１の縁は、上記半導体チップの厚さ方向に交差する第１方向に延び、上記第２の縁は、上記厚さ方向および上記第１方向のいずれにも交差する第２方向に延び、上記複数のバンプのいずれか一つは、上記第１電極パッドに導通する第１バンプであり、上記複数のバンプのいずれか一つは、上記第１電極パッドに導通する第２バンプであり、上記第１バンプは、上記複数のバンプのうち、上記第１方向の一端且つ上記第２方向の一端に配置されたものである、半導体装置。
  2. 　上記半導体チップに積層された第２電極パッドを更に備え、
    　上記半導体チップは、上記第１電極パッドおよび上記第２電極パッドを導通させる配線層を含み、上記第２バンプは、上記第２電極パッドを経由して上記第１電極パッドと導通している、請求項１に記載の半導体装置。
  3. 　上記第１電極パッドおよび上記第２電極パッドを露出させる被覆膜を更に備え、
    　上記中間層は、上記被覆膜に積層された応力緩和層と、上記応力緩和層に積層された第１再配線層と、上記応力緩和層に積層された第２再配線層と、を含み、上記第１再配線層は、上記厚さ方向視において上記第１バンプと重なる部位を有し、上記第２再配線層は、上記厚さ方向視において上記第２バンプと重なる部位を有し、上記第１再配線層と上記第２再配線層とは互いに離間している、請求項２に記載の半導体装置。
  4. 　上記第１電極パッドおよび上記第２電極パッドを露出させる被覆膜を更に備え、
    　上記中間層は、上記被覆膜に積層された応力緩和層と、上記応力緩和層に積層された再配線層と、を含み、上記再配線層は、上記第１バンプおよび上記第２バンプを導通させている、請求項２に記載の半導体装置。
  5. 　上記第１電極パッドを露出させる被覆膜を更に備え、
    　上記中間層は、上記被覆膜に積層された応力緩和層と、上記応力緩和層に積層された再配線層と、を含み、上記再配線層は、上記第１バンプおよび上記第２バンプを導通させている、請求項１に記載の半導体装置。
  6. 　上記中間層は、上記半導体チップの厚さ方向に延びる第１ポストと、上記半導体チップの厚さ方向に向かって延びる第２ポストと、を含み、上記第１ポストは、上記第１バンプに接し、上記第２ポストは、上記第２バンプに接する、請求項１ないし５のいずれかに記載の半導体装置。
  7. 　上記第１ポストと上記第１バンプとの接合面積は、上記第２ポストと上記第２バンプとの接合面積より大きい、請求項６に記載の半導体装置。
  8. 　上記第１方向および上記第２方向に広がる平面による上記第１ポストの断面積は、上記第１方向および上記第２方向に広がる平面による上記第２ポストの断面積より大きい、請求項６または７に記載の半導体装置。
  9. 　上記第１ポストは第１寸法を直径として上記厚さ方向に延びる円柱状であり、上記第２

    ポストは上記第１寸法より小さい第２寸法を直径として上記厚さ方向に延びる円柱状である、請求項６ないし８のいずれかに記載の半導体装置。
  10. 　上記第１寸法は、上記第２寸法の１．１倍～１．５倍である、請求項９に記載の半導体装置。
  11. 　上記中間層は、主面および裏面を有する基材と、上記主面に形成された主面配線層と、上記裏面に形成された裏面配線層と、を含み、上記裏面は上記主面の反対側を向き、上記主面には、上記半導体チップが搭載されており、上記裏面配線層は、上記主面配線層と導通し、上記裏面配線層は、上記第１バンプおよび上記第２バンプのいずれにも接する、請求項１に記載の半導体装置。
  12. 　上記第１バンプおよび上記第２バンプの体積はいずれも同一である、請求項１ないし１１のいずれかに記載の半導体装置。
  13. 　上記複数のバンプは、２５個以上である、請求項１ないし１２のいずれかに記載の半導体装置。
  14. 　上記厚さ方向視において上記第１バンプは第１長さを直径とする円形状であり、上記厚さ方向視において上記第２バンプは上記第１長さより小さい第２長さを直径とする円形状である、請求項１ないし１３のいずれかに記載の半導体装置。
  15. 　上記第１長さは、上記第２長さの１．１倍～１．５倍である、請求項１４に記載の半導体装置。
  16. 　上記第２バンプは、上記複数のバンプのうち上記第１バンプに最も隣接しているものである、請求項１ないし１５のいずれかに記載の半導体装置。
  17. 　上記第１バンプおよび上記第２バンプはいずれも機能ピンである、請求項１ないし１６のいずれかに記載の半導体装置。
  18. 　上記複数のバンプのうち四角に配置されたものは上記第１バンプである、請求項１ないし１７のいずれかに記載の半導体装置。
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