TWI538133B - 墊結構及其形成方法以及具有該墊結構的半導體裝置 - Google Patents

墊結構及其形成方法以及具有該墊結構的半導體裝置 Download PDF

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TWI538133B
TWI538133B TW102144774A TW102144774A TWI538133B TW I538133 B TWI538133 B TW I538133B TW 102144774 A TW102144774 A TW 102144774A TW 102144774 A TW102144774 A TW 102144774A TW I538133 B TWI538133 B TW I538133B
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Taiwan
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pads
pad
package substrate
layer
substrate
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TW102144774A
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TW201423936A (zh
Inventor
劉浩君
莊其達
莊曜群
曾明鴻
陳承先
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台灣積體電路製造股份有限公司
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
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Description

墊結構及其形成方法以及具有該墊結構的半導體裝置
本發明是關於半導體晶片封裝技術，特別是關於封裝基板的墊結構及其形成方法。
半導體工業已歷經了快速成長，這是因為在各種電子構件(例如電晶體、二極體、電阻器、電容器等等)的積集密度(integration density)的持續改善。其中最大的部分，在積集密度的改善是來自最小特徵尺寸的不斷縮減，而可將更多的構件整合至一既定區域。隨著近來對更小的電子裝置需求的成長，對於半導體晶片的更小、更創新的封裝技術的需求仍不斷成長。
隨著半導體技術的發展，應用晶片尺度或晶片尺寸封裝的半導體裝置已浮現更有效率的方案來進一步縮減一半導體晶片的物理尺寸。在一應用晶片尺度封裝的半導體裝置中，封裝是發生在晶片具有由各種凸塊構成的接點上。藉由應用晶片尺度封裝的半導體裝置的採用，可達成更高的密度。還有，應用晶片尺度封裝的半導體裝置可達成更小的形狀因子、具有成本效率、性能的提升、較低的能耗及較低的產熱。
為了提升製造效率及降低製造成本，可在半導體晶圓中製造積體電路，每一片晶圓包含許多相同的半導體晶片。一旦完成積體電路的製造，可對半導體晶圓施加一切割製程。其結果，將半導體晶片從晶圓切出。
在一封裝製程中，可將半導體晶片貼附於一封裝基板。封裝製程的製造步驟可包含在封裝基板上保全半導體晶片，並將半導體晶片上的銲墊連接於封裝基板上的銲墊。還有，可應用一底膠填充(underfill)層來進一步保全半導體晶片與封裝基板之間的接合。
本發明的一實施例是提供一種墊結構，包含：一第一墊，突出於一封裝基板的一上表面的上方，其中上述第一墊具有一第一細長形狀；一第二墊，嵌於上述封裝基板中，其中上述第二墊具有一第二細長形狀；以及一介層窗，耦接於上述第一墊與上述第二墊之間。
在上述之墊結構中，較好為更包含一第三墊，嵌於上述封裝基板中，且鄰接上述第二墊；以及一跡線(trace)，耦接於上述第二墊且位於上述第二墊與上述第三墊之間。
在上述之墊結構中，上述第一細長形狀較好是選自下列組成之族群：具有弧形邊的長方形、橢圓形、多邊形以及具有弧形邊的正方形。
在上述之墊結構中，上述第二細長形狀較好是選自下列組成之族群：具有弧形邊的長方形、橢圓形、多邊形以及具有弧形邊的正方形。
在上述之墊結構中，較好為更包含：複數個底墊， 嵌於上述封裝基板中；以及複數個頂墊，突出於上述封裝基板的上方；其中上述底墊具有細長形狀；上述底墊是排列成一向心性的圖形；上述頂墊具有細長形狀；以及上述頂墊是排列成行列(rows and columns)。
在上述之墊結構中，較好為更包含：複數個底墊， 嵌於上述封裝基板中；以及複數個頂墊，突出於上述封裝基板的上方；其中上述底墊具有細長形狀；上述底墊是排列成行列；上述頂墊具有細長形狀；以及上述頂墊是排列成一向心性的圖形。
在上述之墊結構中，較好為更包含：複數個底墊， 嵌於上述封裝基板中；以及複數個頂墊，突出於上述封裝基板的上方；其中上述底墊具有細長形狀；上述底墊是排列成行列；上述頂墊具有細長形狀；以及上述頂墊是排列成行列。
在上述之墊結構中，較好為更包含：複數個底墊， 嵌於上述封裝基板中；以及複數個頂墊，突出於上述封裝基板的上方；其中上述底墊具有細長形狀；上述底墊是排列成一向心性的圖形；上述頂墊具有細長形狀；以及上述頂墊是排列成一向心性的圖形。
本發明的另一實施例是提供一種半導體裝置，包 含：一半導體晶片，具有主動電路；一金屬凸塊，形成於上述半導體晶片的一第一側上，其中上述主動電路是鄰接上述第一側；以及一封裝基板，經由上述金屬凸塊耦接於上述半導體晶片，其中上述封裝基板包含：一頂墊，突出於上述封裝基板的 一上表面的上方，其中上述頂墊具有一第一細長形狀；一底墊，嵌於上述封裝基板中，其中上述底墊具有一第二細長形狀；及一介層窗，耦接於上述頂墊與上述底墊之間。
在上述之半導體裝置中，較好為：上述金屬凸塊是由銅形成。
在上述之半導體裝置中，較好為更包含：一銲阻層，形成於上述封裝基底的上方，其中上述頂墊突出於上述銲阻層的一上表面的上方。
在上述之半導體裝置中，較好為更包含：複數個連接墊，形成於上述封裝基底的上方，其中上述連接墊是排列成一向心性的圖形。
在上述之半導體裝置中，較好為更包含：複數個連接墊，形成於上述封裝基底的上方，其中上述連接墊是排列成行列。
在上述之半導體裝置中，較好為更包含：複數個佈線墊(routing pads)，嵌於上述封裝基板中，其中上述佈線墊是排列成行列。
在上述之半導體裝置中，較好為更包含：複數個佈線墊，嵌於上述封裝基板中，其中上述佈線墊是排列成一向心性的圖形。
本發明的又另一實施例是提供一種墊結構的形成方法，包含：在一封裝基板中形成複數個第一墊，其中上述第一墊具有一第一細長形狀；在上述第一墊的上方形成複數個介層窗；以及在上述介層窗的上方形成複數個第二墊；其中上述 第二墊具有一第二細長形狀；及上述第二墊是經由上述介層窗耦接於上述第一墊。
在上述之墊結構的形成方法中，較好為更包含：在上述封裝基板的上方沉積一銲阻層，其中上述第二墊是在上述銲阻層的一上表面的上方。
在上述之墊結構的形成方法中，較好為：上述第一墊是排列成行列；以及上述第二墊是排列成一向心性的圖形。
在上述之墊結構的形成方法中，較好為：上述第一墊是排列成一向心性的圖形；以及上述第二墊是排列成行列。
在上述之墊結構的形成方法中，較好為：上述第一墊是排列成行列；以及上述第二墊是排列成行列。
在上述之墊結構的形成方法中，較好為：上述第一墊是排列成一向心性的圖形；以及上述第二墊是排列成一向心性的圖形。
100‧‧‧半導體裝置
101‧‧‧半導體晶片
102‧‧‧基底
104‧‧‧層間介電層
106‧‧‧底部金屬化層
108‧‧‧頂部金屬化層
110‧‧‧介電層
112‧‧‧第一鈍化層
114‧‧‧第二鈍化層
116‧‧‧接合墊(鋁墊)
117‧‧‧接合墊(鋁墊)
118‧‧‧PI層(聚合物層)
120‧‧‧凸塊下金屬結構
122‧‧‧金屬凸塊
123‧‧‧金屬凸塊
124‧‧‧軟銲球
125‧‧‧軟銲球
126‧‧‧第一金屬線
128‧‧‧第二金屬線
129‧‧‧頂部金屬連接器
150‧‧‧基板
152‧‧‧頂墊
153‧‧‧介層窗
154‧‧‧底墊
155‧‧‧頂墊
156‧‧‧介層窗
157‧‧‧底墊
158‧‧‧銲阻層
200‧‧‧半導體裝置
202‧‧‧軟銲球
204‧‧‧軟銲球
400‧‧‧第一俯視圖
410‧‧‧第二俯視圖
412‧‧‧中心
500‧‧‧第一俯視圖
502‧‧‧頂墊
504‧‧‧頂墊
506‧‧‧頂墊
508‧‧‧頂墊
510‧‧‧第二俯視圖
511‧‧‧跡線
512‧‧‧底墊
513‧‧‧跡線
514‧‧‧底墊
515‧‧‧跡線
516‧‧‧底墊
518‧‧‧底墊
902‧‧‧區域
904‧‧‧區域
906‧‧‧區域
908‧‧‧區域
912‧‧‧中心
第1圖是一剖面圖，顯示本發明的各種實施例的一半導體裝置。
第2圖是一剖面圖，顯示本發明的各種實施例的另一種半導體裝置。
第3圖是一詳細的剖面圖，顯示本發明的各種實施例的示於第1圖與第2圖的半導體裝置。
第4圖是顯示本發明的各種實施例的頂墊與底墊的俯視
圖。
第5圖是顯示本發明的各種實施例的頂墊與底墊的俯視圖。
第6圖是顯示本發明的各種實施例的頂墊與底墊的另一種俯視圖。
第7圖是顯示本發明的各種實施例的頂墊與底墊的另一種俯視圖。
第8圖是顯示本發明的各種實施例的頂墊與底墊的另一種俯視圖。
第9圖是顯示本發明的各種實施例的另一種墊配置。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。以下將配合所附圖式詳述本發明之實施例，其中同樣或類似的元件將盡可能以相同的元件符號表示。在圖式中可能誇大實施例的形狀與厚度以便清楚表面本發明之特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方，即表示其包含了所形成的上述第一特徵與上 述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本說明書以下的揭露內容可能在各個範例中使用重複的元件符號，以使說明內容更加簡化、明確，但是重複的元件符號本身並未指示不同的實施例及/或結構之間的關係。
本發明將會以特定的文章脈絡針對本發明的實施 例作敘述，其中一封裝基板具有形成於此封裝基板上方的一第一細長墊與嵌於此封裝基板中的一第二細長墊。然而，本發明亦可應用於各種的封裝基板。以下，參考對應的圖式，將會詳細地解釋各種實施例。
第1圖是一剖面圖，顯示本發明的各種實施例的一 半導體裝置。半導體裝置100可包含一半導體晶片101與一基板150。在某些實施例中，基板150可以是一封裝基板。特別是，基板150可以是一轉化墊覆晶(translation pad flip chip；TPFC)基板。
如第1圖所示，半導體晶片101可包含複數個金屬 凸塊(例如金屬凸塊122與123)與形成於其對應的金屬凸塊上方的複數個軟銲球(例如軟銲球124與125)。基板150可包含複數個連接墊。更詳細而言，可以有複數個頂墊(例如頂墊152與155)是突出於基板150的一上表面的上方。還有，可以有複數個底墊(例如底墊154與157)是嵌於基板150中。如第1圖所示，可以有複數個介層窗(例如介層窗153與156)是連接於上述頂墊與上述底墊之間。在某些實施例中，基板150的墊間距(pad pitch) 是小於130μm。
半導體晶片101將會經由半導體晶片101上的金屬 凸塊(例如金屬凸塊122與123)及基板150上的頂墊(例如頂墊152與155)而安裝於基板150上。如第1圖所示，頂墊152與155是形成在基板150的頂部上。
金屬凸塊122與123是形成在半導體晶片101的一 第一側上。在某些實施例中，半導體晶片101的第一側是形成有半導體晶片101的主動電路的那一側。
根據半導體裝置100的接合製程，可以有一軟銲球 (例如為軟銲球124與125)是在將半導體晶片101安裝於基板150上之前，形成在每個金屬凸塊(例如金屬凸塊122與123)上。還有，將半導體晶片101貼附於基板150之後，可經由一迴銲(reflow)製程使軟銲球124與125熔化。因此，將半導體晶片101接合於基板150上。
軟銲球124與125可由任何適用的材料製造。在某 些實施例中，軟銲球124與125可包含SAC405。SAC405包含95.5% Sn、4.0% Ag與0.5% Cu。
第1圖還顯示可以有形成於基板150的上方的一銲 阻層158。銲阻層158是被沉積於基板150的上表面上。如第1圖所示，頂墊152與155是突出於銲阻層158的上表面的上方。
將半導體晶片101安裝於基板150上之後，可在基 板150、也在半導體晶片101的上方形成一囊封層(encapsulation layer)(未繪示)。更詳細而言，半導體晶片101是被嵌於上述囊封層中。在某些實施例中，上述囊封層可以是一封膠層(molding compound layer)、一底膠填充(underfill)層等等。在整篇說明書中，上述囊封層可能會被改稱為一封膠層。
上述封膠層可由以環氧樹脂為基底的樹脂等形 成。此外，上述封膠層可被光敏材料替代，上述光敏材料包含聚苯噁唑(polybenzoxazole；PBO)、SU-8光敏環氧樹脂、薄膜形式的聚合物材料等等。上述封膠層的形成可藉由一旋轉塗佈法(spin-on coating)製程、乾膜層積製程等等。
具有一封膠層的一項優點在於上述封膠層可幫助 保護半導體晶片101不受熱、衝擊、濕氣以及腐蝕的侵害。此外，上述封膠層可幫助避免半導體裝置100在例如熱循環製程等的可靠度試驗的過程中龜裂。另一項優點在於上述封膠層可幫助減少在半導體裝置100的製造過程中的機械應力與熱應力。
第2圖是一剖面圖，顯示本發明的各種實施例的另 一種半導體裝置。示於第2圖的半導體裝置200是類似於第1圖所示的半導體裝置100，除了將軟銲球202與204形成於頂墊152與155的頂面上之外，因此未在此處敘述而避免重複。
要注意的是第1圖與第2圖所示的金屬凸塊(例如為 金屬凸塊122與123)僅為一範例。本發明可應用於各種的半導體凸塊。
第3圖是一詳細的剖面圖，顯示本發明的各種實施 例的示於第1圖與第2圖的半導體裝置。如第1與2圖所示，半導體裝置100包含半導體晶片101與基板150，其中半導體晶片101是經由金屬凸塊(例如金屬凸塊122)與頂墊(例如頂墊152)形成 的一連接結構而耦合於基板150。基板150可以是一封裝基板，例如一轉化墊覆晶基板。此外，基板150的結構可以類似於半導體晶片101。為了簡潔，第3圖僅繪示半導體晶片101的詳細結構。
基底102可由矽形成，但其亦可由其他III族、IV族及/或V族元素形成，例如為矽、鍺、鎵、砷、上述之組合等等。基底102亦可為絕緣層上覆矽(silicon-on-insulator；SOI)的形式。上述絕緣層上覆矽基底可具有形成於一絕緣層(例如埋入式氧化物層等等)的上方的一層半導體材料(例如矽、鍺等等)，其中上述絕緣層是形成於一基底中。此外，亦可使用其他基底，包含多層基底、組成漸變基底、混合結晶取向基底等等。基底102可更包含各種電路(未繪示)。形成於基底102上的上述電路可以是適用於一特定應用的任何形式的電路系統。
在某些實施例中，上述電路可包含各種n型金屬-氧化物-半導體(n-type metal-oxide semiconductor；NMOS)裝置及/或p型金屬-氧化物-半導體(p-type metal-oxide semiconductor；PMOS)裝置，例如電晶體、電容器、電阻器、二極體、光學二極體、熔絲(fuse)等等。上述電路可彼此互連，以執行一或多項功能。上述功能可包含記憶體結構、處理結構、感測器、放大器、配電(power distribution)、輸入/輸出電路系統等等。本技術領域中具有通常知識者應可瞭解以上提供的例子是為了例示的目的，僅為了進一步解釋本發明的應用範圍，而不是為了以任何形態限制本發明的範圍。
一層間介電層104是形成於基底102的頂部上。例 如，可以以例如氧化矽等的一低介電常數介電材料來形成層間介電層104。層間介電層104的形成可藉由任何本技術領域已知的適當的方法，例如旋轉塗佈法、化學氣相沉積(chemical vapor deposition；CVD)以及電漿增益化學氣相沉積(plasma enhanced chemical vapor deposition；PECVD)。要注意的是本技術領域中具有通常知識者應可瞭解層間介電層104可更包含複數層的介電層。
一底部金屬化層106與一頂部金屬化層108是形成 於層間介電層104的上方。如第3圖所示，底部金屬化層106包含一第一金屬線126。同樣地，頂部金屬化層108包含一第二金屬線128。第一金屬線126與第二金屬線128是由例如銅或銅合金等的金屬材料形成。底部金屬化層106與頂部金屬化層108可經由任何適當的製程(例如沉積、鑲嵌等等)來形成。總而言之，一或多個金屬間介電層與相關的金屬化層是用來使基底102中的電路互連以形成功能性的電路系統，並進一步提供一外部電性連接。
要瞭解的是雖然第3圖顯示底部金屬化層106與頂 部金屬化層108，本技術領域中具有通常知識者應可瞭解一或多個金屬間介電層(未繪示)與相關的金屬化層(未繪示)是形成於底部金屬化層106與頂部金屬化層108之間。具體而言，在底部金屬化層106與頂部金屬化層108之間的各層，可藉由交互排列的介電質(例如極低介電常數介電材料(extremely low-k dielectric material))層與導體材料(例如銅)層而形成。
一介電層110是形成於頂部金屬化層108的頂部 上。如第3圖所示，一頂部金屬連接器129是被嵌於介電層110中。具體而言，頂部金屬連接器129是提供第二金屬線128與半導體裝置的電性連接結構之間的導電通道。頂部金屬連接器129可由金屬材料製造，例如銅、銅合金、鋁、銀、金及上述的任一組合。頂部金屬連接器129可藉由例如化學氣相沉積等的適當的技術形成。作為替代方案，頂部金屬連接器129可藉由濺鍍、電鍍等形成。
一第一鈍化層112是形成於介電層110的頂部上。 在某些實施例中，是以無機材料例如未摻雜的矽酸玻璃、氮化矽、氧化矽等形成第一鈍化層112。作為一替代方案，可以以例如摻碳的氧化物等的低介電常數介電質來形成第一鈍化層112。此外，例如多孔質的摻碳的二氧化矽等的極低介電常數(extremely low-k；ELK)介電質可用來形成第一鈍化層112。第一鈍化層112可經由例如化學氣相沉積等的任何適當的技術形成。如第3圖所示，可以有形成於第一鈍化層112中的開口。上述開口是用來安裝接合墊116，此接合墊116會在後文中詳細敘述。
一第二鈍化層114是形成於第一鈍化層112的頂部 上。第二鈍化層114可與第一鈍化層112類似，因此為了避免不必要重複而不更詳細地討論。如第3圖所示，在第一鈍化層112與第二鈍化層114的開口中形成接合墊116與117。在某些實施例中，可以由鋁來形成接合墊116與117。為了簡潔，在整份說明書中，可將接合墊116與117改稱為鋁墊116與117。
鋁墊116與117可被第一鈍化層112與第二鈍化層 114封閉。具體而言，鋁墊116與117的底部是嵌於第一鈍化層112中，而鋁墊116與117的頂部則嵌於第二鈍化層114中。
第一鈍化層112與第二鈍化層114重疊並密封鋁墊 116與117的邊緣，以藉由避免鋁墊116與117受到腐蝕而改善電性穩定度。此外，第一鈍化層112與第二鈍化層114可幫助減少半導體裝置的漏電流。
一聚合物層118是形成於第二鈍化層114的頂部 上。聚合物層118是由例如環氧樹脂、聚醯亞胺(polyimide；PI)等的聚合物材料製造。具體而言，聚合物層118可包含可由光定義的聚醯亞胺材料，例如HD4104。為了簡潔，在整份說明書中，會將聚合物層118改稱為PI層118。可藉由例如旋轉塗佈法等本技術領域已知的任何適當方法來製造PI層118。
若將上述接合墊重新安排至新的位置，可在半導 體裝置100中形成一重分佈層(redistribution layer)(未繪示)。上述重分佈層是在金屬線(例如第二金屬線128)與被重分佈的接合墊之間提供一導電路徑。上述重分佈層的作用原理已為本技術領域所熟知，因此在此不作詳細討論。
將PI層118圖形化以形成複數個開口。還有，在上 述開口的頂部上形成各種的凸塊下金屬(under bump metal；UBM)結構120。凸塊下金屬結構120是用來使鋁墊(例如鋁墊116與117)連接於各種的輸入與輸出端子(例如金屬凸塊122與123)。可藉由例如電鍍等的任何適當的技術來形成凸塊下金屬結構120。其他形成製程例如濺鍍、蒸鍍、電漿增益化學氣相沉積等等可取代前述形成凸塊下金屬結構120的技術，視所需 要的材料而定。
在某些實施例中，金屬凸塊122與123可以是銅凸 塊。上述銅凸塊的高度可為約45μm。在某些實施例中，各種封裝技術例如濺鍍、電鍍以及微影可用來形成上述銅凸塊。如本技術領域的已知技術，為了確保上述銅凸塊與接合墊116與117之間的可靠的黏著與電氣導通(electrical continuity)，可在上述銅凸塊與接合墊116與117之間形成一附加層，此附加層包含一阻障層、一黏著層與一種子層(均未繪示)。
第4圖是顯示本發明的各種實施例的頂墊與底墊 的俯視圖。請回去參考第1圖，有複數個頂墊在基板150上，且有複數個底墊嵌於基板150中。然而第1圖的剖面圖無法顯示上述頂墊與底墊的形狀。
一第一俯視圖400顯示上述頂墊與上述底墊可以 是細長的墊。要瞭解的是，第4圖中所示的形狀僅為一範例，而不應用以限制本發明請求項的範圍。本發明所屬技術領域中具有通常知識者可理解有許多變形、替代物與改良。例如使墊具有其他形狀例如但不限於具有弧形邊的長方形、橢圓形、多邊形、具有弧形邊的正方形、上述的任意組合等等，均在本發明的範疇與發明精神內。
第一俯視圖400顯示了四群的墊。然而，本發明所 屬技術領域中具有通常知識者可理解基板150可具有複數個頂墊與底墊。此外，上述複數個頂墊在形狀方面為細長形，且在基板150的上表面上排列成行列(rows and columns)。同樣地，上述複數個底墊在形狀方面為細長形，且在基板150的上表面 上排列成行列。
一第二俯視圖410顯示上述頂墊與底墊可具有細 長的形狀並排列成一向心性的圖形。具體而言，如第4圖所示，基底150的上表面可具有一中心412。上述頂墊或上述底墊可在形狀方面為細長形。每個細長形墊的長軸是指向中心412。要注意的是雖然第二俯視圖410顯示十六個細長形墊，但上述半導體裝置可裝配任何數量的細長形墊。
第5圖是顯示本發明的各種實施例的頂墊與底墊 的俯視圖。在某些實施例中，一第一俯視圖500是顯示基板150(示於第1圖)的頂墊的形狀。如第5圖所示，頂墊502、504、506及508在形狀方面為細長形。
一第二俯視圖510是顯示基板150的底墊的形狀。如第5圖所示，底墊512、514、516及518在形狀方面為細長形。此外，跡線(trace)513與515是分別耦合於底墊512與514。跡線511、513與515是位於底墊512、514、516及518之間。
如第5圖所示之具有細長形狀的底墊的一項優點是上述細長形狀的底墊(例如底墊512與514)可為耦合於上述底墊的上述跡線提供繞線空間。
第6圖是顯示本發明的各種實施例的頂墊與底墊的另一種俯視圖。示於第6圖的俯視圖是與示於第5圖的俯視圖相似，除了基板150(示於第1圖)的頂墊可排列成一向心性的圖形之外。排列成一向心性的圖形的墊已被詳細敘述於根據第4圖所作說明，因此為了避免重複而不再討論。
第7圖是顯示本發明的各種實施例的頂墊與底墊 的另一種俯視圖。示於第7圖的俯視圖是與示於第5圖的俯視圖相似，除了底墊與偶合於上述底墊的跡線可排列成一向心性的圖形之外。排列成一向心性的圖形的墊已被詳細敘述於根據第4圖所作說明，因此為了避免重複而不再討論。
第8圖是顯示本發明的各種實施例的頂墊與底墊 的另一種俯視圖。示於第8圖的俯視圖是與示於第5圖的俯視圖相似，除了基板150的頂墊與底墊均可排列成一向心性的圖形之外。排列成一向心性的圖形的墊已被詳細敘述於根據第4圖所作說明，因此為了避免重複而不再討論。
第9圖是顯示本發明的各種實施例的另一種墊配 置。排列成一向心性的圖形的墊已被詳細敘述於根據第4圖所作說明。請回去參考第4圖，在第4圖中可具有一中心412。第4圖所示的細長形墊的長軸是指向中心412。換句話說，第4圖所示的細長形墊是排列成一向心性的圖形。
第4圖中所示的向心性的圖形僅為一範例，而不應 用以限制本發明請求項的範圍。本發明所屬技術領域中具有通常知識者可理解有許多變形、替代物與改良。例如如第9圖所示，基板150的上表面被分成四個區域，也就是區域902、904、906與908。在每一個區域(例如區域902)中的細長形墊、還有沿著每一個區域之間的邊界排列的細長形墊，可指向基板150的上表面的中心912。
雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體裝置
101‧‧‧半導體晶片
122‧‧‧金屬凸塊
123‧‧‧金屬凸塊
124‧‧‧軟銲球
125‧‧‧軟銲球
150‧‧‧基板
152‧‧‧頂墊
153‧‧‧介層窗
154‧‧‧底墊
155‧‧‧頂墊
156‧‧‧介層窗
157‧‧‧底墊
158‧‧‧銲阻層

Claims (8)

  1. 一種墊結構，包含：一第一墊，突出於一封裝基板的一上表面的上方，其中該第一墊具有一第一細長形狀；一第二墊，嵌於該封裝基板中，其中該第二墊具有一第二細長形狀，且其中該第一墊和該第二墊藉由一銲阻層彼此分離；以及一介層窗，耦接於該第一墊與該第二墊之間。
  2. 如申請專利範圍第1項所述之墊結構，其中：該第一細長形狀是選自下列組成之族群：具有弧形邊的長方形、橢圓形、多邊形以及具有弧形邊的正方形；以及該第二細長形狀是選自下列組成之族群：具有弧形邊的長方形、橢圓形、多邊形以及具有弧形邊的正方形。
  3. 如申請專利範圍第1項所述之墊結構，更包含：複數個底墊，嵌於該封裝基板中；以及複數個頂墊，突出於該封裝基板的上方；其中，該些底墊具有細長形狀；該些底墊是排列成一向心性的圖形或行列；該些頂墊具有細長形狀；以及該些頂墊是排列成行列(rows and columns)或一向心性的圖形。
  4. 一種半導體裝置，包含：一半導體晶片，具有主動電路； 一金屬凸塊，形成於該半導體晶片的一第一側上，其中該主動電路是鄰接該第一側；以及一封裝基板，經由該金屬凸塊耦接於該半導體晶片，其中該封裝基板包含：一頂墊，突出於該封裝基板的一上表面的上方，其中該頂墊具有一第一細長形狀；一底墊，嵌於該封裝基板中，其中該底墊具有一第二細長形狀；一介層窗，耦接於該頂墊與該底墊之間；以及一銲阻層，形成於該封裝基底的上方，其中該頂墊突出於該銲阻層的一上表面的上方。
  5. 如申請專利範圍第4項所述之半導體裝置，更包含：複數個連接墊，形成於該封裝基底的上方，其中該些連接墊是排列成一向心性的圖形或行列。
  6. 如申請專利範圍第4項所述之半導體裝置，更包含：複數個佈線墊，嵌於該封裝基板中，其中該些佈線墊是排列成一向心性的圖形或行列。
  7. 一種墊結構的形成方法，包含：在一封裝基板中形成複數個第一墊，其中該些第一墊具有一第一細長形狀；在該些第一墊的上方形成複數個介層窗；在該些介層窗的上方形成複數個第二墊；其中，該些第二墊具有一第二細長形狀；以及該些第二墊是經由該些介層窗耦接於該些第一墊；以及 在該封裝基板的上方沉積一銲阻層，其中該些第二墊是在該銲阻層的一上表面的上方。
  8. 如申請專利範圍第7項所述之墊結構的形成方法，其中：該些第一墊是排列成行列或一向心性的圖形；以及該些第二墊是排列成一向心性的圖形或行列。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9396991B2 (en) 2014-08-25 2016-07-19 Globalfoundries Inc. Multilayered contact structure having nickel, copper, and nickel-iron layers
US20160064320A1 (en) * 2014-08-27 2016-03-03 Cisco Technology, Inc. Coupling of an interposer to a package substrate
US9748196B2 (en) * 2014-09-15 2017-08-29 Advanced Semiconductor Engineering, Inc. Semiconductor package structure including die and substrate electrically connected through conductive segments
EP3277065B1 (en) * 2015-03-27 2021-08-11 Kyocera Corporation Imaging component, and imaging module provided with same
US9893028B2 (en) 2015-12-28 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond structures and the methods of forming the same
US10014268B2 (en) * 2016-03-01 2018-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor chip, semiconductor device and manufacturing process for manufacturing the same
US10026691B2 (en) * 2016-06-13 2018-07-17 Intel Corporation Package substrate having noncircular interconnects
CN108573885B (zh) * 2017-03-07 2021-03-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US10950535B2 (en) 2017-05-09 2021-03-16 Unimicron Technology Corp. Package structure and method of manufacturing the same
US10714448B2 (en) * 2017-05-09 2020-07-14 Unimicron Technology Corp. Chip module with porous bonding layer and stacked structure with porous bonding layer
US10178755B2 (en) 2017-05-09 2019-01-08 Unimicron Technology Corp. Circuit board stacked structure and method for forming the same
US10685922B2 (en) 2017-05-09 2020-06-16 Unimicron Technology Corp. Package structure with structure reinforcing element and manufacturing method thereof
US10777496B2 (en) * 2017-10-06 2020-09-15 International Business Machines Corporation Chip packages with sintered interconnects formed out of pads
JP6701261B2 (ja) * 2018-05-08 2020-05-27 矢崎総業株式会社 筐体、電気接続箱及びワイヤハーネス
CN113517209A (zh) * 2020-04-10 2021-10-19 长鑫存储技术有限公司 半导体结构及其形成方法
KR20220155741A (ko) 2021-05-17 2022-11-24 삼성전자주식회사 반도체 패키지

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2867313B2 (ja) * 1993-12-10 1999-03-08 日本特殊陶業株式会社 セラミック基板
TW421860B (en) * 1997-09-09 2001-02-11 Hitachi Ltd Semiconductor device
JP4405024B2 (ja) * 2000-01-18 2010-01-27 株式会社ルネサステクノロジ 半導体装置
US7317165B2 (en) * 2003-06-24 2008-01-08 Ngk Spark Plug Co., Ltd. Intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, and structure having semiconductor element, intermediate substrate and substrate
US7057296B2 (en) * 2003-10-29 2006-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding pad structure
US7808115B2 (en) * 2004-05-03 2010-10-05 Broadcom Corporation Test circuit under pad
TWI290820B (en) * 2005-10-13 2007-12-01 Phoenix Prec Technology Corp Circuit board structure of integrated optoelectronic component
KR100987479B1 (ko) * 2005-12-19 2010-10-13 삼성전자주식회사 반도체 칩 및 이를 이용한 반도체 칩 패키지
US7830004B2 (en) * 2006-10-27 2010-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with base layers comprising alloy 42
JP5581060B2 (ja) * 2007-03-08 2014-08-27 センセオニクス，インコーポレーテッド 過酷な環境のための発光ダイオード
KR20080088321A (ko) 2007-03-29 2008-10-02 주식회사 하이닉스반도체 플립 칩 패키지
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
TW200906260A (en) * 2007-07-20 2009-02-01 Siliconware Precision Industries Co Ltd Circuit board structure and fabrication method thereof
KR100966336B1 (ko) 2008-04-07 2010-06-28 삼성전기주식회사 고밀도 회로기판 및 그 형성방법
KR101086964B1 (ko) 2009-06-09 2011-11-29 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법
KR20110061404A (ko) * 2009-12-01 2011-06-09 삼성전자주식회사 칩 실리콘 관통 비아와 패키지간 연결부를 포함하는 반도체 패키지들의 적층 구조 및 그 제조 방법
TW201135858A (en) * 2010-04-01 2011-10-16 Jung-Tang Huang Structure and method of forming pillar bumps with controllable shape and size
US20120098120A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package
JP5675443B2 (ja) * 2011-03-04 2015-02-25 新光電気工業株式会社 配線基板及び配線基板の製造方法
US8729699B2 (en) * 2011-10-18 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Connector structures of integrated circuits

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