TWI556394B - 半導體結構及其形成方法及半導體裝置 - Google Patents
半導體結構及其形成方法及半導體裝置 Download PDFInfo
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Description
本發明係有關於一種半導體結構及其形成方法,且特別是有關於一種內連線結構及其形成方法。
由於許多電子元件(例如:電晶體、二極體、電阻、電容等)的積體密度的持續進步,半導體工業也經歷了快速的成長。積體密度的改善最主要的部分在於元件寬度的不斷縮減,使得在給定區域內可積體更多元件。最近,隨著電子元件的寬度更加縮減,因此需要更小且更有創意的半導體晶粒封裝技術。
隨著半導體技術的發展,晶片尺度(chip-scale)或晶片寬度(chip-size)封裝半導體裝置出現了縮減半導體晶片的物理寬度的另一選擇。在晶片尺度封裝半導體裝置(chip-scale packaging based semiconductor device)中,封裝主要在晶粒上且利用各種的凸塊以提供接觸插塞,例如銅凸塊、焊料球、及/或其類似物。藉由晶片尺度封裝半導體裝置可達到更高的密度。
晶片尺度封裝半導體裝置可包括複數個焊料球,形成在半導體晶粒的複數個凸塊下金屬(under bump metallization;UBM)開口上。或者,可利用銅凸塊以電性連接
半導體裝置及外部電路。在半導體裝置的連接結構的鄰近區域可具有集中的應力。例如,層間介電層(inter-level dielectric layer)位於緊鄰電性連接結構之下。此外,層間介電層可由極低介電常數介電質(extreme low-k dielectric;ELK)材料所形成。因此,由電性連接結構所產生的應力可能導致極低介電常數介電質層在應力下破裂或脫層。
晶片尺度封裝技術具有一些優點。晶片尺度封裝的優點之一在於晶片尺度封裝技術可降低製程花費。晶片尺度封裝多晶片半導體裝置的另一優點為藉由使用在半導體裝置及印刷電路板之間夾置的凸塊可降低寄生損失(parasitic losses)。因此,晶片尺度封裝半導體裝置可達到寬度較小、花費少、提升性能、低消耗功率、及低熱量產升等優點。
本發明一實施例提供一種半導體結構,包括一第一鈍化層(first passivation layer),形成在一基板上;一第二鈍化層,形在在該第一鈍化層上,其中該第二鈍化層包括具有一第一寬度的一第一開口;一接合墊,埋置在該第一鈍化層及該第二鈍化層中;一保護層,形成在該第二鈍化層上,該保護層包括具有一第二寬度的一第二開口,其中該第二寬度大於該第一寬度;以及一連接部,形成在該接合墊上。
本發明另一實施例提供一種半導體裝置,包括:一基板,包括矽;一第一金屬層,形成在該基板上;一第一介電層,形成在該第一金屬層上;一第二金屬層,形成在該第一介電層上;一第一鈍化層,形成在該第二金屬層上;一第二鈍
化層,形成在該第一鈍化層上;其中具有一第一寬度的一第一開口形成在該第二鈍化層中;一接合墊,埋置在該第一鈍化層及該第二鈍化層中;一保護層,形成在該第二鈍化層上,該第二鈍化層包括具有一第二寬度的一第二開口,其中該第二寬度大於該第一寬度;以及一連接部,形成在該接合墊上。
本發明又一實施例提供一種半導體結構的形成方法,包括:在一基板上沉積一第一鈍化層;在該第一鈍化層上沉積一第二鈍化層;在該第二鈍化層中形成具有一第一寬度的一第一開口;在該第一鈍化層及該第二鈍化層中埋置一接合墊;在該第二鈍化層上沉積一保護層;在該保護層中形成具有一第二寬度的一第二開口,其中該第二寬度大於該第一寬度;以及在該接合墊上設置一連接部,其中該連接部包括:一第一部分,被該第二鈍化層圍繞,其中該第一部分具有一第一水平寬度;以及一第二部分,被該保護層圍繞,其中該第二部分具有一第二水平寬度,其中該第二水平寬度大於該第一水平寬度。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
100‧‧‧半導體裝置
102‧‧‧基板
150‧‧‧階梯狀部分
104‧‧‧層間介電層
106‧‧‧底部金屬化層
108‧‧‧頂部金屬化層
126‧‧‧第一金屬線
128‧‧‧第二金屬線
110‧‧‧介電層
124‧‧‧頂部金屬連接部
122‧‧‧連接部
112‧‧‧第一鈍化層
116‧‧‧接合墊
114‧‧‧第二鈍化層
118‧‧‧聚合物層
402‧‧‧第一部分
404‧‧‧第二部分
406‧‧‧第三部分
第1圖顯示在本發明一些實施例中的內連線結構的剖面圖。
第2圖顯示在本發明一些實施例中另一內連線結構的剖面
圖。
第3圖顯示在本發明一些實施例中另一內連線結構的剖面圖。
第4圖顯示在本發明一些實施例中,在第1圖中的半導體裝置的一部分的剖面圖。
第5圖顯示在本發明一些實施例中,第2圖所示半導體裝置的一部分的剖面圖。
第6圖顯示在本發明一些實施例中,第3圖所示半導體裝置的一部分的剖面圖。
因本發明之不同特徵而提供數個不同的實施例。本發明中特定的元件及安排係為了簡化,但本發明並不以這些實施例為限。舉例而言,於第二元件上形成第一元件的描述可包括第一元件與第二元件直接接觸的實施例,亦包括具有額外的元件形成在第一元件與第二元件之間、使得第一元件與第二元件並未直接接觸的實施例。此外,為簡明起見,本發明在不同例子中以重複的元件符號及/或字母表示,但不代表所述各實施例及/或結構間具有特定的關係。
在本發明一些實施例中,敘述一種內連線結構(interconnection structure),包括具有階梯狀部分(ladder shaped portion)的凸塊。然而,在一些實施例中也可使用不同的內連線結構及凸塊。以下將配合圖示解釋本發明不同的實施例。
第1圖顯示在本發明一些實施例中的內連線結構的剖面圖。半導體裝置100包括基板102及形成在基板102上的
內連線結構。內連線結構包括階梯狀部分150。此階梯狀部分150有助於降低在極低介電常數(extreme low-k;ELK)層上的應力。以下將配合第4圖詳細敘述階梯狀部分150。
可利用矽形成基板102,但也可用其他第III族、第IV族、及/或第V族元素形成,例如矽、鍺、鎵、砷、及前述之組合、及/或其類似物。也可利用絕緣層上矽(silicon-on-insulator;SOI)形成基板102。SOI基板可包括在絕緣層(例如:掩埋氧化物(buried oxide)等)上形成的半導體材料層(例如:矽、鍺等),其中絕緣層形成在矽基板上。此外,也可利用其他的基板,包括多層基板、梯度基板(gradient substrates)、混成方向基板(hybrid orientation substrates)等。基板102可更包括一些電子電路(圖中未顯示)。在基板102上所形成的電子電路可為適用於任何特定應用的電路種類。
在一實施例中,電子電路可包括一些n型金氧半(NMOS)及/或p型金氧半(PMOS)裝置,例如電晶體、電容、電阻、二極體、光二極體、熔絲(fuse)等。電子電路可內連線以進行一或多個功能。其功能可包括記憶體結構、處理結構、感應器、放大器、功率分佈(power distribution)、輸入/輸出電路等。本發明所屬技術領域中具有通常知識者應可了解上述例子僅為舉例說明之用,本發明之精神與範疇並非以此為限。
在基板102的頂部上形成層間介電層104。可利用低介電常數介電材料形成層間介電層104,例如:氧化矽。可利用任何適合的方法形成層間介電層104,例如旋塗、化學氣相沉積(CVD)、電漿強化化學氣相沉積(PECVD)等。本發明所
屬技術領域中具有通常知識者應可了解層間介電層104可更包括複數個介電層。
在層間介電層104上形成底部金屬化層(bottom metallization layer)106及頂部金屬化層(top metallization layer)108。如第1圖所示,底部金屬化層106包括第一金屬線126。類似的,頂部金屬化層108包括第二金屬線128。以金屬材料形成金屬線126及128,例如銅、銅合金等。可利用任何適合的技術形成金屬化層106及108,例如沉積、鑲嵌等。一般而言,利用一或多個金屬間介電層及相對應的金屬化層,以使基板102中的電路彼此內連線,以形成功能性電路,並更進一步提供外部電性連接。
應注意雖然在第1圖中顯示底部金屬化層106及頂部金屬化層108,任何所屬技術領域中具有通常知識者應可了解在底部金屬化層106及頂部金屬化層108之間可形成一或多個金屬間介電層(圖中未顯示)及相對應的金屬化層(圖中未顯示)。特別是在底部金屬化層106及頂部金屬化層108之間的層狀物可為交替的介電層(如:極低介電常數介電材料)及導電層(如:銅)。
在頂部金屬化層108上形成介電層110。如第1圖所示,在介電層110中埋置頂部金屬連接部(top metal connector)124。特別是,頂部金屬連接部在金屬線128及半導體裝置的電性連接結構之間提供導電通道。可利用金屬性材料形成頂部金屬連接部124,例如銅、銅合金、鋁、銀、金、及前述之組合。可利用適合的技術形成頂部金屬連接部124,例
如:化學氣相沉積。或者,可利用濺鍍、電鍍等方法形成頂部金屬連接部124。
在介電層110上形成第一鈍化層(first passivation layer)112。在一實施例中,利用非有機材料(non-organic material)形成第一鈍化層112,例如未摻雜矽酸鹽玻璃(un-doped silicate glass)、氮化矽、氧化矽等。或者,可利用低介電常數介電質形成第一鈍化層112,例如碳摻雜氧化物等。此外,可利用極低介電常數介電質形成第一鈍化層112,如孔洞碳摻雜二氧化矽(porous carbon doped silicon dioxide)。可利用任何適合的技術形成第一鈍化層112,例如化學氣相沉積等。如第1圖所示,可在第一鈍化層112中形成開口。開口可用以容納接合墊116(詳述如下)。
在第一鈍化層的頂部上形成第二鈍化層114。第二鈍化層114可類似於第一鈍化層112,因此在此不再複述其細節。如第1圖所示,在第二鈍化層及第一鈍化層的開口中形成接合墊116。在一實施例中,可利用鋁形成接合墊116。為了簡化的緣故,在以下說明中,接合墊116也可稱為鋁墊116。
鋁墊116可被第一鈍化層112及第二鈍化層114圍住(enclosed)。特別是,鋁墊116的底部部分埋置於第一鈍化層112中,而鋁墊116的頂部部分埋置於第二鈍化層114中。第一鈍化層112及第二鈍化層114重疊並封閉鋁墊116的邊緣,藉此避免鋁墊116邊緣的腐蝕,因而可提升電性穩定性。此外,第一鈍化層112及第二鈍化層114可降低半導體裝置的漏電流。
在第二鈍化層114的頂部上形成聚合物層118。利
用聚合物材料形成聚合物層118,例如:環氧樹脂、聚亞醯胺等。特別是,聚合物層118可包括光可定義聚亞醯胺材料(photo-definable polyimide material),例如:HD4104。為了簡化的緣故,在以下敘述中,聚合物層118也可稱為聚亞醯胺層118。可利用任何適合的方法形成聚亞醯胺層118,例如旋塗等。若接合墊重新設置於另一新的位置,則可在半導體裝置100中形成再分部層(redistribution layer,圖中未顯示)。再分部層提供金屬線(例如:金屬線128)及再分部接合墊之間的導電路徑。再分部層的使用為所屬技術領域中具有通常知識者所熟知,故在此不詳述。
圖案化聚亞醯胺層118以形成複數個開口。此外,在開口的頂部上形成多種凸塊下金屬(under bump metal;UBM)結構。使用凸塊下金屬結構以連接鋁墊(例如:鋁墊116)及多種輸入及輸出端點(例如:連接部122)。可利用任何適合的技術形成凸塊下金屬結構,例如電鍍。或者也可依照所需使用的材料利用其他製程,例如:濺鍍、蒸鍍(evaporation)、電漿強化化學氣相沉積(PECVD)等。
在一些實施例中,連接部122可為銅凸塊。銅凸塊的高度可為約45μm。可利用各種半導體封裝技術來形成銅凸塊122,例如:濺鍍、電鍍、光微影等。已知為了確保在銅凸塊及接合墊116之間的黏著性及電性連續,可在銅凸塊122及接合墊116之間形成額外的層狀物,包括阻障層、黏著層、及種子層(圖中未顯示)。
第2圖顯示在本發明一些實施例中另一內連線結
構的剖面圖。第2圖的結構類似於第1圖,然而在第2圖中連接部122為梯形而非矩形。第2圖中的連接部122通常稱為階梯凸塊(ladder bump)。
第3圖顯示在本發明一些實施例中另一內連線結構的剖面圖。第3圖的結構類似於第1圖,然而在第3圖中連接部122為焊料球。連接部122形成在凸塊下金屬結構的頂部上(圖中未顯示)。在一些實施例中,連接部122可為焊料球。可用任何適合的材料形成焊料球。在一些實施例中,焊料球可包括SAC405。SAC405包括95.5%的錫、4.0%的銀、以及0.5%的銅。
應了解第1圖、第2圖、第3圖的連接部122僅為例子。本領域中具有通常知識者應可知悉可應用多種半導體連接部。
第4圖顯示在本發明一些實施例中,在第1圖中的半導體裝置的一部分的剖面圖。為了簡化的緣故,在第4圖中僅顯示第1圖的半導體裝置100中一些相關的部分。
如第4圖所示,連接部122可包括三個部分402、404、及406。第一部分402被第二鈍化層114所圍繞。亦即,第一部分402位於第二鈍化層114的開口中。類似的,第二部分404被聚亞醯胺層118所圍繞。第二部分404位於聚亞醯胺層118的開口中。第三部分406突出自聚亞醯胺層118的頂表面上。應注意第一部分402及第二部分404形成第1圖所示的階梯狀部分150。
如第4圖所示,第三部分406的寬度(dimension)大於第二部分的寬度。相似的,第二部分404的寬度大於第一部
分的寬度。為了更清楚的顯示寬度的差異,在第二鈍化層118中的開口的寬度定義為PASS2。在聚亞醯胺層118中的開口的寬度定義為PIO。
應注意的是,第4圖僅顯示半導體裝置100的剖面圖。第二鈍化層114及聚亞醯胺層118的開口由上視圖來看可具有多種形狀(圖中未顯示)。第二鈍化層114及聚亞醯胺層118的開口的形狀可包括多角形、圓形、橢圓形、瘦長形、前述之組合、及/或其類似形狀。
在一些實施例中,為了降低電性連接結構下的層狀物的應力,特別是極低介電常數介電層(ELK layer)上的應力,上述寬度有以下限制:PASS2<PIO
上述限制的優點之一在於寬度限制有助於降低極低介電常數介電層上的應力。極低介電常數介電層上的應力降低有助於避免一些製造上的失敗,如脫層及/或其類似情況的發生。
在一些實施例中,藉由使用第4圖中所是內連線結構,在極低介電常數介電層上的應力可降低30%。因此,可改善半導體裝置100的晶片封裝積體(chip package integration;CPI)。
第5圖顯示在本發明一些實施例中,第2圖所示半導體裝置的一部分的剖面圖。在第5圖中的開口及其寬度類似於第4圖中的開口及其寬度,但在第4圖中的矩形連接部122被梯形連接部取代。為了避免重複,其他部分在此不詳述。
第6圖顯示在本發明一些實施例中,第3圖所示半導體裝置的一部分的剖面圖。在第6圖中的開口及其寬度類似於第4圖中的開口及其寬度,但在第4圖中的銅連接部122被焊料球取代。為了避免重複,其他部分在此不詳述。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體裝置
102‧‧‧基板
150‧‧‧階梯狀部分
104‧‧‧層間介電層
106‧‧‧底部金屬化層
108‧‧‧頂部金屬化層
126‧‧‧第一金屬線
128‧‧‧第二金屬線
110‧‧‧介電層
124‧‧‧頂部金屬連接部
112‧‧‧第一鈍化層
116‧‧‧接合墊
114‧‧‧第二鈍化層
118‧‧‧聚合物層
122‧‧‧連接部
Claims (8)
- 一種半導體結構,包括:一第一鈍化層(first passivation layer),形成在一基板上,且該第一鈍化層係極低介電常數介電質;一第二鈍化層,形在在該第一鈍化層上,其中該第二鈍化層包括具有一第一寬度的一第一開口,且該第二鈍化層係非有機材料;一T型接合墊,埋置在該第一鈍化層及該第二鈍化層中,其中該T型接合墊具有一垂直部份與一水平部份,該垂直部份埋置在該第一鈍化層中,且該第二鈍化層覆蓋該水平部份的部份上表面;一保護層,形成在該第二鈍化層上,該保護層包括具有一第二寬度的一第二開口,且該保護層係光可定義聚亞醯胺材料,其中該第二寬度大於該第一寬度;以及一連接部,形成在該接合墊上。
- 如申請專利範圍第1項所述之半導體結構,其中該接合墊包括鋁,且該連接部為一焊料層。
- 如申請專利範圍第1項所述之半導體結構,其中該連接部包括一銅凸塊,且其中該連接部的形狀為矩形或梯形。
- 一種半導體裝置,包括:一基板;一第一金屬層,形成在該基板上;一第一介電層,形成在該第一金屬層上;一第二金屬層,形成在該第一介電層上; 一第一鈍化層,形成在該第二金屬層上,且該第一鈍化層係極低介電常數介電質;一第二鈍化層,形成在該第一鈍化層上,且該第二鈍化層係非有機材料;其中具有一第一寬度的一第一開口形成在該第二鈍化層中;一T型接合墊,埋置在該第一鈍化層及該第二鈍化層中,其中該T型接合墊具有一垂直部份與一水平部份,該垂直部份埋置在該第一鈍化層中,且該第二鈍化層覆蓋該水平部份的部份上表面;一保護層,形成在該第二鈍化層上,且該保護層係光可定義聚亞醯胺材料,該第二鈍化層包括具有一第二寬度的一第二開口,其中該第二寬度大於該第一寬度;以及一連接部,形成在該接合墊上。
- 如申請專利範圍第4項所述之半導體裝置,其中該連接部包括:一第一部分,被該第二鈍化層所圍繞,其中該第一部分在一第一水平寬度;一第二部分,被該保護層所圍繞,其中該第二部分在一第二水平寬度;以及一第三部分,由該保護層的一頂部表面突出,其中該第三部分在一第三水平寬度;其中,該第三水平寬度大於該第二水平寬度;以及該第二水平寬度大於該第一水平寬度。
- 一種半導體結構的形成方法,包括: 在一基板上沉積一第一鈍化層,且該第一鈍化層係極低介電常數介電質;在該第一鈍化層上沉積一第二鈍化層,且該第二鈍化層係非有機材料;在該第二鈍化層中形成具有一第一寬度的一第一開口;在該第一鈍化層及該第二鈍化層中埋置一T型接合墊,其中該T型接合墊具有一垂直部份與一水平部份,該垂直部份埋置在該第一鈍化層中,且該第二鈍化層覆蓋該水平部份的部份上表面;在該第二鈍化層上沉積一保護層,且該保護層係光可定義聚亞醯胺材料;在該保護層中形成具有一第二寬度的一第二開口,其中該第二寬度大於該第一寬度;以及在該接合墊上設置一連接部,其中該連接部包括:一第一部分,被該第二鈍化層圍繞,其中該第一部分具有一第一水平寬度;以及一第二部分,被該保護層圍繞,其中該第二部分具有一第二水平寬度,其中該第二水平寬度大於該第一水平寬度。
- 如申請專利範圍第6項所述之半導體結構的形成方法,更包括:在該接合墊上形成一階梯狀連接部,其中該階梯狀連接部以一導電材料所形成。
- 如申請專利範圍第6項所述之半導體結構的形成方法,更包括: 在該連接部及該接合墊之間形成一凸塊下金屬結構。
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TW201417234A (zh) | 2014-05-01 |
US9673125B2 (en) | 2017-06-06 |
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