TWI490993B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI490993B
TWI490993B TW101129469A TW101129469A TWI490993B TW I490993 B TWI490993 B TW I490993B TW 101129469 A TW101129469 A TW 101129469A TW 101129469 A TW101129469 A TW 101129469A TW I490993 B TWI490993 B TW I490993B
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TW
Taiwan
Prior art keywords
layer
bump
passivation
protective structure
protective
Prior art date
Application number
TW101129469A
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English (en)
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TW201316471A (zh
Inventor
Chen Hua Yu
Hung Pin Chang
An Jhih Su
Tsang Jiuh Wu
Wen Chih Chiou
Shin Puu Jeng
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Taiwan Semiconductor Mfg Co Ltd
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Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201316471A publication Critical patent/TW201316471A/zh
Application granted granted Critical
Publication of TWI490993B publication Critical patent/TWI490993B/zh

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    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
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Description

半導體裝置
本發明係有關於一半導體裝置,特別是有關於一種半導體裝置,其包括一具有保護結構的凸塊。
現代積體電路(IC)是由百萬個主動裝置(例如,電晶體及電容)所組成。這些裝置一開始的時後彼此隔離,但在後來內連在一起而形成功能電路。典型的內連結構包括橫向內連接(例如金屬線(接線))以及垂值內連接(例如介層窗(via)或接觸窗(contact))。內連線取決於現代積體電路的效能及密度限制。在內連結構上方,形成了接合墊且露出各自的晶片表面。透過接合墊將晶片連接至封裝基底或另一晶片而構成電性連接。接合墊可使用於打線接合(wire bonding)或覆晶接合(flip-chip bonding)。覆晶封裝利用凸塊來建立晶片的輸入/輸出(I/O)接墊與基底或封裝的導線架(lead frame)之間的電性接觸。在結構上,凸塊實際上包含凸塊本身及位於凸塊與輸入/輸出(I/O)接墊之間的凸塊下方金屬(under bump metallurgy,UBM)。焊球可放置於UBM上方。
現今晶圓級晶片尺寸封裝(wafer level chip scale packaging,WLCSP)因成本低且製程相對簡單而被廣泛地使用。在一典型的WLCSP中,後鈍化護層內連(post-passivation interconnect,PPI)線,例如重佈線(redistribution line,RDL),形成於鈍化護層 (passivation)上,接著在形成高分子層及凸塊。WLCSP 通常接合置一印刷電路板(printed circuited circuit,PCB)。為了能夠具有將接合至PCB的缺陷WLCSP取代為良好WLCSP的選擇性,WLCSP與PCB之間並沒有填入底膠(underfill)材料。然而,上述配置因晶片與PCB之間熱不匹配(thermal mismatch)(其會在熱循環或墜落測試期間讓焊料接點產生裂縫),而限制了現行WLCSP技術的晶片尺寸。現時另一考量點在於PPI線上方的鈍化護層結構所引起的應力,其影響了裝置效能及可靠度。
在本發明一實施例中,一種半導體裝置包括:一半導體基底;一鈍化護層,位於半導體基底上;一後鈍化護層內連線,位於鈍化護層上;一保護結構,位於鈍化護層及後鈍化護層內連線上,其中保護結構具有一開口,以至少露出一部分的後鈍化護層內連線;以及一凸塊結構,形成於保護結構內,且透過保護結構的開口而電性連接至後鈍化護層內連線。保護結構包括:一高分子層、形成於高分子層下方的一第一介電層以及形成於鈍化護層上的一第二介電層。
在本發明另一實施例中,一種半導體裝置包括:一半導體基底;一鈍化護層,位於半導體基底上;一後鈍化護層內連線,位於鈍化護層上;一保護結構,位於鈍化護層及後鈍化護層內連線上,其中保護結構具有一開口,以至少露出一部分的後鈍化護層內連線;以及一凸 塊結構,形成於保護結構內,且透過保護結構的開口而電性連接至後鈍化護層內連線。保護結構包括:一高分子層以及圍繞該高分子層的一介電層。
以下說明本發明實施例之製作與使用。然而,可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。以下實施例是關於適用於半導體裝置的凸塊結構的使用。如以下所述,本文實施例揭示利用凸塊結構將一基底貼附至另一基底,其中每一基底可為晶片、晶圓、轉接(interposer)基底、印刷電路板或封裝基底等等,藉以提供晶片對晶片、晶圓對晶片、晶圓對晶圓、晶片或晶圓對轉接基底或印刷電路板或封裝基底等接合。全文中不同的實施例及圖式中,相同的部間隙使用相同的標號。
以下配合圖式說明詳細的實施例。如果可能的話,圖式及說明中使用相同的標號來表示相同或相似的部件。在圖式中,為了清楚及方便性,而擴大形狀及厚度。以下說明將特別針對本發明實施例之裝置或是其中元件的形成部分。可以理解的是未特別繪示或說明的元件可具有各種不同的型式。本說明書全文中所提及關於”一實施例”的意思是指有關於本實施例中所提及特定的特徵(feature)、結構、或特色係包含於本發明的至少一實施例中。因此,本說明書全文中各處所出現的”在一實 施例中”用語所指的並不全然表示為相同的實施例。再者,特定的特徵、結構、或特色能以任何適當方式而與一或多個實施例作結合。可以理解的是以下的圖式並未依照比例繪示,而僅僅提供說明之用。
第1圖係繪示出根據本發明一實施例之具有保護結構位於PPI線上方的凸塊剖面示意圖。
請參照第1圖,其繪示出一部分的裝置基底100,裝置基底100具有電路形成於內及/或形成於上。裝置基底100可包括一半導體基底,例如一矽晶圓、一矽晶片、一半導體上覆矽(semiconductor-on-insulator,SOI)基底或任何包括半導體材料的結構。內連接並執行一或多種功能的半導體裝置,例如電晶體、電容、電阻、二極體、光電二極體或熔絲等,形成於半導體基底的表面。內連結構可包括金屬線及形成於內層介電(inter-layer dielectric,ILD)層內且電性耦接至半導體裝置的介層窗(via),且形成於半導體基底100上。在一些實施例中,基底通孔電極(through-substrate via,TSV)形成於半導體基底100內,且電性連接至內連結構。金屬接墊可圖案化於位在上層內層介電層上的金屬化層內,以電性連接至半導體裝置,例如,透過下方的內連結構。
一鈍化護層102形成於裝置基底100上並圖案化,以形成露出下方金屬接墊的一開口(未繪示)。在一實施例中,鈍化護層102由一無機材料所構成,其可擇自於未摻雜的矽玻璃(un-doped silicate glass,USG)、氮化矽、氮氧化矽、氧化矽及其組合。在另一實施例中, 鈍化護層102由高分子層所構成,例如環氧化物、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)或聚苯噁唑(polybenzoxazole,PBO)等,然而也可使用其他相對軟性有機介電材料。
再者,一後鈍化護層內連(PPI)線104形成於鈍化護層102上並圖案化。後鈍化護層內連線104可填入鈍化護層102的開口內,以電性連接至下方的金屬接墊。舉例來說,後鈍化護層內連線104的製做包括沉積一金屬材料、使用遮罩及微影製程、進行蝕刻製程及去除遮罩。後鈍化護層內連線104可由一導電材料所構成,其包括但不侷限於鋁、銅合金、鎳或其他活動態金屬(mobile metal)材料。後鈍化護層內連線104的沉積方法可包括電鍍、無電電鍍、濺鍍及化學氣相沉積(chemical vapor deposition,CVD)等等。後鈍化護層內連線104將金屬接墊連接至後續形成的凸塊特徵部件。後鈍化護層內連線104也可作為電源線、重佈線(redistribution line,RDL)、電感、電容或其他被動元件。在一實施例中,後鈍化護層內連線104具有一厚度小於30微米(μm),例如在2微米至25微米的範圍。
接著,一保護結構106A形成於後鈍化護層內連線104上並圖案化,以形成一開口108A而露出一部分的後鈍化護層內連線104。後鈍化護層內連線104的露出部分為一接合墊(landing pad)區,其上接著會形成凸塊結構114A。在一實施例中,凸塊結構114A包括形成於開口108內的一凸塊下方金屬(under-bump metallization, UBM)層110及一導電凸塊112。凸塊下方金屬層110順應性形成於開口108的側壁及底部。凸塊下方金屬層110更包括位於保護結構106A上方的部分,以形成一突出部110a。導電凸塊112形成於凸塊下方金屬層110上,以填入開口108A,其突出於保護結構106A的上表面。接著切割裝置基底100並與位在封裝基底或其他晶片的接墊上的焊球或銅柱(post)封裝至一封裝基底或另一晶片上。
在一實施例中,凸塊下方金屬層110包括一擴散阻障層及/或一晶種(seed)層。擴散阻障層可由氮化鉭所構成,然而也可使用其他材料,例如氮化鈦、鉭或鈦等等。晶種層可為一銅晶種層,且形成於擴散阻障層上。銅晶種層也可由銅合金所構成,其包括銀、鉻、鎳、錫、金或其組合。在一實施例中,凸塊下方金屬層110包括由鈦所構成的擴散阻障層及銅所構成的晶種層。導電凸塊112可包括一金屬層、一焊料層或其組合。導電凸塊112內的金屬層可包括一銅層、一銅合金層、一鎳層、一鎳合金層或其組合。導電凸塊112內的焊料層可包括無鉛預焊(lead-free pre-solder)層、SnAg或一焊料(其包括由錫、鉛、銀、銅、鎳、鉍或其組合所構成的合金)。
形成於後鈍化護層內連線104上且圍繞凸塊結構114A的保護結構106A構成應粒緩衝的鈍化保護結構,並消除高分子材料相關釋氣(out-gassing)問題。在一實施例中,保護結構106A包括一高分子層32,夾設於第一保護層30I與第二保護層30II之間。高分子層32具有 一厚度在30微米至200微米的範圍。因為具有很厚的厚度,高分子層32可作為有效的應力緩衝。高分子層32可由高分子材料所構成,例如環氧化物、聚醯亞胺、苯並環丁烯(BCB)或聚苯噁唑(PBO)等,然而也可使用其他相對軟性有機介電材料。在一實施例中,高分子層32為一聚醯亞胺層。高分子層32為軟性且容易形成數十微米的厚度,因而能具有降低各個基底的應力的功能。
高分子層32的製做需要塗佈、固化及去除殘留物(descum)等步驟。然而,不適當或不完全固化的高分子會造成腐蝕氣體射出或釋氣問題,引發物理性/電性可靠度問題。為了消除高分子層32的相關釋氣問題,高分子層32下方的第一保護層30I夾設於後鈍化護層內連線104與高分子層32之間,且夾設於凸塊結構114A的底部與高分子層32之間,因而能夠阻擋高分子層32釋出的水氣。同樣地,形成於高分子層32上的第二保護層32II夾設於凸塊結構114A的頂部與高分子層32之間,因而能夠遮蔽高分子層32釋出的水氣,以避免凸塊黏著問題以及封裝部件在製造期間或之後發生失效。在一實施例中,第一保護層30I可由一介電材料所構成,其包括氮化矽、碳化矽、氮碳化矽、碳氧化矽、四乙基矽酸鹽(tetra-ethyl-ortho-silicate,TEOS)氧化物、氧化矽、其多層結構及/或其組合,且利用電漿輔助化學氣相沉積(plasma enhanced CVD,PECVD)技術或高密度電漿化學氣相沉積(high density plasma CVD,HDPCVD)等而形成。在一實施例中,第二保護層30II可由一介電材料 所構成,其包括氮化矽、碳化矽、氮碳化矽、碳氧化矽、四乙基矽酸鹽(TEOS)氧化物、氧化矽、其多層結構及/或其組合,且利用電漿輔助化學氣相沉積(PECVD)技術或高密度電漿化學氣相沉積(HDPCVD)等而形成。在一實施例中,第一保護層30I具有一厚度小於2微米,例如在0.2微米至1微米的範圍。在另一實施例中,第二保護層30II具有一厚度小於2微米,例如在0.11微米至0.5微米的範圍。
第1圖所示的實施例採用具有高分子層32的保護結構106A來形成用於後鈍化護層內連線104及凸塊結構114A的應力緩衝結構,且採用具有第一及第二保護層30I及30II的保護結構106A來阻擋及遮蔽高分子層32所釋出的水氣,以消除釋氣問題。此改善了凸塊結構114A及後鈍化護層內連線104的物理性/電性效能及可靠度。再者,保護結構106A圍繞且貼附於後鈍化護層內連線104及凸塊結構114A,因而能提供塊結構114A較佳的機械強度,且可實施於較大的金屬對金屬接觸面積。
第2圖係繪示出根據本發明另一實施例之保護結構剖面示意圖,其中相同於第1圖的部件係使用相同的標號。特別的是實施例中的結構、材料及厚度實質上相同於第1圖所示的實施例。請參照第2圖,另一保護結構106B包括完全被保護層30隔絕並與凸塊結構114A及後鈍化護層內連線104隔開的高分子層32。在一實施例中,保護層30包括形成於鈍化護層102上的第一部30a、延伸至後鈍化護層內連線104側壁及周圍邊緣的第二部 30b、覆蓋高分子層32外側壁的第三部30c、形成於凸塊結構114A側壁與高分子層32之間的第四部30d以及形成於高分子層32上方的第五部30e。因此,高分子層32被保護層30所隔絕。
第3圖係繪示出根據本發明另一實施例之保護結構剖面示意圖,其中相同於第1圖的部件係使用相同的標號。特別的是實施例中的結構、材料及厚度實質上相同於第1圖所示的實施例。請參照第3圖,另一凸塊結構114B形成於一開口108B內,其圖案化於保護結構106A內且穿過保護結構106A。開口108B具有一主開口109a露出後鈍化護層內連線104的上表面,且具有一周圍開口109b露出後鈍化護層內連線104的側壁以及鄰近於後鈍化護層內連線104的鈍化護層102。因此,相較於第1圖的凸塊金屬下方金屬層,凸塊金屬下方金屬層110順應性形成於開口108B內更包括一延伸部110b,位於後鈍化護層內連線104露出的側壁以及鈍化護層102的露出表面。再者,形成於開口108B內的導電凸塊112更包括一延伸部112a,填入周圍開口109b並圍繞後鈍化護層內連線104的側壁。
第4圖係繪示出根據本發明另一實施例之保護結構剖面示意圖,其中相同於第1及3圖的部件係使用相同的標號。特別的是實施例中的結構、材料及厚度實質上相同於第1及3圖所示的實施例。請參照第4圖,另一保護結構106B包括完全被保護層30隔絕並與凸塊結構114B及後鈍化護層內連線104隔開的高分子層32。
第5至9圖係繪示出根據第1圖實施例之半導體裝置中具有保護結構106A的凸塊結構114A製造方法剖面示意圖,其中相同於第1圖的部件係使用相同的標號。
請參照第5圖,其繪示出具有電路12形成於半導體基底10內及/或其上方的裝置基底100局部的剖面示意圖。半導體基底10可包括,例如,矽塊材(bulk)、摻雜或未摻雜的絕緣層覆半導體(SOI)基底或是SOI基底的主動層。一般而言,SOI基底包括形成於絕緣層上的一層半導體材料,例如矽。絕緣層可為埋入式氧化層(buried oxide,BOX)層或是氧化矽層。絕緣層位於一基底上,通常為矽基底或玻璃基底。也可使用其他基底,例如多層或漸變(gradient)基底。形成於半導體基底10上的電路12可為適用於特定應用的任何種類的電路。在一實施例中,電路12包括形成於半導體基底10上的電子裝置,其上具有一或多個介電層。金屬層可形成於介電層之間,以作為電子裝置之間電子訊號佈線。電子裝置也可形成於一或多個介電層內。舉例來說,電路12可包括不同的N型金屬氧化物半導體(NMOS)及/或P型金屬氧化物半導體(PMOS)裝置(例如,電晶體)、電容、電阻、二極體、光電二極體及熔絲等等且內連接以進行一或多種功能。上述功能包括記憶體結構、處理器結構、感測器、放大器、電源分配器(power distribution)或輸入/輸出電路等。任何所屬技術領域中具有通常知識者可理解上述僅為範例說明,用以進一步解釋實施例的應用,且未有限定本發明之意。可視特定應用的情況使用 其他裝置。
請再參照第5圖,一內層介電層14位於電路12上。內層介電層14可由低介電常數(low-K)材料,例如磷矽玻璃(phosphosilicate glass,PSG)、硼磷矽玻璃(boro-phosphosilicate glass,BPSG)、氟矽玻璃(fluorinated silicate glass,FSG)、SiOx Cy 、旋塗玻璃(spin-on glass)、旋塗高分子、碳化矽材料、其化合物、其複合物及其組合等所構成,且透過任何適當的方法而形成,例如旋塗法、化學氣相沉積(CVD)及電漿輔助化學氣相沉積(PECVD)。需注意的是內層介電層14可包括複數個介電層。接觸窗(未繪示)可穿過內層介電層14以提供與電路12的電性接觸。接觸窗可由一或多層的TaN、Ta、TiN、Ti、CoW、銅、鎢、鋁、銀或其組合等所構成。
一或多個金屬層間介電(inter-metal dielectric,IMD)層16及金屬化層形成於內層介電層14上。一般而言,一或多個金屬層間介電層16及金屬化層(例如,金屬線18及介層窗19)使用於將電路12彼此內連接,並提供外部電性連接。金屬層間介電層16可由低介電常數材料所構成,例如由電漿輔助化學氣相沉積(PECVD)或高密度電漿化學氣相沉積(HDPCVD)等所形成的氟矽玻璃(FSG),且可包括居中的蝕刻終止層。需注意的是一或多個蝕刻終止層(未繪示)可位於相鄰的介電層(例如,內層介電層14及金屬層間介電層16)之間。一般而言,蝕刻終止層提供蝕刻製程形成介層窗(via)及/或接觸窗(contact)時的停止機制。蝕刻終止層由具有與相 鄰層(如,下方半導體基底10、上方的內層介電層14及上方的金屬層間介電層16)間不同蝕刻選擇比的介電材料所構成。在一實施例中,蝕刻終止層可由透過化學氣相沉積(CVD)或電漿輔助化學氣相沉積(PECVD)而形成的SiN、SiCN、SiCO、CN或其組合等所構成。金屬化層可由銅或銅合金所構成。然而,也可由其他金屬所構成。任何所屬技術領域中具有通常知識者可理解金屬化層的製做細節。再者,金屬化層包括上金屬層20形成且圖案化於頂層金屬層間介電層16T的內部或上方,以提供外部電性連接並保護下方膜層受到各種環境汙染。頂層金屬層間介電層16T可由介電材料所構成,例如氮化矽、氧化矽或未摻雜矽玻璃等。在後續圖式中並未繪示半導體基底10、電路12、內層介電層14及金屬層間介電層16及金屬化層(金屬線18及介層窗19)。上金屬層20可作為頂層金屬層間介電層16T上方的上金屬化層的一部分。之後,形成一導電接墊22並圖案化,以與上金屬層20接觸或透過介層窗而電性耦接至上金屬層20。導電接墊22可由鋁、鋁銅、鋁合金、銅或銅合金等所構成。
請參照第5圖,形成一或多個鈍化護層(例如第一及第二鈍化護膜24及26)並圖案化,以形成鈍化護層102,其露出一部分的導電接墊22。在一實施例中,第一鈍化護膜24形成於頂層金屬層間介電層16T上並圖案化,以形成露出一部分導電接墊22的開口。接著第二頓化護膜26形成於第一鈍化護膜24上並圖案化,以形成 相對較大的開口,其露出導電接墊22中心部分。
第一及第二鈍化護膜24及26可由介電材料所構成,例如未摻雜的矽玻璃(USG)、氮化矽、氧化矽、氮氧化矽或無孔材料等,且可由適當方法來製做,例如化學氣相沉積(CVD)或物理氣相沉積(PVD)等。第一及第二鈍化護膜24及26可為一單層或疊層。任何所屬技術領域中具有通常知識者可理解此處僅以單層的導電接墊及鈍化物層作為範例說明。在其他實施例中,也可包括任何數量的導電層及/或鈍化護層。
之後,在鈍化護層102上形成後鈍化護層內連線104,並圖案化。後鈍化護層內連線104穿過鈍化護層102,以電性連接導電接墊22。在一實施例中,後鈍化護層內連線104包括一內連線區28I及一接合墊(landing pad)區28P。內連線區28I及接合墊區28P可同時形成,且由同一導電材料所構成。一凸塊特徵部件在後續製程中將會形成於接合墊區28P並與其電性連接。後鈍化護層內連線104可包括但不限於使用電鍍、無電電鍍、濺鍍或化學氣相沉積等所形成的銅、鋁、銅合金或其他活動態導電材料。在一些實施中,後鈍化護層內連線104可作為電源線、重佈線(re-distribution line,RDL)、電感、電容或任何被動元件。透過後鈍化護層內連線104的佈線,接合墊區28P可直接位於或不位於導電接墊22上。
在後鈍化護層內連線上製造保護結構及凸塊結構的後續製程係以沿第5圖中5-5線的剖面示意圖作說明。在 第6至9圖中係省略一些部件已達到簡化及清晰的目的。
請參照第6圖,第一保護層30I、高分子層32及第二保護層30II依序形成於基底100上。高分子層32由擇自於環氧化物、聚醯亞胺、苯並環丁烯(BCB)或聚苯噁唑(PBO)等高分子材料所構成。在一實施例中,高分子層32可具有相對較高的彈性。再者,高分子層32可由適用於固化前形成疊層的材料所構成。為了降低用以形成開口的圖案化步驟的成本,高分子層32可由光阻材料所構成,其在曝光之後容易進行圖案化。高分子層32的厚度大於30微米,且大於100微米。高分子層32的厚度也可在30微米至200微米的範圍。具有大厚度的高分子層32可作為有效的應力緩衝。本文中所列舉的尺寸僅作為範例說明,且將會隨著積體電路的尺寸縮小而縮小。
接著,請參照第7圖,使用微影及蝕刻製程,以形成穿過第二保護層30II、高分子層32及第一保護層30I且露出部分的接合墊區28P的開口108A而完成保護結構106A的製做。接著在保護結構106A上形成一金屬化層36,並進行凸塊製程,如第8及9圖所示。圖案化金屬化層36,以作為導電凸塊112下方的凸塊下方金屬(UBM)層110。在一實施例中,金屬化層36形成於保護結構106A的表面且露出接合墊區28P的表面。在至少一實施例中,金屬化層36包括一擴散阻障層。擴散阻障層可由鈦(Ti)所構成,然而也可使用其他的材料,例如氮化鈦(TiN)、氧化鈦(TiOx )、鉭(Ta)、氮化鉭 (TaN)或其組合(例如,Ti/TiN或Ti/TiN/Ti等)。形成的方法包括物理氣相沉積(PVD)或濺鍍。在至少一實施例中,金屬化層36包括位於擴散阻障上的一銅層。銅層可透過物理氣相沉積或濺鍍而形成。在一些實施例中,銅層可由銅合金所構成,其包括銀、鉻、鎳、錫、金或其組合。
請參照第9圖,一導電凸塊112形成於金屬化層36上,且填入開口108A。圖案化金屬化層36,以作為導電凸塊112下方的凸塊下方金屬層110,因而露出第二保護層30II的上表面,而完成位於半導體裝置上且包括凸塊下方金屬層110及導電凸塊112的凸塊結構114A的製做。在一些實施例中,凸塊下方金屬層110更包括位於第二保護層30II表面正上方的部分,以形成一突出部110a。導電凸塊112可在進行圖案化金屬化層36的步驟之前或之後製做。在一實施例中,導電凸塊112為一焊料凸塊,其係透過在金屬化層36上放置焊球並接著進行焊料回流製程而形成。焊料凸塊可包括無鉛預焊層、SnAg或一焊料(其包括由錫、鉛、銀、銅、鎳、鉍或其組合所構成的合金)。在另一實施例中,導電凸塊112為焊料凸塊,其透過使用遮罩及微影、焊料電鍍、光阻剝除製程以及凸塊下方金屬層蝕刻與焊料回流製程而形成。在至少一些實施例中,另一金屬化層可在進行焊料電鍍製程之前製做。舉例來說,透過電鍍、無電電鍍或沉浸金屬沉積(immersion metal deposition)製程而形成一銅層、一銅合金層、一鎳層、一鎳合金層或其組合。在一 些實施例中,導電凸塊112可為一金屬柱體,例如一銅柱體。
請參照第10至14圖,其繪示出根據第2圖實施例之半導體裝置中具有另一保護結構106B的凸塊結構114A製造方法剖面示意圖,除了特別不同之處,其他相同於第5至9圖的部件係使用相同的標號。
請參照第10圖,在形成第一保護層30I及高分子層32之後,圖案化高分子層32,以露出部分的第一保護層30I。在一實施例中,移除位於鈍化護層102上方局部的第一保護層30I上的高分子層32。也移除位於接合墊區28P上表面局部的第一保護層30I上的高分子層32。而高分子層32餘留於局部第一保護層30I上且鄰近於接合墊區28P的側壁。接下來,請參照第11圖,形成第二保護層30II,以覆蓋第一保護層30I及高分子層32。此後,為了簡化及清晰目的,第一及第二保護層30I及30II係以保護層30表示之。
接著移除位於接合墊區28P上表面的保護層30,如第12圖所示,其提供後續製做凸塊結構的開口。以上完成保護結構106B的製做,其包括被保護層30的第一部30a、第二部30b、第三部30c、第四部30d及第五部30e隔絕的高分子層32。
接著,一金屬化層36形成於保護結構106b上,並接著進行凸塊製程,如第13及14圖所示。圖案化金屬化層36,以作為導電凸塊112下方的凸塊下方金屬層110,因而露出保護層30的上表面。在一些實施例中, 凸塊下方金屬層110更包括位於保護層30表面正上方的部分,以形成一突出部110a。在一實施例中,導電凸塊112為焊料凸塊。在一些實施例中,導電凸塊112可為金屬柱體,例如銅柱體。
於先前說明中,本文配合特定實施例來作說明。然而,很明顯的是在不脫離本發明之精神和範圍內,當可作出各種不同的潤飾、結構、製程及更動。因此,說明書及圖式是用於範例說明而非用以限定本發明。可以理解本說明能夠用於不同的其他組合及環境,且能夠在不脫離本發明之精神和範圍內作出更動及潤飾。
10‧‧‧半導體基底
12‧‧‧電路
14‧‧‧內層介電層
16‧‧‧金屬層間介電層
16T‧‧‧頂層金屬層間介電層
18‧‧‧金屬線
19‧‧‧介層窗
20‧‧‧上金屬層
22‧‧‧導電接墊
24‧‧‧第一鈍化護膜
26‧‧‧第二鈍化護膜
28I‧‧‧內連線區
28P‧‧‧接合墊區
30‧‧‧保護層
30a‧‧‧第一部
30b‧‧‧第二部
30c‧‧‧第三部
30d‧‧‧第四部
30e‧‧‧第四部
30I‧‧‧第一保護層
30II‧‧‧第二保護層
32‧‧‧高分子層
36‧‧‧金屬化層
100‧‧‧裝置基底
102‧‧‧鈍化護層
104‧‧‧後鈍化護層內連線
106A、106B‧‧‧保護結構
108A、108B‧‧‧開口
109a‧‧‧主開口
109b‧‧‧周圍開口
110‧‧‧凸塊下方金屬層
110a‧‧‧突出部
112‧‧‧導電凸塊
112a‧‧‧延伸部
114A、114B‧‧‧凸塊結構
第1圖係繪示出根據本發明一實施例之具有保護結構位於後鈍化護層內連(PPI)線上方的凸塊剖面示意圖;第2至4圖係繪示出根據本發明不同實施例之具有保護結構的凸塊剖面示意圖;第5至9圖係繪示出根據第1圖實施例之半導體裝置中具有保護結構的凸塊結構製造方法剖面示意圖;以及第10至14圖係繪示出根據第2圖實施例之半導體裝置中具有保護結構的凸塊結構製造方法剖面示意圖。
30I‧‧‧第一保護層
30II‧‧‧第二保護層
32‧‧‧高分子層
100‧‧‧裝置基底
102‧‧‧鈍化護層
104‧‧‧後鈍化護層內連線
106A‧‧‧保護結構
108A‧‧‧開口
110‧‧‧凸塊下方金屬層
110a‧‧‧突出部
112‧‧‧導電凸塊
114A‧‧‧凸塊結構

Claims (9)

  1. 一種半導體裝置,包括:一半導體基底;一鈍化護層,位於該半導體基底上;一後鈍化護層內連線,位於該鈍化護層上;一保護結構,位於該鈍化護層及該後鈍化護層內連線上,其中該保護結構具有一開口,以至少露出一部分的該後鈍化護層內連線;以及一凸塊結構,形成於該保護結構內,且透過該保護結構的該開口而電性連接至該後鈍化護層內連線;其中該保護結構包括:一高分子層,夾設於一第一介電層與一第二介電層之間,其中該第一介電層夾設於該高分子層與該後鈍化護層內連線之間。
  2. 如申請專利範圍第1項所述之半導體裝置,其中該保護結構的該開口更露出鄰近於該後鈍化護層內連線的一部分的該鈍化護層。
  3. 如申請專利範圍第1項所述之半導體裝置,其中該凸塊結構包括一凸塊下方金屬層,順應性形成於該保護結構的該開口內,該凸塊下方金屬層包括一突出部,位於該保護結構的上表面上,且該凸塊結構包括一導電凸塊,形成於該凸塊下方金屬層上,且填入該保護結構的該開口內。
  4. 如申請專利範圍第3項所述之半導體裝置,其中該導電凸塊突出於該保護結構的上表面。
  5. 一種半導體裝置,包括: 一半導體基底;一鈍化護層,位於該半導體基底上;一後鈍化護層內連線,位於該鈍化護層上;一保護結構,位於該鈍化護層及該後鈍化護層內連線上,其中該保護結構具有一開口,以至少露出一部分的該後鈍化護層內連線;以及一凸塊結構,形成於該保護結構內,且透過該保護結構的該開口而電性連接至該後鈍化護層內連線;其中該保護結構包括:一高分子層以及圍繞該高分子層的一介電層,其中該高分子層透過該介電層而與該後鈍化護層內連線隔開。
  6. 如申請專利範圍第5項所述之半導體裝置,其中該高分子層透過該介電層而與該凸塊結構隔開。
  7. 如申請專利範圍第5項所述之半導體裝置,其中該介電層覆蓋該高分子層的上表面及外側壁。
  8. 如申請專利範圍第5項所述之半導體裝置,其中該保護結構的該開口更露出鄰近於該後鈍化護層內連線的一部分的該鈍化護層。
  9. 如申請專利範圍第5項所述之半導體裝置,其中該凸塊結構包括一凸塊下方金屬層,順應性形成於該保護結構的該開口內,該凸塊下方金屬層包括一突出部,位於該保護結構的上表面上且該凸塊結構包括一導電凸塊,形成於該凸塊下方金屬層上,且填入該保護結構的該開口內。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI449141B (zh) * 2011-10-19 2014-08-11 Richtek Technology Corp 晶圓級晶片尺度封裝元件以及其製造方法
US9257276B2 (en) 2011-12-31 2016-02-09 Intel Corporation Organic thin film passivation of metal interconnections
WO2013101243A1 (en) 2011-12-31 2013-07-04 Intel Corporation High density package interconnects
TWI484610B (zh) 2012-07-09 2015-05-11 矽品精密工業股份有限公司 半導體結構之製法與導電凸塊
US9673093B2 (en) 2013-08-06 2017-06-06 STATS ChipPAC Pte. Ltd. Semiconductor device and method of making wafer level chip scale package
CN104752404B (zh) * 2013-12-27 2019-01-25 中芯国际集成电路制造(上海)有限公司 用于封装测试的半导体结构及其形成方法
US9711474B2 (en) * 2014-09-24 2017-07-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure with polymeric layer and manufacturing method thereof
US9780052B2 (en) * 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods
US10658199B2 (en) * 2016-08-23 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10297563B2 (en) * 2016-09-15 2019-05-21 Intel Corporation Copper seed layer and nickel-tin microbump structures
US10290596B2 (en) * 2016-12-14 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a passivation layer and method of making the same
US10312207B2 (en) 2017-07-14 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation scheme for pad openings and trenches
US10276528B2 (en) * 2017-07-18 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor device and manufacturing method thereof
US10483226B2 (en) * 2018-04-20 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
DE102019117214A1 (de) 2019-06-26 2020-12-31 RF360 Europe GmbH Kontakthöckerkissenumfassung, Kontakthöckerverbinder, elektrisches Bauteil, elektrische Vorrichtung und Verfahren zum Herstellen
US10892239B1 (en) * 2019-07-10 2021-01-12 Globalfoundries Singapore Pte. Ltd. Bond pad reliability of semiconductor devices
TWI730884B (zh) * 2020-08-27 2021-06-11 新唐科技股份有限公司 半導體結構及其形成方法
US11942418B2 (en) * 2021-07-23 2024-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method for making the same
US20230274977A1 (en) * 2022-02-25 2023-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Self-Aligned Interconnect Structures and Methods of Forming the Same
DE102022107599A1 (de) 2022-03-30 2023-10-05 Infineon Technologies Ag Halbleitervorrichtung mit kontakt-pad-struktur

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7271030B2 (en) * 2003-10-20 2007-09-18 Texas Instruments Incorporated Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
US20080001290A1 (en) * 2006-06-28 2008-01-03 Megica Corporation Integrated circuit (IC) chip and method for fabricating the same
US7465653B2 (en) * 2001-02-15 2008-12-16 Megica Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8022543B2 (en) * 2008-03-25 2011-09-20 International Business Machines Corporation Underbump metallurgy for enhanced electromigration resistance

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070170599A1 (en) * 2006-01-24 2007-07-26 Masazumi Amagai Flip-attached and underfilled stacked semiconductor devices
US7674701B2 (en) * 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US9466577B2 (en) * 2008-02-22 2016-10-11 STATS ChipPAC Pte. Ltd. Semiconductor interconnect structure with stacked vias separated by signal line and method therefor
US9024431B2 (en) * 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7465653B2 (en) * 2001-02-15 2008-12-16 Megica Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US7271030B2 (en) * 2003-10-20 2007-09-18 Texas Instruments Incorporated Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
US20080001290A1 (en) * 2006-06-28 2008-01-03 Megica Corporation Integrated circuit (IC) chip and method for fabricating the same
US8022543B2 (en) * 2008-03-25 2011-09-20 International Business Machines Corporation Underbump metallurgy for enhanced electromigration resistance

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