TWI449141B - 晶圓級晶片尺度封裝元件以及其製造方法 - Google Patents

晶圓級晶片尺度封裝元件以及其製造方法 Download PDF

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Publication number
TWI449141B
TWI449141B TW100137821A TW100137821A TWI449141B TW I449141 B TWI449141 B TW I449141B TW 100137821 A TW100137821 A TW 100137821A TW 100137821 A TW100137821 A TW 100137821A TW I449141 B TWI449141 B TW I449141B
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Taiwan
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layer
solder
wafer
scale package
ball
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TW100137821A
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TW201318124A (zh
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Po Jui Chen
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Richtek Technology Corp
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Priority to TW100137821A priority Critical patent/TWI449141B/zh
Priority to US13/569,729 priority patent/US20130099380A1/en
Publication of TW201318124A publication Critical patent/TW201318124A/zh
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Publication of TWI449141B publication Critical patent/TWI449141B/zh
Priority to US14/579,753 priority patent/US20150111375A1/en

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Description

晶圓級晶片尺度封裝元件以及其製造方法
本發明係有關一種晶圓級晶片尺度封裝(WLCSP,Wafer Level Chip Scale Package)元件以及其製造方法，可增加封裝元件之I/O接點的站立高度(stand-off height)及尺寸，因此可以提升封裝元件之可靠度。
晶圓級晶片尺度封裝是以植球製程來製作晶片對外的I/O接點。根據Coffin-Mansion公式對於因溫度循環(temperature cycling)產生疲勞破壞之預測，可知球的站立高度越大，則可越提高元件封裝的疲勞耐受循環數(endurance cycle)。因此，先前技術提出一些方法來增加I/O接點植球的站立高度。對於增加植球的站立高度，最直接的方式是選用直徑較大之單一錫球。然採大的錫球時若仍保持相同的球間距(ball pitch)，就很容易於後續迴焊(reflow)製程中造成相鄰錫球熔接在一起，形成短路而報廢。換言之，若晶片的球間距受到限制，則單一錫球的站立高度也受到限制。
第1圖顯示先前技術之晶圓級晶片尺度封裝元件與電路板結合之示意圖。參照第1圖，在晶圓級晶片尺度封裝元件10之I/O接點12係以雙錫球堆疊於晶片(chip)13之主動面(active surface)上，以藉由雙錫球來增加站立高度H。晶片13直接連接之基部錫球(solder ball)周圍係由環氧樹脂(epoxy)14保護，又於環氧樹脂(epoxy)14露出基部錫球之各開口進行二次植球(ball mount)，如此才能形成疊球之I/O接點12。疊置於基部錫球上之另一錫球係銲接於電路板11上，由於晶片13和電路板11之熱膨脹係數(CTE)相差較大，而不同熱膨脹係數之材料會因溫度變化而有不同變形量，故I/O接點12之兩端有不同位移而產生應力。尤其，當晶片13之尺寸較大時，位於晶片13之角落附近的I/O接點12會受到更大之應力。雖然此種I/O接點12可以有較大之站立高度H(由晶片13之表面至電路板11之表面的距離)，以提升封裝元件之可靠度，且樹脂14能作為應力之緩衝層，但晶圓級晶片尺度封裝元件10需要二次植球之製程，且採取較少使用之環氧樹脂，故製程複雜及成本較高，並有應力與對準的問題。
第2圖顯示先前技術US 6930032之晶圓級晶片尺度封裝元件之示意圖。晶片201之周圍有複數個銲墊203，藉由重新分配層(redistribution layer；RDL)將各銲墊203連接至位於中間之一重分配銲墊205。於重分配銲墊205先形成一緩衝層211，並再沉積一呈現凹字型之球底金屬層(under bump metallurgy；UBM) 215。錫球217係焊接於凸塊下金屬化層215上，藉由此凹字型之特殊結構保護錫球217之最脆弱的頸部。又介於各球底金屬層215間有兩個介電層207及209。雖然此種球底金屬層215的特殊設計可以使錫球217較不易於頸部發生斷裂，但需要修改光罩，以及特殊之製程參數，故製程複雜及成本較高。
有鑑於此，本發明即針對上述先前技術之不足，提出一種晶圓級晶片尺度封裝元件以及其製造方法，可增加封裝元件之I/O接點的站立高度及尺寸，因此可以提升封裝元件之可靠度。
本發明目的之一在提供一種晶圓級晶片尺度封裝元件。
本發明的另一目的在提供一種晶圓級晶片尺度封裝元件之製造方法。
為達上述之目的，就其中一個觀點言，本發明提供了一種晶圓級晶片尺度封裝元件，包含：一晶片，包括至少一銲墊；一球底金屬層，設於該銲墊上；一預銲層，設於該球底金屬層上；以及一凸塊，與該預銲層相熔接而結合。
在其中一種實施型態中，上述晶圓級晶片尺度封裝元件另包含：一阻障層，設於該銲墊上；以及一種晶層，設於該阻障層上，且在該球底金屬層下。
在其中一種實施型態中，該凸塊係一錫球。該預銲層之材料係選擇錫、錫鉛合金、錫鋅合金、錫銀合金、錫銅合金、或錫銀銅合金中一者。
在其中一種實施型態中，該預銲層之材料係選擇和該凸塊能互相熔接之金屬或合金。
在其中一種實施型態中，該預銲層及該凸塊結合形成一I/O接點，該I/O接點之尺寸大於該凸塊之尺寸。
就再一個觀點言，本發明提供了一種晶圓級晶片尺度封裝元件，包含：一晶片，包括至少一銲墊；一球底金屬層，設於該銲墊上；一第一預銲層，設於該球底金屬層上；一第二預銲層，設於該第一預銲層上，其中該第一預銲層之熔點高於該第二預銲層之熔點；以及一凸塊，與該第二預銲層相熔接而結合。
在其中一種實施型態中，該第一預銲層之材料係選擇熔點較高的焊錫。
就再一個觀點言，本發明提供了一種晶圓級晶片尺度封裝元件之製造方法，包含：提供一具有至少一銲墊之晶片；形成一球底金屬層於該銲墊上；形成一預銲層於該球底金屬層上；以及熔接一凸塊與該預銲層而結合。
在其中一種實施型態中，本方法另包含：形成一高熔點預銲層於該球底金屬層及該預銲層之間，其中該高熔點預銲層之熔點高於該預銲層之熔點。
在其中一種實施型態中，本方法另包含：形成一阻障層於該銲墊上；以及形成一種晶層於該阻障層上，且在該球底金屬層下。
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明中的圖式均屬示意，主要意在表示結構中各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。
請參閱第3A圖至第3I圖，顯示本發明的一實施例之各製造步驟。如第3A圖所示，提供一晶片31。晶片31包括一半導體之基板311、至少一銲墊312及一第一鈍化層(passivation layer)313，其中銲墊312係設於基板311之主動面(active surface)上，又第一鈍化層313保護主動面之電路(圖未示)。第一鈍化層313有至少一個開口314，該開口314露出銲墊312以供內部連接線(internal connection)與外部連接。
於第一鈍化層313上，再形成一第二鈍化層32，如第3B圖所示。該第二鈍化層32之材料是利用旋塗(spin coating)或化學氣相沉積的方式所形成，其材料可為氧化矽、苯環丁烯(BCB)或聚苯噁唑(polybenzoxazole,PBO)。本實施例中，第二鈍化層32覆蓋銲墊312外圍之部分面積，然本發明之保護範圍並不受此限制。
參閱第3C圖及第3D圖，以濺鍍或化學沉積依序形成一阻障層(barrier layer) 33’及一種晶層(seed layer) 34’。阻障層33’功用主要是防止後續銲墊與球底金屬層快速反應，其材料係選自鈦金屬、氮化鈦、鈦鎢合金、鉭金屬層、鉻、鉻銅合金及氮化鉭其中之一或所組成之群組的其中之至少一者。種晶層34’功用係使後續球底金屬層有較佳之晶向成長方向，因此選擇和該鍍膜相同之材料為較佳。
藉由微影製程形成一光阻層(photoresist layer) 39，再形成一球底金屬層(under bump metallurgy；UBM) 35於該種晶層34’上，如第3E圖所示。球底金屬層35之材料可以是Al/NiV/Cu、Ti/NiV/Cu、或Ti/Cu/Ni等，但不限於前開所例示之材料。利用相同之光阻層39為遮罩，再沉積一預銲層36於球底金屬層35上，如第3F圖所示。預銲層36可以選擇和後續接合之凸塊能互相熔接之金屬或合金。當凸塊係錫球時，則預銲層36係選擇錫、錫鉛合金、錫鋅合金、錫銀合金、錫銅合金或錫銀銅合金中一者。
參閱第3G圖，除去光阻層39、及蝕刻阻障層33’及種晶層34’位於預銲層36外側之部分區域，則阻障層33、種晶層34、球底金屬層35及預銲層36之部分或全部凸出於第二鈍化層32之上。然後，以網印或其他方式於球底金屬層35上塗佈助銲劑(flux) 38，並將凸塊37’植球(ball mount)於預銲層36上，如第3H圖所示。藉由迴焊製程，將凸塊37’和預銲層36相熔接而結合，如此形成一較原凸塊37’尺寸大之I/O接點37，如第3I圖所示。如此，I/O尺寸大之接點37焊接在電路板之銲墊，可以產生較大站立高度，因此根據前述Coffin-Mansion公式有較佳之可靠度。
如果直接選用較大尺寸之凸塊，雖然也可以得到較大站立高度，但如前所述容易於後續迴焊製程造成相鄰凸塊熔接。反觀，本案中位置固定之預銲層36不但可以產生較大站立高度，且能避免迴焊製程中較大寸大之凸塊(或錫球)因偏移而造成之短路。因此，本案不但可增加封裝元件之可靠度，相當適用於微間距(fine pitch)及高I/O接點數之電子產品；且仍利用原本之光罩及製程，故相較於前案有低成本(或不增加成本)之優勢。以目前的植球製程為例，若I/O接點之節距為400um，最大可植約250um直徑的錫球，迴焊後的錫球高度(ball height)大約為200um(假設球底金屬層直徑為240um)。若採用本案前述之實施例所教示之步驟，假設先在球底金屬層上方鍍上一厚約55um的預銲層，則在採用相同250um直徑的錫球之條件下，迴焊後錫球高度約可達到220um，即站立高度可提升約10%，又以Coffin-Mansion equation公式來預估大約可提昇20%的疲勞耐受循環數(代表可靠度)。
第4A圖至第4D圖示出本發明另一實施例之部分製造步驟。本實施例之製造步驟係接續前開實施例之第3E圖，亦即第3A圖至第3E圖皆係本實施例之製造步驟，之後銜接第4A圖。參閱第4A圖，利用相同之光阻層39為遮罩，再沉積一具高熔點之第一預銲層461於球底金屬層35上，接著沉積一第二預銲層462於第一預銲層461上。第二預銲層462可以選擇和後續接合之凸塊能互相熔接之金屬或合金，亦即可選用與前開實施例之預銲層36相同之材料。第一預銲層461之材料可以選擇熔點較高的焊錫，例如：錫金(Sn/Au)合金、錫鋅(Sn/Zn)合金等。
參閱第4B圖，除去光阻層39。及蝕刻阻障層33’及種晶層34’位於預銲層36兩側之部分區域，則阻障層33、種晶層34、球底金屬層35、第一預銲層461及第二預銲層462之部分或全部凸出於第二鈍化層32之上。然後，以網印或其他方式於球底金屬層35上塗佈助銲劑38，並將凸塊37’植球(ball mount)於第二預銲層462上，如第4C圖所示。藉由迴焊製程，將凸塊37’和第二預銲層462相熔接而結合，但高熔點之第一預銲層461則未與凸塊37’和第二預銲層462相熔，如此形成一較原凸塊37’尺寸大之I/O接點47，如第4D圖所示。如此，藉由高熔點之第一預銲層461，可更有效增加錫球的站立高度，因此根據前述Coffin-Mansion公式有較佳之可靠度，但由於錫球直徑沒有大幅增加，因此與相鄰錫球不至於熔接在一起。
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，本發明之控制迴路中回授訊號之產生，並不限於以誤差放大器處理，或可採減法器減去參考電壓以產生各級之回授訊號。因此，本發明的範圍應涵蓋上述及其他所有等效變化。
10．．．晶圓級晶片尺度封裝元件
11．．．電路板
12．．．I/O接點
13．．．晶片
14．．．樹脂
201．．．晶片
203．．．銲墊
205．．．重分配銲墊
207、209．．．重分配銲墊
215．．．凸塊下金屬化層
217．．．錫球
31．．．晶片
311．．．基板
312．．．銲墊
313．．．第一鈍化層
314．．．開口
32．．．第二鈍化層
33、33’．．．阻障層
34、34’．．．種晶層
35．．．球底金屬層
36．．．預銲層
37’．．．凸塊
37、47．．．I/O接點
38．．．助銲劑
39．．．光阻層
461．．．第一預銲層
462．．．第二預銲層
第1圖顯示先前技術之晶圓級晶片尺度封裝元件與電路板結合之示意圖。
第2圖顯示先前技術之晶圓級晶片尺度封裝元件之示意圖。
第3A圖至第3I圖顯示本發明的一實施例之晶圓級晶片尺度封裝元件之各製造步驟。
第4A圖至第4D圖示出本發明另一實施例之晶圓級晶片尺度封裝元件之部分製造步驟。
31‧‧‧晶片
311‧‧‧基板
312‧‧‧銲墊
313‧‧‧第一鈍化層
32‧‧‧第二鈍化層
33‧‧‧阻障層
34‧‧‧種晶層
35‧‧‧球底金屬層
37‧‧‧I/O接點

Claims (8)

  1. 一種晶圓級晶片尺度封裝元件，包含：一晶片，包括至少一銲墊；一球底金屬層，設於該銲墊上；一第一預銲層，設於該球底金屬層上；一第二預銲層，設於該第一預銲層上，其中該第一預銲層之熔點高於該第二預銲層之熔點；以及一凸塊，與該第二預銲層相熔接而結合。
  2. 如申請專利範圍第1項所述之晶圓級晶片尺度封裝元件，其另包含：一阻障層，設於該銲墊上；以及一種晶層，設於該阻障層上，且在該球底金屬層下。
  3. 如申請專利範圍第1項所述之晶圓級晶片尺度封裝元件，其中該凸塊係一錫球。
  4. 如申請專利範圍第3項所述之晶圓級晶片尺度封裝元件，其中該第二預銲層之材料係選擇錫、錫鉛合金、錫鋅合金、錫銀合金、錫銅合金或錫銀銅合金中一者。
  5. 如申請專利範圍第1項所述之晶圓級晶片尺度封裝元件，其中該第二預銲層之材料係選擇和該凸塊能互相熔接之金屬或合金。
  6. 如申請專利範圍第1項所述之晶圓級晶片尺度封裝元件，其中該第二預銲層及該凸塊結合形成一I/O接點，該I/O接點之尺寸大於該凸塊之尺寸。
  7. 如申請專利範圍第1項所述之晶圓級晶片尺度封裝元件，其中該第一預銲層之材料係選擇熔點較高的焊錫。
  8. 一種晶圓級晶片尺度封裝元件之製造方法，包含： 提供一具有至少一銲墊之晶片；形成一球底金屬層於該銲墊上；形成一預銲層於該球底金屬層上；以及形成一高熔點預銲層於該球底金屬層及該預銲層之間，其中該高熔點預銲層之熔點高於該預銲層之熔點熔接一凸塊與該預銲層而結合。
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