TWI408786B - 半導體元件之銲墊結構 - Google Patents

半導體元件之銲墊結構 Download PDF

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Publication number
TWI408786B
TWI408786B TW99112377A TW99112377A TWI408786B TW I408786 B TWI408786 B TW I408786B TW 99112377 A TW99112377 A TW 99112377A TW 99112377 A TW99112377 A TW 99112377A TW I408786 B TWI408786 B TW I408786B
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Taiwan
Prior art keywords
metal
layers
vias
pad
dummy
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TW99112377A
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English (en)
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TW201118997A (en
Inventor
Hsienwei Chen
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Taiwan Semiconductor Mfg
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Publication of TW201118997A publication Critical patent/TW201118997A/zh
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    • H—ELECTRICITY
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

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Description

半導體元件之銲墊結構
本發明是有關於一種半導體元件，特別是有關於一種半導體元件之銲墊結構。
在半導體技術中，晶圓會經歷各種製程以形成積體電路。積體電路之銲線路徑係由內連線結構所提供，其中內連線結構可包括多個金屬層，而此些金屬層係一一由介墊層絕緣。銲墊一般係形成於內連線結構上，用以進行晶圓級測試以及晶片封裝(例如打線(wire bonding)以及覆晶(flip-chip))。在先進技術製程(例如45奈米、32奈米以及以下)中，在內連線結構中使用低介電常數(low-k)之介電材料，可提升其效能。然而，上述低介電常數之介電材料的機械強度性質較弱，特別是金屬層受到高應力(stress)的區域，例如銲墊下方的區域，會造成剝離或龜裂。是以，金屬層之剝離或龜裂會導致元件效能不佳，而且在一些情形下會導致元件失效。
因此，本發明之一態樣是在提供一種半導體元件，其包括此半導體基材具有複數個微電子構件；一內連線結構形成於前述半導體基材上，其中此內連線結構包括複數個金屬層及用以隔離前述金屬層之複數個內金屬介電層，前述金屬層包括一頂金屬層、一底金屬層、以及設於頂金屬層與底金屬層之間的至少二金屬層；複數個虛擬金屬介層窗形成於前述內金屬介電層之一或多者中，其中前述內金屬介電層係設於前述至少二金屬層之間；以及一銲墊結構，其中此銲墊結構係形成於前述虛擬金屬介層窗之正上方。
其次，本發明之另一態樣是在提供一種半導體元件之製造方法，其包括提供一半導體基材，其中此半導體基材具有複數個微電子構件；形成一內連線結構形成於前述半導體基材上，其中此內連線結構包括複數個金屬層以及複數個內金屬介電層，前述金屬層包括一頂金屬層、一底金屬層、以及設於頂金屬層與底金屬層之間的至少二金屬層；形成複數個虛擬金屬介層窗於前述內金屬介電層之一或多者中，其中前述內金屬介電層係設於至少二金屬層之間；以及形成一銲墊結構，其中此銲墊結構係形成於前述虛擬金屬介層窗之正上方。
再者，本發明之又一態樣是在提供一種半導體元件，其包括此半導體基材具有複數個微電子構件；一內連線結構形成於前述半導體基材上，其中此內連線結構包括一頂金屬層以及一底金屬層，且此頂金屬層包括一金屬銲墊；複數個虛擬金屬介層窗形成於前述內金屬介電層之一或多者中，其中前述內金屬介電層係設於前述頂金屬層與底金屬層之間，前述虛擬金屬介層窗係位於前述頂金屬層之金屬銲墊之下方，前述虛擬金屬介層窗建立一介層窗密度，此介層窗密度是根據位於前述頂金屬層之金屬銲墊正下方的內連線結構之一區域計算。
可以理解的是，以下揭露內容提供許多不同的實施例或例示，以實施本發明之不同特徵。以下所述之構件與排列的特定例示係用以簡化本揭露內容。當然，這些例示僅為舉例說明，並非用以限制本發明。此外，本揭露可能會在各種例子中重覆使用圖號及/或字母符號。此重覆使用的目的係為了簡要清楚說明，其本身並不指定所討論之各種實施例及/或配置之間的關係。再者，舉例而言，說明書中，第一特徵形成於第二特徵上或其上方，可能包括第一特徵以直接接觸之方式形成於第二特徵上的實施例，也可能包括第一特徵與第二特徵之間形成其他額外特徵、以至於第一特徵以非直接接觸之方式形成於第二特徵上的實施例。
請參閱第1圖，其係根據本揭露內容之各種觀點說明半導體元件之製造方法100。此方法100係自方塊102開始，其係提供一半導體基材，其中此半導體基材具有複數個微電子構件。接著，此方法100繼續進行至方塊104，其係形成一內連線結構形成於前述半導體基材上。此內連線結構包括複數個金屬層以及複數個內金屬介電層。前述金屬層包括一頂金屬層、一底金屬層、以及設於頂金屬層與底金屬層之間的至少二金屬層。之後，此方法100繼續進行至方塊106，其係形成複數個虛擬金屬介層窗於前述內金屬介電層之一或多者中，其中前述內金屬介電層係設於至少二金屬層之間。然後，此方法100繼續進行至方塊108，其係形成一銲墊結構，其中此銲墊結構係形成於前述虛擬金屬介層窗之正上方。實施上述方法100可製造以下所述之半導體元件的各種實施例。
請參閱第2圖，其係根據本揭露內容之各種觀點說明具有銲墊結構之半導體元件200的剖面示意圖。在一實施例中，此半導體元件200可根據第1圖之方法100製造。可以理解的是，此半導體元件200包括各種特徵與結構，惟此處係加以簡化，以更加了解本揭露內容之發明概念。半導體元件200包括半導體基材202，例如結晶結構的矽基材。此半導體元件200亦可包括其他元素型半導體，例如鍺。另一種方式，此半導體元件200亦可選擇性包括化合物型半導體，例如碳化矽、砷化鎵、砷化銦以及磷化銦。此外，此半導體元件200亦可選擇性包括藉由磊晶成長製程形成之磊晶層。此半導體元件200更可至少包含複數個隔離特徵(圖未繪示)，例如淺溝渠隔離(shallow trench isolation；STI)特徵或區域性矽氧化(local oxidation of silicon；LOCOS)特徵。
隔離特徵可定義並隔離出不同微電子構件(圖未繪示)之主動區，前述微電子構件例如電晶體(例如金屬氧化半導體場效電晶體(metal oxide semiconductor field effect transistor；MOSFET)、互補式金氧半導體(complementary metal oxide semiconductor；CMOS)電晶體、雙載子接合電晶體(bipolar junction transistor；BJT)、高壓電晶體、高頻電晶體等)、電阻、二極體、電容以及其他適合的構件。因此，可進行熟習此項技藝人士可以使用的各種製程，例如沉積、蝕刻、離子植入、微影、回火以及其他適合的製程，以形成微電子構件。微電子構件經由內連線連接而形成積體電路，例如邏輯元件、記憶元件(例如靜態隨機存取記憶體(SRAM))、射頻(RF)元件、輸入/輸出(input/output；I/O)元件、系統單晶片(system-on-chip；SoC)元件、上述之任意組合以及其他適合形式的習知元件。
此半導體元件200更包括形成於其上之內層介電(inter-layer dielectric；ILD)層204，其中此半導體元件200包括微電子構件。內層介電層204可包括氧化矽、氮氧化矽、或其他低介電常數材料。內層介電層204可藉由化學氣相沉積(chemical vapor deposition；CVD)法、高密度電漿化學氣相沉積(high density plasma CVD；HDP-CVD)法、旋塗(spin-on)法、物理氣相沉積(physical vapor deposition；PVD；或濺鍍(sputtering))法、或其他適合的技術而形成。應留意的是，在形成內層介電層204之前，可形成例如接觸蝕刻終止層(contact etch stop layer；CESL)之應力層於半導體基材202上。此半導體元件200更包括形成於內層介電層204上之複數個接觸206(亦稱為第一接觸)。前述接觸206可藉由對內層介電層204進行第一圖案化及蝕刻步驟而形成多個溝渠。前述溝渠可藉由沉積例如氮化鈦(TiN)之金屬阻障層而進行填充，之後沉積例如鎢(W)之接觸插塞層於金屬阻障層上。在一些實施例中，鎢接觸插塞之金屬阻障層可包括鈦/氮化鈦(Ti/TiN)。在一些實施例中，銅(Cu)接觸插塞之金屬阻障層可包括鉭/氮化鉭(Ta/TaN)。接觸206可提供半導體基材202上形成之各種微電子構件的電性連接。
此半導體元件200更包括內連線結構。此內連線結構包括複數個金屬層210a至金屬層210i，以提供各種微電子構件之間以及金屬層本身之間的內連線(打線)。可以理解的是，金屬層的數量端視特定半導體元件的設定而有所變動。在揭露的實施例中，前述金屬層210a至金屬層210i包括九層金屬層，即底金屬層210a(M1)、頂金屬層210i(M9)、以及介於底金屬層210a(M1)與頂金屬層210i(M9)之間的金屬層210b(M2)至金屬層210h(M8)。前述金屬層210a(M1)至金屬層210i(M9)可包括由導體材料形成之線路，而此導體材料可例如鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、複晶矽、金屬矽化物、或上述之任意組合。另一種方式，前述金屬層210a(M1)至金屬層210i(M9)可包括由導體材料形成之線路，而此導體材料可例如銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、複晶矽、金屬矽化物、或上述之任意組合。
前述金屬層210a(M1)至金屬層210i(M9)可藉由多個內金屬介電(inter-metal dielectric；IMD)層220而互相絕緣。前述內金屬介電層220可包括低介電常數材料。在一些實施例中，前述內連線結構中不同層的內金屬介電層220可由不同介電材料而形成。目前已觀察到，以低介電常數(low-K；LK)材料、超低介電常數(extreme low-K；ELK)材料、及/或極低介電常數(extra low-K；XLK)材料會提升線路效能。前述介電材料係根據介電常數進行分類。舉例而言，低介電常數材料係指介電常數低於約3.5之材料，而以介電常數低於約3.0之材料為較佳。超低介電常數材料係指介電常數低於約2.9之材料，而以介電常數低於約2.6之材料為較佳。極低介電常數材料係指介電常數低於約2.4之材料。可以理解的是，上述分類僅為例示，根據材料之介電常數的其他分類亦可使用。前述LK、ELK及/或XLK介電材料可至少包含氮化矽、氮氧化矽、旋塗式玻璃(spin-on glass；SOG)、未摻雜矽酸鹽玻璃(undoped silicate glass；USG)、氟化矽玻璃(fluorinated silica glass；FSG)、碳摻雜氧化矽(例如SiCOH)、含碳材料、黑鑽石(Black Diamond；Applied Materials of Santa Clara,California)、乾凝膠(Xerogel)、氣凝膠(Aerogel)、非晶系氟化碳(amorphous fluorinated carbon)、聚對二甲苯(Parylene)、苯并環丁烯(bis-benzocyclobutenes；BCB)、摻氟的聚對二甲苯醚(Flare)、芳香族碳氫化合物(SiLK；Dow Chemical,Midland,Michigan)、聚亞醯胺(polyimide)、其他適合的多孔性高分子材料、其他適合的介電材料、及/或上述之任意組合。內金屬介電層220可利用旋塗(spin-on)法、化學氣相沉積(CVD)法、物理氣相沉積(PVD)法、或原子層沉積(atomic layer deposition；ALD)法等技術形成。
雖然前述LK、ELK及XLK介電材料可提升線路效能，不過已觀察到上述材料(例如多孔性材料)呈現的機械強度較差，也因此在受到各種半導體製程引起的應力時，會導致剝離、龜裂及/或分層(delaminate)。此外，根據應力分布的分析，已觀察到越高的金屬層會比越低的金屬層受到更高的應力。舉例而言，在晶片封裝時，位於銲墊結構、接合(bonding)結構、或銲球結構正下方的區域240(虛線所示之區域)內之較上層的金屬層210d至210i(M4以上)以及內金屬介電層220，會受到較高的機械應力。因此，相較於內連線結構之其他區域，區域240內出現剝離、龜裂及/或分層的風險會較高。另外，中間金屬層(M4/M5，或M5/M6)的界面產生薄膜龜裂的風險較高。故此，以下揭露之特徵及結構可提供節省成本又有效率的技術，以強化區域240內之內金屬介電層220的機械強度。然而，可以理解的是，以下揭露之特徵及結構亦可用於強化或鞏固內連線結構的其他區域，及/或半導體元件200中可應用的其他介電層。
金屬層210a至210i及內金屬介電層220可於例如金屬鑲嵌(damascene)製程或微影/電漿蝕刻製程等積體電路製程中形成。底金屬層210a(M1)可包括金屬線路224，其中此金屬線路224係與多個接觸206耦接，以連接至半導體基材202中形成的微電子構件。底金屬層210a(M1)更可包括多個虛擬金屬線路226，其中前述虛擬金屬線路226並未電性連接至任何具有功能的線路及/或銲墊。不過，前述虛擬金屬線路226可用於例如調整局部圖案密度，以獲致更佳的研磨效果。金屬層220b至220g(M2-M7)亦可包括金屬線路224與虛擬金屬線路226。內連線結構又可包括在前述內金屬介電層220內設置的金屬介層窗230，以連接鄰近金屬層220a至220i的金屬線路224。內連線結構更可包括多個虛擬金屬介層窗235，其中虛擬金屬介層窗235係設於區域240內之內金屬介電層220中。前述虛擬金屬介層窗235並未電性連接至任何具有功能的線路及/或銲墊。不過，前述虛擬金屬介層窗235可用於連接鄰近金屬層220d至220g(例如M4/M5、M5/M6以及M6/M7)的虛擬金屬線路226。故此，前述虛擬金屬介層窗235可強化區域240內之內金屬介電層220的機械強度。
在一實施例中，前述虛擬金屬介層窗235與實際金屬介層窗230(位於區域240內一或多層之內金屬介電層220中)可共同建立約1.5百分比之介層窗密度。以下將詳述根據銲墊結構、接合結構、或銲球結構，以局部計算出介層窗密度。在另一實施例中，前述虛擬金屬介層窗235與實際金屬介層窗230(位於區域240內一或多層之內金屬介電層220中)可共同建立約3.0百分比之介層窗密度。在其他實施例中，前述金屬層210d(M4)與金屬層210e(M5)之間可插入虛擬金屬介層窗235，以在區域240內之內金屬介電層220(介於金屬層210d(M4)與金屬層210e(M5)之間)中建立大於1.5百分比之介層窗密度。應留意的是，已經找出特定的介層窗密度百分比，以有效改善區域240內之內金屬介電層220的機械強度。然而，可以理解的是，根據設計需求及/或可取得的封裝覆蓋尺寸(footprint)，虛擬金屬介層窗可以使用其他百分比之介層窗密度。
頂金屬層210i(M9)及金屬層210h(M8)包括雙重金屬銲墊配置。舉例而言，金屬層210h(M8)包括金屬銲墊245，而頂金屬層210i(M9)包括金屬銲墊248。金屬銲墊245可包括與金屬銲墊248類似之形狀及尺寸。金屬銲墊245與金屬銲墊248係藉由設置於內金屬介電層220中的多個金屬介層窗250而彼此耦接。在其他實施例中，內連線結構可包括單一金屬銲墊配置，其中此金屬銲墊只形成於頂金屬層210i(M9)中。同樣地，前述金屬層210g(M7)與金屬層210h(M8)之間可插入虛擬金屬介層窗235。
此半導體元件200又可包括保護層252，此保護層252係形成於頂金屬層210i(M9)上，以覆蓋並保護內連線結構。保護層252可包括氧化矽、氮化矽、氮氧化矽、或上述之任意組合。此保護層252可利用化學氣相沉積(CVD)法、旋塗(spin-on)法、或其他適合的技術形成。
此半導體元件200更可包括銲墊260。銲墊260可形成於頂金屬層210i(M9)之金屬銲墊248上。銲墊260可配置成提供內連線結構電性連接，以進行晶圓級測試、打線、或晶片封裝。銲墊260可利用習知製程形成於保護層252內。舉例而言，可對保護層252進行蝕刻製程，形成開口以暴露出頂金屬層210i(M9)之金屬銲墊248。接著，可沉積導體材料層於保護層252上並填滿上述開口。然後，可對導體材料層進行圖案化以形成銲墊260。銲墊260可包括導電材料，而此導電材料可例如鋁、鋁合金、銅、銅合金、或上述之任意組合。為了獲致適當的接合性質，銲墊260的輪廓可具有適合的階梯高度。
保護層262可形成於保護層252上，而保護層262經圖案化後可暴露出銲墊260。保護層262可包括氧化矽、氮化矽、氮氧化矽、或上述之任意組合。此保護層262可利用化學氣相沉積(CVD)法、旋塗(spin-on)法、或其他適合的技術形成。此半導體元件200又包括銲線組270。銲線組270可形成為與銲墊260接觸。銲線組270可利用例如熱超音波接合(thermosonic bonding)及熱壓接合(thermocompression bonding)等習知打線(wire bonding)技術而形成。大體上，打線係運用機械力、熱能以及聲能，將銲線接至銲墊260。就不同的接合技術而言，銲墊260的厚度可提供適當的接合性質。銲線組270使半導體元件200得以與外部零件連接。
應當注意的是，可根據不同結構，而局部計算出前述區域240內之虛擬金屬介層窗235的介層窗密度。在一實施例中，銲墊260下方的局部區域可用於計算出介層窗密度。因此，介層窗密度可表示為(介層窗面積/銲墊面積)。在其他實施例中，頂金屬層210i(M9)之金屬銲墊248下方的局部面積可用來計算介層窗密度。所以介層窗密度可表示為(介層窗面積/金屬銲墊面積)。
請參閱第3圖，其係根據本揭露內容之各種觀點說明具有銲墊結構之半導體元件300的剖面示意圖。在一實施例中，半導體元件300可根據第1圖之方法100製造。此半導體元件300可類似於第2圖之半導體元件200，惟以下所述之相異處除外。為了簡化及清楚之故，第2圖與第3圖之相似特徵則以相同圖號來表示。半導體元件300包括多個虛擬金屬介層窗235，其中虛擬金屬介層窗235係設於區域310內。區域310類似於第2圖之區域240，不過區域310更延伸到下方的金屬層210a(M1)至金屬層210c(M3)。因此，頂金屬層210i(M9)之金屬銲墊248或銲墊260正下方的金屬層210a(M1)至金屬層210g(M7)之間可插入虛擬金屬介層窗235。從而，可局部計算出金屬銲墊248或銲墊260區域下方的介層窗密度。舉例而言，在一實施例中，虛擬金屬介層窗235與實際金屬介層窗230(位於區域310內一或多層之內金屬介電層220中)可共同建立約1.5百分比之介層窗密度。在另一實施例中，前述虛擬金屬介層窗235與實際金屬介層窗230(位於區域310內一或多層之內金屬介電層220中)可共同建立約3.0百分比之介層窗密度。在其他實施例中，前述金屬層210d(M4)與金屬層210e(M5)之間可插入虛擬金屬介層窗235，以在區域310內之內金屬介電層220(介於金屬層210d(M4)與金屬層210e(M5)之間)中建立大於1.5百分比之介層窗密度。
在較低的金屬層之間可設置額外的虛擬金屬介層窗，以進一步改善區域310內之內金屬介電層220的機械強度。應留意的是，半導體元件300可選擇性運用單一的金屬銲墊配置，因此虛擬金屬介層窗亦可插入金屬層210g(M7)與金屬層210h(M8)之間。
請參閱第4圖，其係根據本揭露內容之各種觀點說明具有銲墊結構之半導體元件400的剖面示意圖。在一實施例中，半導體元件400可根據第1圖之方法100製造。此半導體元件400可類似於第2圖之半導體元件200，惟以下所述之相異處除外。為了簡化及清楚之故，第2圖與第4圖之相似特徵則以相同圖號來表示。半導體元件400包括多個虛擬金屬介層窗235，其中虛擬金屬介層窗235係設於區域410內。區域410類似於第2圖之區域240，不過區域410係設於銲線組270之打線銲塊(wire bump)結構420的正下方。因此，虛擬金屬介層窗235係設於銲線組270之打線銲塊結構420正下方的金屬層210d(M4)至金屬層210g(M7)之間。從而，可局部計算出打線銲塊結構420區域下方的介層窗密度。舉例而言，打線銲塊結構具有直徑D，因此打線銲塊結構下方的局部區域可以表示為(D2 /4*π)。
在一實施例中，虛擬金屬介層窗235與實際金屬介層窗230(位於區域410內一或多層之內金屬介電層220中)可共同建立約1.5百分比之介層窗密度。在另一實施例中，前述虛擬金屬介層窗235與實際金屬介層窗230(位於區域410內一或多層之內金屬介電層220中)可共同建立約3.0百分比之介層窗密度。在其他實施例中，前述金屬層210d(M4)與金屬層210e(M5)之間可插入虛擬金屬介層窗235，以在區域410內之內金屬介電層220(介於金屬層210d(M4)與金屬層210e(M5)之間)中建立大於1.5百分比之介層窗密度。應留意的是，半導體元件400可選擇性運用單一的金屬銲墊配置，因此虛擬金屬介層窗亦可插入金屬層210g(M7)與金屬層210h(M8)之間。再者，雖然此處所示之虛擬金屬介層窗235係設於金屬層210d(M4)與金屬層210g(M7)之間，但可以理解的是，虛擬金屬介層窗亦可額外設置於較低的金屬層210a(M1)至金屬層210c(M3)之間，類似於第3圖所揭示的實施例。
請參閱第5圖，其係根據本揭露內容之各種觀點說明具有銲墊結構之半導體元件500的剖面示意圖。在一實施例中，半導體元件500可根據第1圖之方法100製造。此半導體元件500可類似於第2圖之半導體元件200，惟以下所述之相異處除外。為了簡化及清楚之故，第2圖與第5圖之相似特徵則以相同圖號來表示。半導體元件500包括覆晶組510，其中覆晶組510係取代第2圖的銲線組270。覆晶組510可使正面朝下(face-down)的半導體元件500直接電性連接至線路板或基材上。覆晶組510是習知晶片封裝的一種型式，故此處不另贅述。覆晶組510可包括於銲墊260上形成的凸塊下金屬(under bump metallization；UBM)結構512。凸塊下金屬結構512可包括不同材料層，其中此些材料層可以適當地將凸塊下金屬結構512附著至銲墊260與保護層262，可保護下方的材料，並使銲球514潤濕。銲球514可利用蒸鍍(evaporation)法、電鍍(electroplating)、印刷(printing)法、噴墨印刷(jetting)法、凸塊焊接(stud bumping)法或其他適合的技術，形成於凸塊下金屬結構512上。雖然此半導體元件500所示的虛擬金屬介層窗235設於區域240內，可以理解的是，區域240亦可如第3圖揭示的實施例，延伸至包括較低的金屬層210a(M1)至金屬層210d(M4)。
請參閱第6圖，其係說明一實施例之虛擬金屬介層窗的示意概圖600，此虛擬金屬介層窗可分別實施於第2圖至第5圖之各種半導體元件200、半導體元件300、半導體元件400以及半導體元件500中。在此實施例中，不同的具體尺寸係關於32奈米技術節點製程。可以理解的是，亦可使用其他尺寸以實施其他技術節點製程(例如60奈米、45奈米等)。此示意概圖600可用於產生具有虛擬金屬介層窗的設計佈局。此示意概圖600顯示二鄰近金屬層(例如第2圖至第5圖之金屬層210a至金屬層210i之間)。承上所論，鄰近金屬層之每一者包括虛擬金屬線路602與虛擬金屬線路604，其中虛擬金屬線路602與虛擬金屬線路604並未電性連接至任何具有功能的線路及/或銲墊。虛擬金屬線路602與虛擬金屬線路604可藉由虛擬金屬介層窗610而彼此連接。前述虛擬金屬線路602可具有正方形外觀，其寬度615約0.8微米(μm)。虛擬金屬線路604之外型與尺寸可與虛擬金屬線路602相似。虛擬金屬線路602與虛擬金屬線路604可具有約0.7微米(μm)之重疊617。虛擬金屬介層窗610可具有正方形外觀，其寬度619約0.35微米(μm)。虛擬金屬介層窗610與虛擬金屬線路602之間相隔距離621及距離623，其中距離621及距離623各約0.175微米(μm)。應當留意的是，虛擬金屬介層窗與虛擬金屬線路可實施成其他外形，例如橢圓形、圓形、矩形、其他多邊形以及不規則形。
請參閱第7圖，其係說明一實施例之虛擬金屬介層窗的示意概圖700，此虛擬金屬介層窗可分別實施於第2圖至第5圖之各種半導體元件200、半導體元件300、半導體元件400以及半導體元件500中。在此實施例中，不同的具體尺寸係關於32奈米技術節點製程。可以理解的是，亦可使用其他尺寸以實施其他技術節點製程(例如60奈米、45奈米等)。此示意概圖700可用於產生具有虛擬金屬介層窗的設計佈局。此示意概圖700顯示二鄰近金屬層(例如第2圖至第5圖之金屬層210a至金屬層210i之間)。承上所論，鄰近金屬層之每一者包括虛擬金屬線路702與虛擬金屬線路704，其中虛擬金屬線路702與虛擬金屬線路704並未電性連接至任何具有功能的線路及/或銲墊。虛擬金屬線路702與虛擬金屬線路704可藉由虛擬金屬介層窗710與虛擬金屬介層窗712而彼此連接。前述虛擬金屬線路702可具有正方形外觀，其寬度715約0.8微米(μm)。虛擬金屬線路704之外型與尺寸可與虛擬金屬線路702相似。虛擬金屬線路702與虛擬金屬線路704可具有約0.7微米(μm)之重疊717。虛擬金屬介層窗710與虛擬金屬介層窗712可具有正方形外觀，其寬度719約0.14微米(μm)。虛擬金屬介層窗710與虛擬金屬線路704之間相隔距離721及距離723，其中距離721及距離723各約0.065微米(μm)。虛擬金屬介層窗712可與虛擬金屬介層窗710相隔距離725及距離727，其中距離725及距離727各約0.29微米(μm)。應當留意的是，虛擬金屬介層窗與虛擬金屬線路可實施成其他外形，例如橢圓形、圓形、矩形、其他多邊形以及不規則形。
請參閱第8圖，其係說明一實施例之虛擬金屬介層窗的示意概圖800，此虛擬金屬介層窗可分別實施於第2圖至第5圖之各種半導體元件200、半導體元件300、半導體元件400以及半導體元件500中。在此實施例中，不同的具體尺寸係關於32奈米技術節點製程。可以理解的是，亦可使用其他尺寸以實施其他技術節點製程(例如60奈米、45奈米等)。此示意概圖800可用於產生具有虛擬金屬介層窗的設計佈局。此示意概圖800顯示二鄰近金屬層(例如第2圖至第5圖之金屬層210a至金屬層210i之間)。承上所論，鄰近金屬層之每一者包括虛擬金屬線路802與虛擬金屬線路804，其中虛擬金屬線路802與虛擬金屬線路804並未電性連接至任何具有功能的線路及/或銲墊。虛擬金屬線路802與虛擬金屬線路804可藉由虛擬金屬介層窗810、虛擬金屬介層窗811、虛擬金屬介層窗812與虛擬金屬介層窗813而彼此連接。前述虛擬金屬線路802可具有正方形外觀，其寬度815約0.8微米(μm)。虛擬金屬線路804之外型與尺寸可與虛擬金屬線路802相似。虛擬金屬線路802與虛擬金屬線路804可具有約0.7微米(μm)之重疊817。虛擬金屬介層窗810、虛擬金屬介層窗811、虛擬金屬介層窗812與虛擬金屬介層窗813可具有正方形外觀，其寬度819約0.12微米(μm)。虛擬金屬介層窗810與虛擬金屬線路804之間相隔距離821及距離823，其中距離821及距離823各約0.14微米(μm)。虛擬金屬介層窗810、虛擬金屬介層窗811、虛擬金屬介層窗812與虛擬金屬介層窗813係彼此相隔距離825及距離827，其中距離825及距離827各約0.18微米(μm)。應當留意的是，虛擬金屬介層窗與虛擬金屬線路可實施成其他外形，例如橢圓形、圓形、矩形、其他多邊形以及不規則形。
以上已概述數個實施例之特徵，可讓本發明所屬技術領域中任何具有通常知識者更加了解本揭露內容。本發明所屬技術領域的技術人員應可理解，其可輕易利用本揭露內容作為基礎，以設計或修改其他製程或結構，而實現與此處所述之實施例所述相同的目的及/或達成相同的優點。可以理解的是，使用上述例示製程步驟之各種不同的組合，可以結合使用或同時使用。其次，在某些實施例說明及討論的特徵亦可與其他實施例論及的特徵結合。故此，本發明所屬技術領域的技術人員應可理解，上述均等的架構並不脫離本發明之精神和範圍，且此等人員在不脫離本發明之精神和範圍下，可作各種之更動、替換、與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。舉例而言，上述實施例可利用各任何晶片封裝製程，其中可包括但不限於打線、覆晶、晶片接合、及銲錫凸塊接合(solder bump bonding)。此外，雖然上述第6圖至第8圖揭露之實施例顯示特定數量的虛擬介層窗，以連接鄰近金屬層之虛擬金屬線路，惟可以理解的是，可變化介層窗的數量及位置，以改善內連線結構之介電層的機械強度。
100．．．方法
102/104/106/108．．．方塊
200/300/400/500．．．半導體元件
202．．．半導體基材
204．．．內層介電層
206．．．接觸
210a/210b/210c/210d/210e/210f/210g/210h/210i(M1/M2/M3/M4/M5/M6/M7/M8/M9)．．．金屬層
220．．．內金屬介電層
224．．．金屬線路
226/602/604/702/704/802/804．．．虛擬金屬線路
230．．．金屬介層窗
235/610/710/712/810/811/812/813．．．虛擬金屬介層窗
240/310/410．．．區域
245．．．金屬銲墊
248．．．金屬銲墊
250．．．金屬介層窗
252/262．．．保護層
260．．．銲墊
270．．．銲線組
420．．．打線銲塊結構
510．．．覆晶組
512．．．凸塊下金屬結構
514．．．銲球
600/700/800．．．示意概圖
615/619/715/719/815/819．．．寬度
617/717/817．．．重疊
621/623/721/723/725/727/821/823/825/827．．．距離
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之詳細說明如下：
第1圖係根據本揭露內容之各種觀點之半導體元件的製造方法流程圖；
第2圖係根據本揭露內容各種觀點之一實施例具有銲墊結構之半導體元件的剖面示意圖；
第3圖係根據本揭露內容各種觀點之另一實施例具有銲墊結構之半導體元件的剖面示意圖；
第4圖係根據本揭露內容各種觀點之再一實施例具有銲墊結構之半導體元件的剖面示意圖；
第5圖係根據本揭露內容各種觀點之又一實施例具有銲墊結構之半導體元件的剖面示意圖；以及
第6圖至第8圖係根據實施於第2圖至第5圖半導體元件的各種實施例之虛擬金屬介電層的示意概圖。
200．．．半導體元件
202．．．半導體基材
204．．．內層介電層
206．．．接觸
210a/210b/210c/210d/210e/210f/210g/210h/210i(M1/M2/M3/M4/M5/M6/M7/M8/M9)．．．金屬層
220．．．內金屬介電層
224．．．金屬線路
226．．．虛擬金屬線路
230．．．金屬介層窗
235．．．虛擬金屬介層窗
240．．．區域
245．．．金屬銲墊
248．．．金屬銲墊
250．．．金屬介層窗
252/262．．．保護層
260．．．銲墊
270．．．銲線組

Claims (11)

  1. 一種半導體元件，至少包含：一半導體基材，其中該半導體基材具有複數個微電子構件；一內連線結構形成於該半導體基材上，其中該內連線結構包括複數個金屬層及用以隔離該些金屬層之複數個內金屬介電層，該些金屬層包括一頂金屬層、一底金屬層、以及設於該頂金屬層與該底金屬層之間的至少二金屬層；複數個實際金屬介層窗形成於該些內金屬介電層之一或多者中，其中該些內金屬介電層係設於至少二金屬層之間；複數個虛擬金屬介層窗形成於該些內金屬介電層之一或多者中，其中該些內金屬介電層係設於該至少二金屬層之間；以及一銲墊結構，其中該銲墊結構係形成於該些虛擬金屬介層窗之正上方，且該些虛擬金屬介層窗與該些實際金屬介層窗共同建立之一介層窗密度，該介層窗密度是根據位於該銲墊結構正下方的該內連線結構之一區域計算，且該介層窗密度係大於1.5百分比。
  2. 根據申請專利範圍第1項所述之半導體元件，其中該至少二金屬層為複數個相鄰金屬層，該些相鄰金屬層之每一者包括一虛擬金屬特徵，該些相鄰金屬層之該些虛擬金屬特徵分別藉由該些虛擬金屬介層窗之一者耦接。
  3. 根據申請專利範圍第1項所述之半導體元件，其中該些金屬層包括與該頂金屬層相鄰之一第二頂金屬層，且該第二頂金屬層包括另一銲墊結構，該另一銲墊結構藉由複數個上金屬介層窗與該頂金屬層之該銲墊結構耦接。
  4. 根據申請專利範圍第1項所述之半導體元件，其中該至少二金屬層包括七金屬層，且該些虛擬金屬介層窗係設於該七金屬層之任二者之間。
  5. 一種半導體元件，至少包含：一半導體基材，其中該半導體基材具有複數個微電子構件；一內連線結構形成於該半導體基材上，其中該內連線結構包括一頂金屬層以及一底金屬層，且該頂金屬層包括一金屬銲墊；複數個實際金屬介層窗形成於該些內金屬介電層之一或多者中，其中該些內金屬介電層係設於至少二金屬層之間；複數個虛擬金屬介層窗形成於該些內金屬介電層之一或多者中，其中該些內金屬介電層係設於至少二金屬層之間；以及一銲墊結構，其中該銲墊結構係形成於該些虛擬金屬介層窗之正上方，且該些虛擬金屬介層窗與該些實際金屬介層窗共同建立之一介層窗密度，該介層窗密度是根據位於該銲墊結構正下方的該內連線結構之一區域計算，且該 介層窗密度係大於1.5百分比。
  6. 根據申請專利範圍第5項所述之半導體元件，更至少包含一銲墊形成於該頂金屬層上，且與該金屬銲墊耦接。
  7. 根據申請專利範圍第5項所述之半導體元件，其中該內連線結構更包括複數個實際金屬介層窗，該些虛擬金屬介層窗與該些實際金屬介層窗共同建立之一總介層窗密度，該總介層窗密度是根據位於該打線組與該覆晶組之一者正下方的該內連線結構之一區域計算，且該總介層窗密度係大於1.5百分比。
  8. 根據申請專利範圍第5項所述之半導體元件，其中該內連線結構更包括複數個實際金屬介層窗，該些虛擬金屬介層窗與該些實際金屬介層窗共同建立之一介層窗密度，該介層窗密度是根據位於該銲墊結構正下方的該內連線結構之一區域計算，且該介層窗密度係大於1.5百分比。
  9. 一種半導體元件之製造方法，至少包含：提供一半導體基材，其中該半導體基材具有複數個微電子構件；形成一內連線結構形成於該半導體基材上，其中該內連線結構包括複數個金屬層以及複數個內金屬介電層，該些金屬層包括一頂金屬層、一底金屬層、以及設於該頂金屬層與該底金屬層之間的至少二金屬層； 形成複數個實際金屬介層窗形成於該些內金屬介電層之一或多者中，其中該些內金屬介電層係設於至少二金屬層之間；形成複數個虛擬金屬介層窗於該些內金屬介電層之一或多者中，其中該些內金屬介電層係設於該至少二金屬層之間；以及形成一銲墊結構，其中該銲墊結構係形成於該些虛擬金屬介層窗之正上方，且該些虛擬金屬介層窗與該些實際金屬介層窗共同建立之一介層窗密度，該介層窗密度是根據位於該銲墊結構正下方的該內連線結構之一區域計算，且該介層窗密度係大於1.5百分比。
  10. 根據申請專利範圍第9項所述之半導體元件之製造方法，其中形成該銲墊結構之步驟包括形成一銲墊於該頂金屬層上，該銲墊與該頂金屬層之一金屬銲墊耦接，且該半導體元件之製造方法更至少包含形成一打線組以及一覆晶組之一者於該銲墊上。
  11. 根據申請專利範圍第9項所述之半導體元件之製造方法，其中該至少二金屬層包括七金屬層，且該些虛擬金屬介層窗係設於該七金屬層之任二者之間。
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