CN102064155A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN102064155A
CN102064155A CN2010101702323A CN201010170232A CN102064155A CN 102064155 A CN102064155 A CN 102064155A CN 2010101702323 A CN2010101702323 A CN 2010101702323A CN 201010170232 A CN201010170232 A CN 201010170232A CN 102064155 A CN102064155 A CN 102064155A
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metal
semiconductor device
those
metal level
dummy
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CN102064155B (zh
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陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及一种半导体器件及其制造方法，该半导体器件包括一半导体基材，其中此半导体基材具有多个微电子构件；一内连线结构形成于前述半导体基材上，其中此内连线结构包括多个金属层及用以一一隔离前述金属层的多个内金属介电层，前述金属层包括一顶金属层；多个虚拟金属介层窗形成于至少二金属层之间并设于前述内连线结构的一区域内；以及一焊垫结构，其中此焊垫结构形成于前述顶金属层的正上方，使此焊垫结构对准于前述内连线结构的上述区域。

Description

半导体器件及其制造方法
技术领域
本发明是有关于一种半导体器件，特别是有关于一种半导体器件的焊垫结构。
背景技术
在半导体技术中，晶片(wafer)会经历各种工艺以形成集成电路。集成电路的焊线路径是由内连线结构所提供，其中内连线结构可包括多个金属层，而这些金属层一一由介垫层绝缘。焊垫一般形成于内连线结构上，用以进行晶片级测试以及芯片封装(例如打线(wire bonding)以及芯片倒装(flip-chip))。在先进技术工艺(例如45纳米、32纳米以及以下)中，在内连线结构中使用低介电常数(low-k)的介电材料，可提升其效能。然而，上述低介电常数的介电材料的机械强度性质较弱，特别是金属层受到高应力(stress)的区域，例如焊垫下方的区域，会造成剥离或龟裂。是以，金属层的剥离或龟裂会导致器件效能不佳，而且在一些情形下会导致器件失效。
发明内容
因此，本发明的一目的是在提供一种半导体器件，其包括一半导体基材，此半导体基材具有多个微电子构件；一内连线结构形成于前述半导体基材上，其中此内连线结构包括多个金属层及用以隔离前述金属层的多个内金属介电层，前述金属层包括一顶金属层、一底金属层、以及设于顶金属层与底金属层之间的至少二金属层；多个虚拟金属介层窗形成于前述内金属介电层的一或多个中，其中前述内金属介电层设于前述至少二金属层之间；以及一焊垫结构，其中此焊垫结构形成于前述虚拟金属介层窗的正上方。
其次，本发明的另一目的是在提供一种半导体器件的制造方法，其包括提供一半导体基材，其中此半导体基材具行多个微电子构件；形成一内连线结构形成于前述半导体基材上，其中此内连线结构包括多个金属层以及多个内金属介电层，前述金属层包括一顶金属层、一底金属层、以及设于顶金属层与底金属层之间的至少二金属层；形成多个虚拟金属介层窗于前述内金属介电层的一或多个中，其中前述内金属介电层设于至少二金属层之间；以及形成一焊垫结构，其中此焊垫结构形成于前述虚拟金属介层窗的正上方。
再者，本发明的又一目的是在提供一种半导体器件，其包括此半导体基材具有多个微电子构件；一内连线结构形成于前述半导体基材上，其中此内连线结构包括一顶金属层以及一底金属层，且此顶金属层包括一金属焊垫；多个虚拟金属介层窗形成于前述内金属介电层的一或多个中，其中前述内金属介电层设于前述顶金属层与底金属层之间，前述虚拟金属介层窗位于前述顶金属层的金属焊垫的下方，前述虚拟金属介层窗建立一介层窗密度，此介层窗密度是根据位于前述顶金属层的金属焊垫正下方的内连线结构的一区域计算。
应用本发明的半导体器件及其制造方法，其是在焊垫结构或金属焊垫正下方的区域内的较上层的金属层以及内金属介电层，设置虚拟金属线路以及虚拟金属介层窗，可用于例如调整局部图案密度，以获致更佳的研磨效果，并可强化前述区域内的内金属介电层的机械强度，以降低中间金属层的界面产生薄膜剥离、龟裂及/或分层的风险。
附图说明
为让本发明的上述和其它目的、特征、优点与实施例能更明显易懂，所附附图的详细说明如下：
图1是根据本发明的各种观点的半导体器件的制造方法流程图；
图2是根掘本发明各种观点的一实施例具有焊垫结构的半导体器件的剖面示意图；
图3是根据本发明各种观点的另一实施例具有焊垫结构的半导体器件的剖面示意图；
图4是根据本发明各种观点的再一实施例具有焊垫结构的半导体器件的剖面示意图；
图5是根据本发明各种观点的又一实施例具有焊垫结构的半导体器件的剖面示意图；以及
图6至图8是根掘实施于图2至图5半导体器件的各种实施例的虚拟金属介电层的示意概图。
【主要器件符号说明】
100：方法
102/104/106/108：方块
200/300/400/500：半导体器件
202：半导体基材
204：内层介电层
206：接触
210a/210b/210c/210d/210e/210f/210g/210h/210i(M1/M2/M3/M4/M5/M6/M7/M8/M9)：金属层
220：内金属介电层
224：金属线路
226/602/604/702/704/802/804：虚拟金属线路
230：金属介层窗
235/610/710/712/810/811/812/813：虚拟金属介层窗
240/310/410：区域
245：金属焊垫
248：金属焊垫
250：金属介层窗
252/262：保护层
260：焊垫
270：焊线组
420：打线焊块结构
510：芯片倒装组
512：凸块下金属结构
514：焊球
600/700/800：示意概图
615/619/715/719/815/819：宽度
617/717/817：重叠
621/623/721/723/725/727/821/823/825/827：距离
具体实施方式
可以理解的是，以下揭露内容提供许多不同的实施例或例示，以实施本发明的不同特征。以下所述的构件与排列的特定例示是用以简化本发明。当然，这些例示仅为举例说明，并非用以限制本发明。此外，本发明可能会在各种例子中重复使用图号及/或字母符号。此重复使用的目的是为了简要清楚说明，其本身并不指定所讨论的各种实施例及/或配置之间的关系。再者，举例而言，说明书中，第一特征形成于第二特征上或其上方，可能包括第一特征以直接接触的方式形成于第二特征上的实施例，也可能包括第一特征与第二特征之间形成其它额外特征、以至于第一特征以非直接接触的方式形成于第二特征上的实施例。
请参阅图1，其是根据本发明的各种观点说明半导体器件的制造方法100。此方法100自方块102开始，其是提供一半导体基材，其中此半导体基材具有多个微电子构件。接着，此方法100继续进行至方块104，其是形成一内连线结构形成于前述半导体基材上。此内连线结构包括多个金属层以及多个内金属介电层。前述金属层包括一顶金属层、一底金属层、以及设于顶金属层与底金属层之间的至少二金属层。之后，此方法100继续进行至方块106，其是形成多个虚拟金属介层窗于前述内金属介电层的一或多个中，其中前述内金属介电层设于至少二金属层之间。然后，此方法100继续进行至方块108，其是形成一焊垫结构，其中此焊垫结构形成于前述虚拟金属介层窗的正上方。实施上述方法100可制造以下所述的半导体器件的各种实施例。
请参阅图2，其是根据本发明的各种观点说明具有焊垫结构的半导体器件200的剖面示意图。在一实施例中，此半导体器件200可根据图1的方法100制造。可以理解的是，此半导体器件200包括各种特征与结构，但此处是加以简化，以更加了解本发明的发明概念。半导体器件200包括半导体基材202，例如结晶结构的硅基材。此半导体器件200亦可包括其它元素型半导体，例如锗。另一种方式，此半导体器件200亦可选择性包括化合物型半导体，例如碳化硅、砷化镓、砷化铟以及磷化铟。此外，此半导体器件200亦可选择性包括通过外延成长工艺(epitaxial growth process)形成的外延层(epitaxial layer)。此半导体器件200还可至少包含多个隔离特征(图未绘示)，例如浅沟渠隔离(shallow trench isolation；STI)特征或区域性硅氧化(local oxidation of silicon；LOCOS)特征。
隔离特征可定义并隔离出不同微电子构件(图未绘示)的有源区(activeregions)，前述微电子构件例如晶体管(例如金属氧化物半导体场效晶体管(metal oxide semiconductor field effect transistor；MOSFET)、互补式金属氧化物半导体(complementary metal oxide semiconductor；CMOS)晶体管、双载子接合晶体管(bipolar junction transistor；BJT)、高压晶体管、高频晶体管等)、电阻、二极管、电容以及其它适合的构件。因此，可进行熟悉此项技艺人士可以使用的各种工艺，例如沉积、蚀刻、离子植入、光刻、回火以及其它适合的工艺，以形成微电子构件。微电子构件经由内连线连接而形成集成电路，例如逻辑器件、存储元件(例如静态随机存取内存(SRAM))、射频(RF)器件、输入/输出(input/output；I/O)器件、系统单芯片(system-on-chip；SoC)器件、上述的任意组合以及其它适合形式的已知器件。
此半导体器件200还包括形成于其上的内层介电(inter-layer dielectric；ILD)层204，其中此半导体器件200包括微电子构件。内层介电层204可包括氧化硅、氮氧化硅、或其它低介电常数材料。内层介电层204可通过化学气相沉积(chemical vapor deposition；CVD)法、高密度等离子化学气相沉积(high densityplasma CVD；HDP-CVD)法、旋涂(spin-on)法、物理气相沉积(physical vapordeposition；PVD；或溅镀(sputtering))法、或其它适合的技术而形成。应留意的是，在形成内层介电层204之前，可形成例如接触蚀刻终止层(contact etchstop layer；CESL)的应力层于半导体基材202上。此半导体器件200还包括形成于内层介电层204上的多个接触206(亦称为第一接触)。前述接触206可通过对内层介电层204进行第一图案化及蚀刻步骤而形成多个沟渠。前述沟渠可通过沉积例如氮化钛(TiN)的金属阻障层而进行填充，之后沉积例如钨(W)的接触插塞层于金属阻障层上。在一些实施例中，钨接触插塞的金属阻障层可包括钛/氮化钛(Ti/TiN)。在一些实施例中，铜(Cu)接触插塞的金属阻障层可包括钽/氮化钽(Ta/TaN)。接触206可提供半导体基材202上形成的各种微电子构件的电性连接。
此半导体器件200还包括内连线结构。此内连线结构包括多个金属层210a至金属层210i，以提供各种微电子构件之间以及金属层本身之间的内连线(打线)。可以理解的是，金属层的数量端视特定半导体器件的设定而有所变动。在发明的实施例中，前述金属层210a至金属层210i包括九层金属层，即底金属层210a(M1)、顶金属层210i(M9)、以及介于底金属层210a(M1)与顶金属层210i(M9)之间的金属层210b(M2)至金属层210h(M8)。前述金属层210a(M1)至金属层210i(M9)可包括由导体材料形成的线路，而此导体材料可例如铝、铝/硅/铜合金、钛、氮化钛、钨、复晶硅、金属硅化物、或上述的任意组合。另一种方式，前述金属层210a(M1)至金属层210i(M9)可包括由导体材料形成的线路，而此导体材料可例如铜、铜合金、钛、氮化钛、钽、氮化钽、钨、复晶硅、金属硅化物、或上述的任意组合。
前述金属层210a(M1)至金属层210i(M9)可通过多个内金属介电(inter-metal dielectric；IMD)层220而互相绝缘。前述内金属介电层220可包括低介电常数材料。在一些实施例中，前述内连线结构中不同层的内金属介电层220可由不同介电材料而形成。目前已观察到，以低介电常数(low-K；LK)材料、超低介电常数(extreme low-K；ELK)材料、及/或极低介电常数(extra low-K；XLK)材料会提升线路效能。前述介电材料是根据介电常数进行分类。举例而言，低介电常数材料是指介电常数低于约3.5的材料，而以介电常数低于约3.0的材料为较佳。超低介电常数材料是指介电常数低于约2.9的材料，而以介电常数低于约2.6的材料为较佳。极低介电常数材料是指介电常数低于约2.4的材料。可以理解的是，上述分类仅为例示，根据材料的介电常数的其它分类亦可使用。前述LK、ELK及/或XLK介电材料可至少包含氮化硅、氮氧化硅、旋涂式玻璃(spin-on glass；SOG)、未掺杂硅酸盐玻璃(undoped silicate glass；USG)、氟化硅玻璃(fluorinated silica glass；FSG)、碳掺杂氧化硅(例如SiCOH)、含碳材料、黑钻石(Black
Figure GSA00000099629900061
Applied Materials of Santa Clara，California)、干凝胶(Xerogel)、气凝胶(Aerogel)、非晶系氟化碳(amorphousfluorinated carbon)、聚对二甲苯(Parylene)、苯并环丁烯(bis-benzocyclobutenes；BCB)、掺氟的聚对二甲苯醚(Flare)、芳香族碳氢化合物(SiLK；Dow Chemical，Midland，Michigan)、聚亚酰胺(polyimide)、其它适合的多孔性高分子材料、其它适合的介电材料、及/或上述的任意组合。内金属介电层220可利用旋涂(spin-on)法、化学气相沉积(CVD)法、物理气相沉积(PVD)法、或原子层沉积(atomic layer deposition；ALD)法等技术形成。
虽然前述LK、ELK及XLK介电材料可提升线路效能，不过已观察到上述材料(例如多孔性材料)呈现的机械强度较差，也因此在受到各种半导体工艺引起的应力时，会导致剥离、龟裂及/或分层(delaminate)。此外，根据应力分布的分析，已观察到越高的金属层会比越低的金属层受到更高的应力。举例而言，在芯片封装时，位于焊垫结构、接合(bonding)结构、或焊球结构正下方的区域240(虚线所示的区域)内的较上层的金属层210d至210i(M4以上)以及内金属介电层220，会受到较高的机械应力。因此，相较于内连线结构的其它区域，区域240内出现剥离、龟裂及/或分层的风险会较高。另外，中间金属层(M4/M5，或M5/M6)的界面产生薄膜龟裂的风险较高。故此，以下揭露的特征及结构可提供节省成本又有效率的技术，以强化区域240内的内金属介电层220的机械强度。然而，可以理解的是，以下揭露的特征及结构亦可用于强化或巩固内连线结构的其它区域，及/或半导体器件200中可应用的其它介电层。
金属层210a至210i及内金属介电层220可于例如金属镶嵌(damascene)工艺或光刻/等离子蚀刻工艺等集成电路工艺中形成。底金属层210a(M1)可包括金属线路224，其中此金属线路224与多个接触206耦接，以连接至半导体基材202中形成的微电子构件。底金属层210a(M1)还可包括多个虚拟金属线路226，其中前述虚拟金属线路226并未电性连接至任何具有功能的线路及/或焊垫。不过，前述虚拟金属线路226可用于例如调整局部图案密度，以获致更佳的研磨效果。金属层220b至220g(M2-M7)亦可包括金属线路224与虚拟金属线路226。内连线结构又可包括在前述内金属介电层220内设置的金属介层窗230，以连接邻近金属层220a至220i的金属线路224。内连线结构更可包括多个虚拟金属介层窗235，其中虚拟金属介层窗235设于区域240内的内金属介电层220中。前述虚拟金属介层窗235并未电性连接至任何具有功能的线路及/或焊垫。不过，前述虚拟金属介层窗235可用于连接邻近金属层220d至220g(例如M4/M5、M5/M6以及M6/M7)的虚拟金属线路226。故此，前述虚拟金属介层窗235可强化区域240内的内金属介电层220的机械强度。
在一实施例中，前述虚拟金属介层窗235与实际金属介层窗230(位于区域240内一或多层的内金属介电层220中)可共同建立约1.5百分比的介层窗密度。以下将详述根掘焊垫结构、接合结构、或焊球结构，以局部计算出介层窗密度。在另一实施例中，前述虚拟金属介层窗235与实际金属介层窗230(位于区域240内一或多层的内金属介电层220中)可共同建立约3.0百分比的介层窗密度。在其它实施例中，前述金属层210d(M4)与金属层210e(M5)之间可插入虚拟金属介层窗235，以在区域240内的内金属介电层220(介于金属层210d(M4)与金属层210e(M5)之间)中建立大于1.5百分比的介层窗密度。应留意的是，已经找出特定的介层窗密度百分比，以有效改善区域240内的内金属介电层220的机械强度。然而，可以理解的是，根据设计需求及/或可取得的封装覆盖尺寸(footprint)，虚拟金属介层窗可以使用其它百分比的介层窗密度。
顶金属层210i(M9)及金属层210h(M8)包括双重金属焊垫配置。举例而言，金属层210h(M8)包括金属焊垫245，而顶金属层210i(M9)包括金属焊垫248。金属焊垫245可包括与金属焊垫248类似的形状及尺寸。金属焊垫245与金属焊垫248是通过设置于内金属介电层220中的多个金属介层窗250而彼此耦接。在其它实施例中，内连线结构可包括单一金属焊垫配置，其中此金属焊垫只形成于顶金属层210i(M9)中。同样地，前述金属层210g(M7)与金属层210h(M8)之间可插入虚拟金属介层窗235。
此半导体器件200又可包括保护层252，此保护层252是形成于顶金属层210i(M9)上，以覆盖并保护内连线结构。保护层252可包括氧化硅、氮化硅、氮氧化硅、或上述的任意组合。此保护层252可利用化学气相沉积(CVD)法、旋涂(spin-on)法、或其它适合的技术形成。
此半导体器件200还可包括焊垫260。焊垫260可形成于顶金属层210i(M9)的金属焊垫248上。焊垫260可配置成提供内连线结构电性连接，以进行晶片级测试、打线、或芯片封装。焊垫260可利用已知工艺形成于保护层252内。举例而言，可对保护层252进行蚀刻工艺，形成开口以暴露出顶金属层210i(M9)的金属焊垫248。接着，可沉积导体材料层于保护层252上并填满上述开口。然后，可对导体材料层进行图案化以形成焊垫260。焊垫260可包括导电材料，而此导电材料可例如铝、铝合金、铜、铜合金、或上述的任意组合。为了获致适当的接合性质，焊垫260的轮廓可具有适合的阶梯高度。
保护层262可形成于保护层252上，而保护层262经图案化后可暴露出焊垫260。保护层262可包括氧化硅、氮化硅、氮氧化硅、或上述的任意组合。此保护层262可利用化学气相沉积(CVD)法、旋涂(spin-on)法、或其它适合的技术形成。此半导体器件200又包括焊线组270。焊线组270可形成为与焊垫260接触。焊线组270可利用例如热超音波接合(thermosonic bonding)及热压接合(thermocompression bonding)等已知打线(wire bonding)技术而形成。大体上，打线是运用机械力、热能以及声能，将焊线接至焊垫260。就不同的接合技术而言，焊垫260的厚度可提供适当的接合性质。焊线组270使半导体器件200得以与外部零件连接。
应当注意的是，可根据不同结构，而局部计算出前述区域240内的虚拟金属介层窗235的介层窗密度。在一实施例中，焊垫260下方的局部区域可用于计算出介层窗密度。因此，介层窗密度可表示为(介层窗面积/焊垫面积)。在其它实施例中，顶金属层210i(M9)的金属焊垫248下方的局部面积可用来计算介层窗密度。所以介层窗密度可表示为(介层窗面积/金属焊垫面积)。
请参阅图3，其是根据本发明的各种观点说明具有焊垫结构的半导体器件300的剖面示意图。在一实施例中，半导体器件300可根据图1的方法100制造。此半导体器件300可类似于图2的半导体器件200，但以下所述的相异除外。为了简化及清楚之故，图2与图3的相似特征则以相同图号来表示。半导体器件300包括多个虚拟金属介层窗235，其中虚拟金属介层窗235设于区域310内。区域310类似于图2的区域240，不过区域310还延伸到下方的金属层210a(M1)至金属层210c(M3)。因此，顶金属层210i(M9)的金属焊垫248或焊垫260正下方的金属层210a(M1)至金属层210g(M7)之间可捅入虚拟金属介层窗235。从而，可局部计算出金属焊垫248或焊垫260区域下方的介层窗密度。举例而言，在一实施例中，虚拟金属介层窗235与实际金属介层窗230(位于区域310内一或多层的内金属介电层220中)可共同建立约1.5百分比的介层窗密度。在另一实施例中，前述虚拟金属介层窗235与实际金属介层窗230(位于区域310内一或多层的内金属介电层220中)可共同建立约3.0百分比的介层窗密度。在其它实施例中，前述金属层210d(M4)与金属层210e(M5)之间可插入虚拟金属介层窗235，以在区域310内的内金属介电层220(介于金属层210d(M4)与金属层210e(M5)之间)中建立大于1.5百分比的介层窗密度。
在较低的金属层之间可设置额外的虚拟金属介层窗，以进一步改善区域310内的内金属介电层220的机械强度。应留意的是，半导体器件300可选择性运用单一的金属焊垫配置，因此虚拟金属介层窗亦可插入金属层210g(M7)与金属层210h(M8)之间。
请参阅图4，其是根据本发明的各种观点说明具有焊垫结构的半导体器件400的剖面示意图。在一实施例中，半导体器件400可根据图1的方法100制造。此半导体器件400可类似于图2的半导体器件200，但以下所述的相异处除外。为了简化及清楚之故，图2与图4的相似特征则以相同图号来表示。半导体器件400包括多个虚拟金属介层窗235，其中虚拟金属介层窗235设于区域410内。区域410类似于图2的区域240，不过区域410设于焊线组270的打线焊块(wire bump)结构420的正下方。因此，虚拟金属介层窗235设于焊线组270的打线焊块结构420正下方的金属层210d(M4)至金属层210g(M7)之间。从而，可局部计算出打线焊块结构420区域下方的介层窗密度。举例而言，打线焊块结构具有直径D，因此打线焊块结构下方的局部区域可以表示为(D2/4*π)。
在一实施例中，虚拟金属介层窗235与实际金属介层窗230(位于区域410内一或多层的内金属介电层220中)可共同建立约1.5百分比的介层窗密度。在另一实施例中，前述虚拟金属介层窗235与实际金属介层窗230(位于区域410内一或多层的内金属介电层220中)可共同建立约3.0百分比的介层窗密度。在其它实施例中，前述金属层210d(M4)与金属层210e(M5)之间可捅入虚拟金属介层窗235，以在区域410内的内金属介电层220(介于金属层210d(M4)与金属层210e(M5)之间)中建立大于1.5百分比的介层窗密度。应留意的是，半导体器件400可选择性运用单一的金属焊垫配置，因此虚拟金属介层窗亦可插入金属层210g(M7)与金属层210h(M8)之间。再者，虽然此处所示的虚拟金属介层窗235设于金属层210d(M4)与金属层210g(M7)之间，但可以理解的是，虚拟金属介层窗亦可额外设置于较低的金属层210a(M1)至金属层210c(M3)之间，类似于图3所揭示的实施例。
请参阅图5，其是根据本发明的各种观点说明具有焊垫结构的半导体器件500的剖面示意图。在一实施例中，半导体器件500可根据图1的方法100制造。此半导体器件500可类似于图2的半导体器件200，但以下所述的相异处除外。为了简化及清楚之故，图2与图5的相似特征则以相同图号来表示。半导体器件500包括芯片倒装组510，其中芯片倒装组510是取代图2的焊线组270。芯片倒装组510可使正面朝下(face-down)的半导体器件500直接电性连接至线路板或基材上。芯片倒装组510是已知芯片封装的一种型式，故此处不另赘述。芯片倒装组510可包括于焊垫260上形成的凸块下金属(under bumpmetallization；UBM)结构512。凸块下金属结构512可包括不同材料层，其中这些材料层可以适当地将凸块下金属结构512附着至焊垫260与保护层262，可保护下方的材料，并使焊球514润湿。焊球514可利用蒸镀(evaporation)法、电镀(electroplating)、印刷(printing)法、喷墨印刷(jetting)法、凸块焊接(studbumping)法或其它适合的技术，形成于凸块下金属结构512上。虽然此半导体器件500所示的虚拟金属介层窗235设于区域240内，可以理解的是，区域240亦可如图3揭示的实施例，延伸至包括较低的金属层210a(M1)至金属层210d(M4)。
请参阅图6，其是说明一实施例的虚拟金属介层窗的示意概图600，此虚拟金属介层窗可分别实施于图2至图5的各种半导体器件200、半导体器件300、半导体器件400以及半导体器件500中。在此实施例中，不同的具体尺寸是关于32纳米技术节点工艺。可以理解的是，亦可使用其它尺寸以实施其它技术节点工艺(例如60纳米、45纳米等)。此示意概图600可用于产生具有虚拟金属介层窗的设计布局。此示意概图600显示二邻近金属层(例如图2至图5的金属层210a至金属层210i之间)。承上所论，邻近金属层的每一个包括虚拟金属线路602与虚拟金属线路604，其中虚拟金属线路602与虚拟金属线路604并未电性连接至任何具有功能的线路及/或焊垫。虚拟金属线路602与虚拟金属线路604可通过虚拟金属介层窗610而彼此连接。前述虚拟金属线路602可具有正方形外观，其宽度615约0.8微米(μm)。虚拟金属线路604的外型与尺寸可与虚拟金属线路602相似。虚拟金属线路602与虚拟金属线路604可具有约0.7微米(μm)的重叠617。虚拟金属介层窗610可具有正方形外观，其宽度619约0.35微米(μm)。虚拟金属介层窗610与虚拟金属线路602之间相隔距离621及距离623，其中距离621及距离623各约0.175微米(μm)。应当留意的是，虚拟金属介层窗与虚拟金属线路可实施成其它外形，例如椭圆形、圆形、矩形、其它多边形以及不规则形。
请参阅图7，其是说明一实施例的虚拟金属介层窗的示意概图700，此虚拟金属介层窗可分别实施于图2至图5的各种半导体器件200、半导体器件300、半导体器件400以及半导体器件500中。在此实施例中，不同的具体尺寸是关于32纳米技术节点工艺。可以理解的是，亦可使用其它尺寸以实施其它技术节点工艺(例如60纳米、45纳米等)。此示意概图700可用于产生具有虚拟金属介层窗的设计布局。此示意概图700显示二邻近金属层(例如图2至图5的金属层210a至金属层210i之间)。承上所论，邻近金属层的每一个包括虚拟金属线路702与虚拟金属线路704，其中虚拟金属线路702与虚拟金属线路704并未电性连接至任何具有功能的线路及/或焊垫。虚拟金属线路702与虚拟金属线路704可通过虚拟金属介层窗710与虚拟金属介层窗712而彼此连接。前述虚拟金属线路702可具有正方形外观，其宽度715约0.8微米(μm)。虚拟金属线路704的外型与尺寸可与虚拟金属线路702相似。虚拟金属线路702与虚拟金属线路704可具有约0.7微米(μm)的重叠717。虚拟金属介层窗710与虚拟金属介层窗712可具有正方形外观，其宽度719约0.14微米(μm)。虚拟金属介层窗710与虚拟金属线路704之间相隔距离721及距离723，其中距离721及距离723各约0.065微米(μm)。虚拟金属介层窗712可与虚拟金属介层窗710相隔距离725及距离727，其中距离725及距离727各约0.29微米(μm)。应当留意的是，虚拟金属介层窗与虚拟金属线路可实施成其它外形，例如椭圆形、圆形、矩形、其它多边形以及不规则形。
请参阅图8，其是说明一实施例的虚拟金属介层窗的示意概图800，此虚拟金属介层窗可分别实施于图2至图5的各种半导体器件200、半导体器件300、半导体器件400以及半导体器件500中。在此实施例中，不同的具体尺寸是关于32纳米技术节点工艺。可以理解的是，亦可使用其它尺寸以实施其它技术节点工艺(例如60纳米、45纳米等)。此示意概图800可用于产生具有虚拟金属介层窗的设计布局。此示意概图800显示二邻近金属层(例如图2至图5的金属层210a至金属层210i之间)。承上所论，邻近金属层的每一个包括虚拟金属线路802与虚拟金属线路804，其中虚拟金属线路802与虚拟金属线路804并未电性连接至任何具有功能的线路及/或焊垫。虚拟金属线路802与虚拟金属线路804可通过虚拟金属介层窗810、虚拟金属介层窗811、虚拟金属介层窗812与虚拟金属介层窗813而彼此连接。前述虚拟金属线路802可具有正方形外观，其宽度815约0.8微米(μm)。虚拟金属线路804的外型与尺寸可与虚拟金属线路802相似。虚拟金属线路802与虚拟金属线路804可具有约0.7微米(μm)的重叠817。虚拟金属介层窗810、虚拟金属介层窗811、虚拟金属介层窗812与虚拟金属介层窗813可具有正方形外观，其宽度819约0.12微米(μm)。虚拟金属介层窗810与虚拟金属线路804之间相隔距离821及距离823，其中距离821及距离823各约0.14微米(μm)。虚拟金属介层窗810、虚拟金属介层窗811、虚拟金属介层窗812与虚拟金属介层窗813彼此相隔距离825及距离827，其中距离825及距离827各约0.18微米(μm)。应当留意的是，虚拟金属介层窗与虚拟金属线路可实施成其它外形，例如椭圆形、圆形、矩形、其它多边形以及不规则形。
以上已概述数个实施例的特征，可让本发明所属技术领域的技术人员更加了解本发明。本发明所属技术领域的技术人员应可理解，其可轻易利用本发明作为基础，以设计或修改其它工艺或结构，而实现与此处所述的实施例所述相同的目的及/或达成相同的优点。可以理解的是，使用上述例示工艺步骤的各种不同的组合，可以结合使用或同时使用。其次，在某些实施例说明及讨论的特征亦可与其它实施例论及的特征结合。故此，本发明所属技术领域的技术人员应可理解，上述均等的架构并不脱离本发明的精神和范围，且此等人员在不脱离本发明的精神和范围下，可作各种的更动、替换、与润饰，因此本发明的保护范围当视权利要求书所界定的范围为准。举例而言，上述实施例可利用各任何芯片封装工艺，其中可包括但不限于打线、芯片倒装、芯片接合、及焊锡凸块接合(solder bump bonding)。此外，虽然上述图6至图8揭露的实施例显示特定数量的虚拟介层窗，以连接邻近金属层的虚拟金属线路，但可以理解的是，可变化介层窗的数量及位置，以改善内连线结构的介电层的机械强度。

Claims (14)

1.一种半导体器件，其特征在于，至少包含：
一半导体基材，其中该半导体基材具有多个微电子构件；
一内连线结构形成于该半导体基材上，其中该内连线结构包括多个金属层及用以隔离该些金属层的多个内金属介电层，该些金属层包括一顶金属层、一底金属层、以及设于该顶金属层与该底金属层之间的至少二金属层；
多个虚拟金属介层窗形成于该些内金属介电层的一或多个中，其中该些内金属介电层设于该至少二金属层之间；以及
一焊垫结构，其中该焊垫结构形成于该些虚拟金属介层窗的正上方。
2.根据权利要求1所述的半导体器件，其特征在于，该至少二金属层为多个相邻金属层，该些相邻金属层的每一个包括一虚拟金属特征，该些相邻金属层的该些虚拟金属特征分别通过该些虚拟金属介层窗的一个耦接。
3.根据权利要求1所述的半导体器件，其特征在于，该焊垫结构形成于该顶金属层中。
4.根据权利要求1所述的半导体器件，其特征在于，该些金属层包括与该顶金属层相邻的一第二顶金属层，且该第二顶金属层包括另一焊垫结构，该另一焊垫结构通过多个上金属介层窗与该顶金属层的该焊垫结构耦接。
5.根据权利要求1所述的半导体器件，其特征在于，该至少二金属层包括七金属层，且该些虚拟金属介层窗设于该七金属层的任意两个之间。
6.根据权利要求5所述的半导体器件，其特征在于，该些虚拟金属介层窗设于该七金属层的五个之间，且该七金属层的该五个邻近该顶金属层。
7.根据权利要求1所述的半导体器件，其特征在于，该些内金属介电层的一介电常数不大于2.5。
8.根据权利要求1所述的半导体器件，其特征在于，还至少包含：
一焊线组以及一芯片倒装组的一个与该焊垫结构耦接。
9.根据权利要求1所述的半导体器件，其特征在于，该内连线结构还包括多个实际金属介层窗，该些虚拟金属介层窗与该些实际金属介层窗共同建立的一介层窗密度，该介层窗密度是根据位于该焊垫结构正下方的该内连线结构的一区域计算，且该介层窗密度大于1.5百分比。
10.一种半导体器件的制造方法，其特征在于，至少包含：
提供一半导体基材，其中该半导体基材具有多个微电子构件；
形成一内连线结构形成于该半导体基材上，其中该内连线结构包括多个金属层以及多个内金属介电层，该些金属层包括一顶金属层、一底金属层、以及设于该顶金属层与该底金属层之间的至少二金属层；
形成多个虚拟金属介层窗于该些内金属介电层的一或多个中，其中该些内金属介电层设于该至少二金属层之间；以及
形成一焊垫结构，其中该焊垫结构形成于该些虚拟金属介层窗的正上方。
11.根据权利要求10所述的半导体器件的制造方法，其特征在于，形成该焊垫结构的步骤与形成该内连线结构的该顶金属层的步骤是在一相同工艺中进行。
12.根据权利要求10所述的半导体器件的制造方法，其特征在于，形成该焊垫结构的步骤包括形成一焊垫于该顶金属层上，该焊垫与该顶金属层的一金属焊垫耦接，且该半导体器件的制造方法还至少包含形成一打线组以及一芯片倒装组的一个于该焊垫上。
13.根据权利要求10所述的半导体器件的制造方法，其特征在于，该至少二金属层包括七金属层，且该些虚拟金属介层窗设于该七金属层的任意两个之间。
14.根据权利要求10所述的半导体器件的制造方法，其特征在于，形成该内连线结构的步骤还包括形成多个实际金属介层窗于该些内金属介电层的一或多个中，该些虚拟金属介层窗与该些实际金属介层窗共同建立一介层窗密度，该介层窗密度是根据位于该焊垫结构正下方的该内连线结构的一区域计算，且该介层窗密度大于1.5百分比。
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