CN101504935B - 焊垫结构 - Google Patents

焊垫结构 Download PDF

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Publication number
CN101504935B
CN101504935B CN2009100004232A CN200910000423A CN101504935B CN 101504935 B CN101504935 B CN 101504935B CN 2009100004232 A CN2009100004232 A CN 2009100004232A CN 200910000423 A CN200910000423 A CN 200910000423A CN 101504935 B CN101504935 B CN 101504935B
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conductive
conductive layer
layer
liner
dielectric
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CN101504935A (zh
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郑心圃
刘豫文
蔡豪益
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种焊垫结构，包括两个导电层和设置在该两个导电层之间的连接层。连接层包括邻接的导电结构。在一个实施例中，邻接导电结构为导电材料的固体层。在另一实施例中，邻接导电结构为例如包括矩阵配置或多个导电条纹的导电网络。至少一个电介质衬垫可以设置在该导电网络中。在一个实施例中，连接层的导电密度位于大约20％到100％之间。

Description

焊垫结构
技术领域
本发明通常涉及集成电路，尤其涉及一种焊垫结构。
背景技术
集成电路通常形成在衬底例如半导体晶片上。焊垫被包含在衬底上，焊垫向集成电路器件提供接触面，藉此可以实现与集成电路器件的电连接。传统工艺利用焊垫可以用来提供从封装端子到集成电路的连接，传统工艺例如是热压或者热超声线焊接、倒装晶片(flip chip)技术以及本领域的其他公知技术。
互连技术能够引起对焊垫结构及周围区域的机械应力，例如从引线接合(wire bonding)工艺中球焊点或楔焊点的位置或者从倒装晶片技术中的凸点(bump)到焊垫上。此外，在电测试工序中，为了分析集成电路器件，焊垫可以用于提供到底层集成电路器件的连接。在测试工序中，测试探针的接触也能够引起对焊垫结构的机械应力。从焊接、电学测试以及其他可能的应力源产生的应力可以导致对焊垫结构以及底层的损坏。例如，可能产生的损坏的种类包括裂化和解层(delayering)。由于位于焊垫区域下部的层，例如具有低介电常数的层间电介质(interlayer dielectric)变得越来越易碎，因此应力成为半导体技术工艺中尤其关键的因素。
由此，现有技术亟需一种改善的焊垫结构。
发明内容
鉴于上述问题，本发明的实施例提供了一种器件，包括第一导电层；位于所述第一导电层上的第二导电层；以及位于所述第二导电层上的焊垫。连接层设置在所述第一导电层与所述第二导电层之间，其中所述连接层包括邻接导电结构。在一个实施例中，该连接层完全为导电材料(例如导电垫或者固体层)、在一个实施例中，所述邻接导电结构包括矩阵配置的导电材料。至少一个衬垫可以设置在所述邻接导电结构(例如矩阵)中。在一个实施例中，衬垫包括电介质材料。在进一步的实施例中，复数个导电塞形成在所述衬垫中。在一个实施例中，提供有连续导电结构，并且一个或多个衬垫可以设置在该连续导电结构中。
本发明的实施例还提供了一种器件，包括衬底；形成在所述衬底上的第一导电层；以及形成在所述第一导电层上的第二导电层。中间层设置在所述第一导电层与所述第二导电层之间，并电连接所述第一导电层与所述第二导电层。所述中间层的导电密度约大于20％，并且所述中间层包括连续的导电材料结构。在一个实施例中，所述连续导电结构可以是矩阵。在一个实施例中，所述中间层的导电密度位于20％到100％之间。
此外，本发明的实施例还提供了一种焊垫结构的形成方法。所述方法包括：形成第一导电层，以及形成位于所述第一导电层上的第二导电层。所述第一导电层与所述第二导电层之间形成有连接层，连接层电连接所述第一导电层与第二导电层。形成连接层包括形成邻接导电结构。
附图说明
当结合附图阅读时，从下文的详细描述本发明的各个方面能够得到最好的理解。需要强调的是，根据工业标准实践，不同的特征没有按比例规定绘制。实际上，为了阐明描述的目的，不同特征的尺寸可以任意增加或减小。
图1为本发明实施例的焊垫结构剖视图；
图2为图1所示实施例的焊垫结构的对应俯视图；
图3为本发明另一实施例的焊垫结构剖视图；
图4为图3所示实施例的焊垫结构的对应俯视图；
图5为本发明实施例的包括导电网络的焊垫结构俯视图；
图6为本发明实施例的包括导电网络和导电塞的焊垫结构俯视图；
图7为本发明又一实施例的焊垫结构的剖视图；
图8为图7所示实施例的焊垫结构的对应俯视图；
图9为本发明实施例的焊垫结构制造方法流程图。
具体实施方式
应当理解，为了实现本发明不同的特征，下文的描述提供了许多不同的实施例或例子。下面描述的特定示例的部件及结构的目的在于简化本发明的公开。当然，它们仅仅为示例，并且不应当受到限制。此外，在不同实施例中，本发明公开可以重复参考编号和/或字母。这些重复目的在于简化和阐明，本质上不在于指示所讨论的不同实施例和/设定之间的关系。另外，在随后描述关于在第二特征上方或上面形成第一特征可以包括第一特征和第二特征以直接方式接触的实施例，也可以包括在第一特征和第二特征之间设置形成的附加特征的实施例，这样第一特征和第二特征可以不是直接接触。此外，例如上部/下部、顶部/底部以及垂直/水平这些解释词汇是用来描述的容易，并且不向绝对方向提供任何限制。例如，上层和下层可以表示相对衬底或者形成在衬底上的集成电路的各自关系，而非表示绝对方向。
现在参考图1，该图显示了本发明实施例的焊垫结构(例如焊垫与焊垫连接)100。焊垫结构100可以形成在包括有集成电路或部分集成电路的衬底上。衬底通常包括导电层、绝缘层及半导体层，这些层被图案化以形成集成电路。衬底可以包括互连结构(例如，多层互连(MLI)或多个导电迹线以及层间电介质)，其中焊垫结构100电连接到该互连结构上。在一个实施例中，焊垫结构100包括垫下电路(circuit under pad，CUP)结构。在CUP结构中，焊垫可以设置在集成电路的有源电路或其一部分的上方。在一个实施例中，焊垫结构100为CUP结构，并且设置在集成电路的输入/输出(I/0)单元上方。CUP的优点包括缩短导线，由此减少它们的阻抗及容抗以能够减少集成电路的寄生电容，以及节省空间。
焊垫结构100包括下导电层110、中间导电层130、上导电层140、介电层120及125、钝化层150及170以及焊垫160。下导电层110可以电连接到互联结构(例如MLI)上或作为互联结构的一部分。中间导电层130设置在下导电层110上，并且上导电层140设置在中间导电层130上，由此中间导电层130设置在下导电层110与上导电层140之间。中间导电层130在上导电层140与下导电层110之间提供电连接。在一个实施例中，下导电层110、中间导电层130以及/或者上导电层140包括铜。其他适合用于下导电层110、中间导电层130以及/或者上导电层140的材料例如包括铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物(例如硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯或者其结合物)、铜、铜合金、钽、氮化钽及其组合。
上导电层140、下导电层110以及/或者中间导电层130如图所示为连续结构的导电材料。尤其，焊垫结构100包括作为导电材料固体层(例如垫)的中间导电层130。换句话说，作为固体层，中间导电层130的导电密度(例如，导电材料相比非导电材料(例如电介质)的百分比)大约是100％。虽然图示中间导电层130包括连续的导电结构，但是其他实施例也是可以的。例如，中间层可以包括任何配置的邻接导电结构。邻接的导电结构配置可以包括连续结构、相邻结构以及/或者紧密接触的结构。
上导电层140电连接到焊垫160上。在一个实施例中，焊垫160包括铝或者铝合金。其他适合用作焊垫160的材料例如包括金属、金属合金、金属硅化物以及/或者它们的结合物。焊垫160可以包括一个或多个导电材料层(例如阻挡层)。在实施例中，焊垫具有大约20微米到200微米范围的水平尺寸，以用于电测试(例如探测)及焊结。
中间导电层130在上导电层140和下导电层110之间提供电连接。实际上，中间导电层130在焊垫160和衬底上形成的集成电路或其部分的互连结构之间提供电连接。通常，通孔阵列可以替换中间导电层130用来向焊垫提供电连接。但是，使用通孔阵列可使得焊接应力产生从而导致扁平化。相比通孔阵列，中间导电层130可以用来改善机械应力的分布。在图示实施例中，中间导电层130与上导电层140的接触面为100％的导电材料。但是，其他实施例可以包括例如图3中描述的焊垫结构300。
焊垫结构100也包括介电层120及125。在一个实施例中，介电层120和125为一个整体(例如，单一的介电层)。适用于介电层120与/或125的材料例如包括二氧化硅、具有低介电常数的材料，例如介电常数(k)大约低于2.5(例如超低k，ELK)、氮化硅、氧氮化硅、聚酰亚胺、旋涂玻璃(SOG)、氟掺杂硅酸盐玻璃(FSG)、未掺杂二氧化硅玻璃(USG)、碳掺杂二氧化硅(SiOC)、Black Diamond(来自Santa Clara，California的应用材料公司)、干凝胶、气凝胶、无定形氟化碳、聚对二甲苯基、双苯并环丁烯预聚体(BCB，bisbenzocyclobutene)、SiLK(来自Midland，Michigan的Dow Chemical公司)以及/或者其它合适材料。在一个实施例中，介电层120包括超低k(ELK)。ELK层可以具有大约2.5的介电常数K。在一个实施例中，介电层125包括未掺杂二氧化硅玻璃(USG)。
焊垫结构100还包括钝化层150及170。钝化层150及/或170可包括二氧化硅、氮化硅、氧氮化硅以及/或者其他合适材料。钝化层150和170的开口暴露出提供焊接区域180的焊垫160。焊接区域180包括可用于焊接，例如用于球、楔或凸点布置的焊垫160的区域。
现在参考图2，图示为包括钝化开口190和导电区域195的焊垫结构100的俯视图。钝化开口190显示了钝化层150和170的开口，导电区域195显示下导电层110、中间导电层130、上导电层140及/或焊垫160的存在。在实施例中，如图2及图3所示，中间导电层130宽于钝化层170及150的开口横向延伸。
现在，参考图3及图4，图示为焊垫结构300的实施例。除下面描述的之外，焊垫结构300类似于上述图1中描述的焊垫结构100。例如，与焊垫结构100类似，焊垫结构300可以包括CUP结构。但是，焊垫结构300包括设置在下导电层110与上导电层140之间的中间层330。中间层330在下导电层110与上导电层140之间提供电连接，中间层330包括导电网络330a和多个衬垫330b。导电网络330a包括邻接的导电结构。在一个实施例中，导电网络330a包括连续的导电结构。衬垫330b可以是统一或者不统一的尺寸。
在一个实施例中，导电网络330a包括铜。其他适用于导电网络330a的材料例如包括铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、硅化金属(例如硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯或者其结合物)、铜、铜合金、钽、氮化钽及其结合物。衬垫330b包括电介质材料。衬垫330b可以包括与介电层125相同的电介质组成。在一个实施例中，衬垫330b包括USG。其他适合用于衬垫330b的材料例如包括二氧化硅、具有低介电常数的材料，例如介电常数(k)低于约2.5、氮化硅、氧氮化硅、聚酰亚胺、旋涂玻璃(SOG)、氟掺杂硅酸盐玻璃(FSG)、碳掺杂二氧化硅(SiOC)、Black Diamond(来自位于Santa Clara，California的应用材料公司)、干凝胶、气凝胶、无定形氟化碳、聚对二甲苯基、双苯并环丁烯预聚体(BCB，bisbenzocyclobutene)、SiLK(来自Midland，Michigan的Dow Chemical公司)以及/或者其它合适材料。在一个实施例中，例如图6中描述，一或多个导电塞可以形成在衬垫330b的通孔中。
导电网络330a可以包括任意配置的导电材料，从而在上导电层140与下导电层110之间提供电连接。这样，导电网络330a提供从上接触面(例如利用上导电层140)到下接触面(例如利用下导电层110，例如该层为垂直连续的)的导电路径。导电网络330a可以设定为网状结构、格子结构、网格结构以及/或者多个导电线(例如条纹)。在一个实施例中，中间层330包括邻接导电网络330a。在进一步的实施例中，导电网络330a为连续导电结构，从而从中间层330(例如水平连续)的一侧壁到中间层330的另一侧壁可以追踪到不间断的导电材料路径。应当注意，水平和垂直的用语不用来表示方向，而是表示相对上导电层140及下导电层110的相对位置。中间层330包括大约20％到100％的导电密度。也就是说，导电材料(例如在导电网络330a中)相对非导电材料(例如在衬垫330b中)的百分比在大约20％到100％的范围内。在一个实施例中，位于中间层330与上导电层140及/或下导电层110之间的接触面的大约20％到100％的表面区域包括导电网络330a。
图4显示了焊垫结构300的俯视图，该俯视图显示了钝化开口390、导电区395以及包括导电网络330a与衬垫330b的中间导电层330。钝化开口390表示钝化层150及170的开口，导电区395表示下导电层110、上导电层140以及/或者焊垫160的存在。如图3及图4所示，在一个实施例中，包括导电网络330a的中间导电层330超出钝化开口390延伸。
现在参考图5及图6，它们显示了部分焊垫结构实施例的俯视图。尤其，图5所示的焊垫结构500与图6所示的焊垫结构600显示了中间层330的示例实施例。焊垫结构500及600示出了上述图4中描述的钝化开口390和导电区395，还示出了导电网络330a和衬垫330b。焊垫结构500包括导电网络330a，其中导电网络330a为包括网状结构的连续导电结构。焊垫结构600也显示了包括导电网络330a的中间层330，其中导电网络330a具有网状结构。在焊垫结构600中，多个导电塞610形成在衬垫330b的通孔中。导电塞610可以在上导电层140与下导电层110之间提供电连接。每个导电塞610可以是离散结构。焊垫结构500及600仅用于示例性目的，目的不在于限制在任一种方式中。虽然图示实施例显示了包括网状结构的连续导电结构的导电网络，但是其他实施例可以包括任意的邻接导电结构。例如，在一个实施例中，中间层可以包括多个为邻接导电结构的结构(例如，诸如条纹的导电线，或者多个矩阵结构)，从而一个或多个的导电结构是相邻的。
现在参考图7及图8，图示为焊垫结构700的实施例。除下面描述之外，焊垫结构700与焊垫结构100类似。例如，与图1的焊垫结构100类似，焊垫结构700可以包括CUP结构。与上文图1中描述的焊垫结构类似，焊垫结构700包括下导电层110、中间导电层130以及上导电层140。虽然图示实施例中包括的中间导电层130具有100％的导电密度(例如，固体垫)，在其他实施例中，焊垫结构700包括例如上面图3、图4、图5及图7中描述的中间层330的中间层。该中间层可以具有低于100％的导电密度，并且可以包括任意配置的邻接导电结构。焊垫结构700包括焊垫710，在焊垫710的周边区域，焊垫710通过导电柱710a连接到上导电层140。钝化层150形成在部分焊垫710的下方。
特别参考图8，该图显示了包括导电区740、第一钝化开口720以及第二钝化开口730的焊垫结构700的俯视图，导电区740从俯视图显示了下导电层110、中间导电层130、上导电层140及/或焊垫710的存在。第一钝化开口720显示了钝化层150的开口，第二钝化开口730显示了钝化层170的开口。
下面参考图9，该图显示了用来形成焊垫结构的方法900的实施例流程图。方法900可以形成例如文中描述的焊垫结构100、300、500、600以及/或者700的焊垫结构。应当理解，对于该方法的其他实施例，在方法900之前、过程中以及之后可以提供附加步骤，并且下面描述的一些步骤可以被替换或删除。首先是方法900的步骤910，该步骤中在衬底上形成或者部分形成集成电路或者部分集成电路，衬底可以是半导体晶片，例如硅晶片。或者，衬底可以包括其他基本半导体材料，例如锗、化合物半导体(例如碳化硅、砷化镓、砷化铟以及磷化铟)、合金半导体材料(例如硅锗、硅锗碳、镓砷磷以及镓铟磷)以及/或者其他已知的衬底组成。
使用例如设置在衬底上的导电层、半导体层以及绝缘层形成集成电路。在一个实施例中，形成多层互连(MLI)结构包括有导电线(通孔和接触孔)以及层内电介质(ILD)层。下面参考步骤945描述形成的焊垫结构从衬底的外侧，例如从封装端向包括互连结构的器件提供电接触。互连结构的导电线可以包括以下材料，例如铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物、铜、铜合金、钽、氮化钽(例如硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯或者其结合物)及/或其他合适材料。互连结构可以通过以下工艺形成，例如包括物理气相沉积(或者溅射)、化学气相沉积(CVD)、整平以及/或者其他合适工艺。其他用来形成互连结构的制作技术可以包括光刻处理及蚀刻，以图案化用于垂直连接(通孔和接触孔)与水平连接(导线)的材料，并且随后可以是回蚀或者化学机械研磨(CMP)工艺。还有其他一些制造工艺，例如热退火可以用来在包含在MLI中的衬底上形成金属硅化物。
MLI的ILD层可以包括的材料例如以下：二氧化硅、具有低介电常数(例如介电常数低于约2.5)的材料、氮化硅、氧氮化硅、聚酰亚胺、旋涂玻璃(SOG)、未掺杂二氧化硅玻璃(USG)、氟掺杂硅酸盐玻璃(FSG)、碳掺杂二氧化硅、Black Diamond(来自位于Santa Clara，California的应用材料公司)、干凝胶、气凝胶、无定形氟化碳、聚对二甲苯基、双苯并环丁烯预聚体(BCB)、SiLK(来自Midland，Michigan的Dow Chemical公司)以及/或者其它合适材料。介电层可以通过包括旋涂、CVD以及/或者其他合适工艺来形成，并且随后可以执行回蚀或CMP工艺。互连结构可以在集成工艺，例如镶嵌(damascene)工艺或者光刻(lithography)/等离子体蚀刻工艺中形成。
然后执行的是方法900的步骤915，在该步骤中形成下导电层与相邻介电层。下导电层与该介电层可以与上述步骤910中描述的互连结构大体类似的方式形成。下导电层可以大体类似于上述图1-8描述的下导电层110，介电层也可以大体类似于上述图1-8中描述的介电层120。在一个实施例中，介电层与下导电层可以与互连结构的一层及/或部分互连结构同时形成。
然后，方法900进行的是步骤920，在该步骤中形成介电层。介电层可以大体上与上述图1、3及7中描述的介电层125类似。介电层可以通过包括旋涂、CVD或者其他合适工艺来形成，并且随后可以执行回蚀或CMP工艺。
然后是方法900的步骤925，在该步骤中对步骤920中形成的介电层进行图案化。介电层的图案化可以使用传统光刻技术。可以图案化介电层，从而使得中间导电层可以形成在下导电层上。图案化可以为即将形成的中间导电层作准备，以包括固体导电层，例如中间导电层130，或者中间导电层可以包括导电网络和衬垫区域，例如中间导电层330。在一个实施例中，图案化介电层，从而在衬垫区域提供通孔。可以使用例如包括形成光致抗蚀剂层的光刻工艺、烘烤工艺、曝光工艺、显影工艺、湿蚀刻或干蚀刻工艺以及/或者其他合适工艺来执行图案化。
接下来执行的是方法900的步骤930，在该步骤中可以将中间层形成在已图案化的介电层上。中间层包括邻接导电结构。在一个实施例中，中间层包括连续导电结构。中间导电层可以大体上类似于上述图1-8中描述的中间导电层130及/或中间层330。可以包括在中间层的邻接导电结构的可能配置例如包括固体层、矩阵结构、多个条纹以及/或者其他可能的配置。
在方法900的替代实施例中，可以形成固体导电层覆盖下导电层。导电层可以被蚀刻，以形成导电网络，并由此从关联衬垫区域除去导电层。然后，可以将介电层沉积在导电层上以及关联的衬垫区域。接着，回蚀以及/或者利用CMP处理介电层，从而介电层充满衬垫区域。上述工艺与/或其他已知工艺的任意结合可以适合用来形成中间导电层。
然后，在方法900的步骤935中形成上导电层。上导电层可以大体上与上述图1、3及7中描述的上导电层140类似。可以使用现有工艺，例如上面形成互连结构的步骤910中描述的工艺。
接着，在方法900的步骤940中形成钝化层。钝化层可以与上述图1、3及7中描述的钝化层150大体上类似。钝化层可以包括二氧化硅、氮化硅、氧氮化硅及其结合物。钝化层可以通过CVD、等离子体增强化学气相沉积(PECVD)、旋涂以及/或者其他合适技术形成。图案化及蚀刻钝化层，从而可以在钝化层中产生的开口中形成焊垫。
下面，在方法900的步骤945中形成焊垫。焊垫可以与上述图1、3及7中描述的焊垫160及/或焊垫710大体相似。焊垫可以包括例如具有阻挡层的多个层。可以使用例如溅射、CVD、整平以及/或者其他合适工艺的沉积技术形成焊垫。在一个实施例中，焊垫包括铝。焊垫可以包括的其他材料例如是钛、钽、铜。钨、其合金组合及/或其他合适导电材料。
然后执行的是方法900的步骤950，在该步骤中形成有附加钝化层。该钝化层可以与上述图1、图3及图7中描述的钝化层170大体上相似。此钝化层可以包括材料组合物，以及/或者以大体类似于步骤940中形成的钝化层的方式形成。
接下来是方法900的步骤955，在该步骤中，将步骤950中形成的钝化层开口，以曝光焊垫并为焊垫区域做准备。利用包括光刻及蚀刻的一系列现有的处理步骤，可以图案化钝化层以提供开口。
方法900可以继续到执行电测试步骤(例如探针测试)，在电测试步骤中，通过用于各种电性测定的测试探针来实现对已暴露焊垫的接触。利用各种引线接合工艺，例如热压焊接或者热超声焊接，方法900也可以继续到向芯片封装提供即将被引线的集成电路(例如管芯)，从而在已形成的焊垫上产生球焊或者楔焊。其他焊接工艺也可以选择使用(例如用于倒装晶片封装的凸点放置)。
上文已经强调了本发明一些具体实施例的特征，因此本领域普通技术人员可以更好地理解下文的详细描述。本领域普通技术人员应当了解，为了实现和文中介绍的实施例相同的目的及/或取得相同的优点，他们可以容易地使用本发明公开作为设计或修改其他工艺及结构的基础。本领域普通技术人员还应当意识到，这样的等同结构不脱离本发明的精神以及公开的保护范围。并且，在不脱离本发明的精神以及公开的保护范围的情况下，他们可以对做出多种变化、替换及更改。

Claims (13)

1.一种器件，包括：
第一导电层；
位于所述第一导电层上的第二导电层；
位于所述第二导电层上的焊垫；以及
设置在所述第一导电层与所述第二导电层之间的连接层，其中所述连接层包括邻接导电结构，
其中，所述连接层还包括至少一个衬垫，所述至少一个衬垫包括电介质与导电塞，所述导电塞通过在所述至少一个衬垫的通孔中填充有导电材料而形成。
2.如权利要求1所述的器件，其中所述邻接导电结构为连续导电结构。
3.如权利要求1所述的器件，其中所述邻接导电结构包括矩阵配置的导电材料。
4.如权利要求1所述的器件，其中所述连接层包括选自以下组的材料：铜、铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物、铜合金、钽、氮化钽及它们的组合。
5.如权利要求1所述的器件，其中还包括：
靠近所述第一导电层的低介电常数层。
6.如权利要求1所述的器件，其中所述邻接导电结构包括多个条纹配置的导电线。
7.如权利要求1所述的器件，其中还包括：
从所述焊垫向所述第二导电层延伸的导电塞。
8.如权利要求1所述的器件，其中所述连接层包括范围在20％到100％的导电密度。
9.一种器件，包括：
衬底；
形成在所述衬底上的第一导电层；
形成在所述第一导电层上的第二导电层；以及
设置在所述第一导电层与所述第二导电层之间并电连接所述第一导电层与所述第二导电层的中间层，其中所述中间层的导电密度大于20％，并且其中所述中间层包括连续的导电材料结构，以及
其中，多个衬垫设置在所述连续导电材料结构中，其中所述衬垫包括电介质以及导电塞，所述导电塞通过在所述衬垫的通孔中填充有导电材料而形成。
10.如权利要求9所述的器件，其中所述中间层包括导电密度为100％的导电垫。
11.如权利要求9所述的器件，更包括：
靠近所述第一导电层与所述第二导电层形成的至少一个介电层；以及
电连接到所述中间层的焊垫。
12.一种焊垫结构，包括：
第一导电层；
位于所述第一导电层上的第二导电层；
设置在所述第一导电层与所述第二导电层之间并电连接所述第一导电层与所述第二导电层的中间层，其中所述中间层包括连续的导电材料网络结构；以及
位于所述导电材料网络结构中的电介质衬垫中的多个通孔，其中所述多个通孔至少被部分填充有导电材料，以形成导电塞。
13.如权利要求12所述的焊垫结构，更包括：
位于所述第二导电层上的焊垫；
连接到所述焊垫的引线接合；及
设置在所述导电材料网络结构中的电介质衬垫。
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US20090194889A1 (en) 2009-08-06
US9601446B2 (en) 2017-03-21
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US20150194397A1 (en) 2015-07-09

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