CN101789417B - 硅通孔侧壁隔离结构 - Google Patents

硅通孔侧壁隔离结构 Download PDF

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CN101789417B
CN101789417B CN2010101035508A CN201010103550A CN101789417B CN 101789417 B CN101789417 B CN 101789417B CN 2010101035508 A CN2010101035508 A CN 2010101035508A CN 201010103550 A CN201010103550 A CN 201010103550A CN 101789417 B CN101789417 B CN 101789417B
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余振华
邱文智
吴文进
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了用于改进的硅通孔隔离结构的系统和方法。一个实施例包括具有在其上形成的电路的衬底的半导体器件。在衬底上方形成一个或多个介电层，并且将开口蚀刻进该结构中，开口从一个或多个介电层的表面开始延伸穿过一个或多个介电层进入衬底；开口具有侧壁。在开口的侧壁上方形成低k介电层。开口填充有导电材料和/或阻挡层，以制造通过低k介电层与周围衬底隔离的硅通孔。

Description

硅通孔侧壁隔离结构
本申请要求于2009年1月28日提交的、标题为“Through-Silicon ViaSidewall Isolation Structure”的美国临时专利申请序列第61/147,871号的优先权，其申请结合与此作为参考。
技术领域
本发明总的来说涉及用于改进的硅通孔的系统和方法，更具体地，涉及用于硅通孔(through-silicon via)侧壁隔离结构的系统和方法。
背景技术
由于集成电路(IC)的发明，半导体工业因为各种电子部件(例如，晶体管、二极管、电阻器、电容器等)集成密度的提高而经历了快速的发展。在很大程度上，集成密度的这种提高源自最小部件尺寸的反复降低，这使得更多部件被集成到给定区域中。
在进一步增加电路密度的尝试中，研究了三维(3D)IC。在3D IC的典型形成工艺中，将两个管芯结合在一起，并在每个管芯与衬底上的接触焊盘之间形成电连接。例如，一种尝试涉及将两个管芯结合在彼此的上面。然后，将堆叠的管芯结合到载体衬底，并且通过丝焊将每个管芯上的接触焊盘连接至载体衬底上的接触焊盘。然而，这种尝试要求载体衬底大于用于丝焊的管芯。
最近更多的尝试集中于硅通孔(TSV)。通常，TSV通过蚀刻垂直通孔穿过衬底并用诸如铜的导电材料填充通孔来形成。衬底的背侧被减薄以露出TSV，并且为TSV形成电接触。
作为TSV形成工艺的一部分，通常在TSV的导电材料与周围衬底之间形成阻挡层。典型地，阻挡层是通过物理汽相沉积(PVD)或化学汽相沉积(CVD)工艺形成的氧化物或氮化物层。然而，阻挡层形成工艺在沿着在衬底中形成的通孔的侧壁形成薄层方面具有难度，并且通常导致衬底表面上的厚层。当衬底表面上的多余导电材料被平面化(诸如采用过化学机械抛光(CMP)，仅留下通孔中的导电材料)时，衬底表面上的厚阻挡层会导致大的后CMP变化。此外，较厚的阻挡层减小了通孔的有效区域，导致试图用导电材料填充通孔时的难度。
因此，需要在通孔侧壁形成阻挡层的更好方法，其能够在通孔侧壁形成较薄的阻挡层，同时减小沿通孔侧壁的电容。
发明内容
通过本发明提供具有侧壁隔离结构的改进硅通孔的半导体器件的实施例，这些和其他问题通常被解决或避免，并且通常实现了技术优点。
根据本发明的一个实施例，提供包括衬底的半导体器件，在衬底上形成电路。在衬底上方形成一个或多个介电层，并且形成通过一个或多个介电层延伸到衬底中的开口。用导电材料填充开口，并在衬底和导电材料之间夹置低k介电层。
根据本发明的另一个实施例，提供了用于制造半导体器件的方法。该方法包括：设置衬底；以及在衬底中形成开口，该开口从衬底的第一表面延伸到衬底中，该开口具有侧壁。沿着开口的侧壁形成低k介电层，并在衬底的第一表面上方形成导电层，填充到开口中。
根据本发明的又一实施例，提供了用于制造半导体器件的方法。该方法包括：设置衬底，该衬底具有电路侧和与电路侧相对的背侧；以及在衬底的电路侧上形成电路。在衬底的电路侧上方形成一个或多个介电层，并在衬底中形成从一个或多个介电层的表面开始延伸的开口，该开口具有侧壁。该方法还包括：在开口的侧壁上方形成低k介电层；以及在低k介电层上方形成导电层，使得开口被导电层填充。
附图说明
为了更全面地理解本发明及其优点，将参考结合附图的以下描述，其中：
图1至图8示出了用于形成具有改进侧壁隔离的硅通孔的工艺中的中间阶段。
具体实施方式
下面详细描述本发明优选实施例的制造和使用。然而，应该理解，本发明提供了许多可以在具体环境下实现的许多可应用的发明概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，并不限制本发明的范围。
图1至图8是制造本发明实施例的中间阶段的截面图。首先参照图1，示出了衬底112，在其上形成有电路113。例如，衬底112可包括体硅、掺杂或未掺杂、或者绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括在绝缘体层上形成的半导体材料(诸如硅)的层。例如，绝缘体层可以是埋入氧化物(BOX)层或氧化硅层。在衬底(通常为硅或玻璃衬底)上设置绝缘体层。还可以使用其他衬底，诸如多层或梯度衬底。
形成在衬底112上的电路113可以是适合于特定应用的任何类型的电路。在一个实施例中，电路包括形成在衬底上的电器件，其中一个或多个介电层上覆电器件。可以在介电层之间形成金属层，以在电器件之间发送电信号。还可以在一个或多个介电层中形成电器件。
例如，电路113可包括互连以执行一个或多个功能的各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔断器等。这些功能可包括存储结构、处理结构、传感器、放大器、配电器、输入/输出电路等。本领域的技术人员应该理解，提供上述实例只是为了进一步解释本发明应用的示意性目的，并不用于以任何方式限制本发明。可以将其他电路适当地用作给定应用。
在图1中还示出了蚀刻阻止层114和层间介电(ILD)层116。优选地，蚀刻阻止层114由具有与相邻层(诸如下面的衬底112和上覆的ILD层116)不同的蚀刻选择性的介电材料形成。在一个实施例中，蚀刻阻止层114可由通过化学汽相沉积(CVD)或等离子体增强型CVD(PECVD)技术沉积的SiN、SiCN、SiCO、CN、它们的组合等形成。
例如，ILD层116可通过本领域已知的任何适合的方法(诸如旋涂、CVD和PECVD)由低k材料(诸如二氧化硅、磷硅酸玻璃(PSG)、硼磷硅玻璃(BPSG)、氟化硅玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的组合物、它们的组合等)形成。应该注意，蚀刻阻止层114和ILD层116可以都包括多个介电层，具有或不具有形成在相邻介电层之间的蚀刻阻止层。
通过ILD层116形成接触118，以提供与电路113的电接触。例如，可通过使用光刻技术在ILD层116上沉积和图样化光刻材料以露出ILD层116中成为接触件118的部分，来形成接触件118。可将诸如各向异性干蚀刻工艺的蚀刻工艺用于在ILD层116中制造开口。优选地，开口衬有扩散阻挡层和/或粘附层(未示出)，并填充有导电材料。优选地，扩散阻挡层包括TaN、Ta、TiN、Ti、CoW等的一层或多层，并且导电材料包括铜、钨、铝、银和它们的组合等，从而形成如图1所示的接触118。
现在参照图2，示出了形成上覆ILD层116的掩模层102。在一个实施例中，掩模层102包括在ILD层116上涂覆并图样化的光刻材料，尽管还可以使用对下面的ILD层116的材料具有高蚀刻选择性的其他材料。通常，掩模层102可由光刻材料通过沉积光刻材料层并根据期望图样露出光刻材料来形成。在露出光刻材料之后，对光刻材料进行显影以去除光刻材料中不想要的部分，从而形成如图2所示的掩模层102。可将其他材料(诸如SiN、SiO2等)用于形成掩模层。
此后，可以执行一个或多个蚀刻工艺以制造如图3所示的开口103。在一个实施例中，执行定时蚀刻工艺(诸如各向异性干蚀刻工艺)，直到在衬底112中获得期望深度的开口103。应该理解，本文所描述的蚀刻工艺可以在单个蚀刻工艺或多个蚀刻工艺中实现。例如，可以执行第一蚀刻工艺以蚀刻穿过ILD层116，以及可执行一个或多个第二蚀刻工艺以蚀刻穿过蚀刻阻止层114和/或衬底112。还应该理解，可通过其他方法(诸如研磨、激光技术等)来形成开口。
此后，如图4所示，旋涂工艺被用于在ILD层116上方形成低k介电层120。优选地，低k介电层120覆盖开口103的侧壁。低k介电层120的介电常数优选小于约4。例如，低k介电层120可以由SOG相关材料、甲基硅倍半氧烷(MSQ，methyl silsesquioxane)、含氢硅酸盐(HSQ，hydrogensilsesquioxane)以及用于形成互连件的所有旋涂低k材料，通过本领域已知的任何适当的方法形成。
图5示出了根据本发明实施例的填充开口103的导电层104和可选阻挡层121。导电层104优选为铜，但是还可以为任何适当的导电材料，诸如铜合金、铝、钨、银、多晶硅和它们的组合。在导电材料为铜的实施例中，导电层104可通过沉积种层，然后执行电镀工艺来形成。用导电层104的导电材料填充开口103来制造硅通孔(TSV)104a。
在图5中还示出了在形成导电层104之前在低k介电层120上方形成可选阻挡层121。优选地，可选阻挡层121包括诸如氮化钛的导电材料，尽管还可以选用诸如钽、氮化钽或钛的其他材料。优选地，使用诸如PECVD的CVD工艺来形成可选阻挡层121。然而，还可以使用其他可选工艺，诸如溅射或金属有机化学汽相沉积(MOCVD)。可选阻挡层121减小了随后置于开口103中的导电材料与周围材料(例如，低k介电层120和衬底112)之间扩散的发生。
本领域的技术人员应该理解，使用旋涂工艺形成低k介电层120使得沿着开口103的侧壁形成相对较薄的均匀涂层。低k介电层120还在TSV104a与衬底112之间提供了附加隔离，从而沿着TSV 104a的侧壁实现了电容的减小。此外，在可选阻挡层121下方的低k介电层120的较薄隔离结构创建了TSV 104a的导电材料的增加有效区域，由此提高了TSV 104a的有效性。
应该注意，虽然TSV 104a被示出为从ILD层116延伸到衬底112中，但还可以使用其他TSV配置。例如，本发明的实施例可利用从随后形成金属层间介电(IMD)层等的衬底112表面开始延伸的TSV。
参照图6，执行一个或多个平面化工艺，以从ILD层116的表面去除导电层104、可选阻挡层121和低k介电层120。可使用机械研磨工艺、化学机械抛光(CMP)工艺、蚀刻工艺和/或它们的组合来执行去除工艺。因为用于形成低k介电层的旋涂工艺所产生的相对较薄的现场沉积(on-fielddeposition)，所以后CMP变化显著降低。
如图7所示，在ILD层116的上方形成一个或多个金属层间介电(IMD)层130和相关的金属化层(未示出)。通常，一个或多个IMD层130和相关的金属层被用于使电路113彼此互连以提供外部电连接。优选地，IMD层130通过PECVD技术或高密度等离子体CVD(HDPCVD)等由低k介电材料(诸如氟硅酸盐玻璃(FSG))形成，并且可包括类似于蚀刻阻止层114的中间蚀刻阻止层。
在图7中还示出了随后执行晶片工艺以提供与外部器件的电连接。例如，在IMD层130的上方形成第一接触焊盘145和凸点下金属化层(UBM)146。形成钝化层141和第一绝缘层142，以使第一接触焊盘145与器件上的其他接触焊盘绝缘。形成第二绝缘层143和第三绝缘层144，以使UBM146与器件上的其他UBM以及外部环境相绝缘。
图8示出了执行背侧工艺以露出用于与其他半导体器件进行电连接的TSV 104a。在一个实施例中，如图8所示，执行诸如CMP的平面化工艺以露出TSV 104a的表面。在减薄衬底112的背侧之后，优选在TSV 104a的上方形成第二接触焊盘153。在衬底112的背侧上方形成背侧钝化层151，以使第二接触焊盘153与衬底112以及可在衬底112的背侧上形成其他接触焊盘绝缘。在背侧钝化层151的上方形成第一背侧绝缘层152，以进一步使接触焊盘153与衬底112的背侧上的其他接触焊盘以及外部环境相绝缘。
应该理解，本发明提供了具有较薄侧壁隔离结构的TSV。本文描述的工艺使用低k介电材料形成了隔离结构，这减小了沿着TSV侧壁的电容，同时还提供了用于将导电材料填充到TSV中的更大区域，由此增加了成功TSV形成的可能性。使用旋涂工艺形成隔离结构还导致较小的由于较薄的现场膜沉积而产生的后CMP变化。
上述实施例和工艺只是示意性的，并不用于限制本发明的范围。可以预期可选工艺和结构。例如，可以在CMP工艺之后执行附加减薄工艺以使衬底112的背侧凹陷，进一步露出TSV 104a。类似地，接触焊盘145和UBM 146可选地包括再分布层、导电凸块和/或附加绝缘层。此外，上述背侧工艺还可以包括再分布层、导电凸块、UBM和/或附加绝缘层的形成。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (15)

1.一种半导体器件，包括：
衬底，具有形成在其上的电路；
一个或多个介电层，形成在所述衬底上方；
开口，通过所述一个或多个介电层延伸到所述衬底中，所述开口填充有导电材料；以及
低k介电层，介于所述衬底和所述导电材料之间，并且沿着所述开口的侧壁形成。
2.根据权利要求1所述的半导体器件，还包括：阻挡层，介于所述低k介电层与所述导电材料之间。
3.根据权利要求1所述的半导体器件，其中，所述低k介电层包括具有小于约4的介电常数的材料；或者
所述低k介电层包括选自由Si-O-H、Si-O-C-H及其组合所组成的组中的材料；或者
所述导电层包括选自由铜、铜合金、铝、钨、银、多晶硅及其组合所组成的组中的材料。
4.一种用于制造半导体器件的方法，所述方法包括：
设置衬底，所述衬底具有电路侧和与所述电路侧相对的背侧；
在所述衬底中形成开口，所述开口从所述电路侧延伸到所述衬底中，所述开口具有侧壁；
沿着所述开口的侧壁形成低k介电层；
在所述开口中形成导电材料；以及
在所述衬底的背侧上露出所述导电材料。
5.根据权利要求4所述的方法，其中，所述方法还包括：在形成所述导电层之前，在所述低k介电层的上方形成阻挡层。
6.根据权利要求4所述的方法，其中，形成所述低k介电层包括旋涂工艺；或者
所述低k介电层包括具有小于约4的介电常数的介电材料；或者
所述低k介电层包括选自基本上由Si-O-H、Si-O-C-H及其组合所组成的材料的组中的介电材料。
7.根据权利要求4所述的方法，还包括：所述开口延伸穿过在所述衬底的电路侧上形成的一个或多个介电层。
8.根据权利要求4所述的方法，其中，形成所述导电层包括电镀工艺。
9.根据权利要求4所述的方法，其中，所述导电层包括选自由铜、铜合金、铝、钨、银、多晶硅及其组合所组成的组中的材料。
10.一种用于制造半导体器件的方法，所述方法包括：
设置衬底，所述衬底具有电路侧和与所述电路侧相对的背侧；
在所述衬底的电路侧上形成电路；
在所述衬底的电路侧上方形成一个或多个介电层；
在所述衬底中形成开口，所述开口从所述一个或多个介电层的表面开始延伸，所述开口具有侧壁；
在所述开口的侧壁上方形成低k介电层，其中，所述低k介电层沿着所述开口的侧壁形成；以及
在所述低k介电层上方形成导电层，使得所述开口填充有所述导电层。
11.根据权利要求10所述的方法，其中，所述方法还包括：在形成所述导电层之前，在所述低k介电层的上方形成阻挡层。
12.根据权利要求10所述的方法，其中，形成所述低k介电层包括旋涂工艺。
13.根据权利要求10所述的方法，其中，所述低k介电层包括具有小于约4的介电常数的材料；或者
所述低k介电层包括选自由Si-O-H、Si-O-C-H及其组合所组成的组中的材料。
14.根据权利要求10所述的方法，还包括：在所述衬底的背侧上露出所述导电层。
15.根据权利要求10所述的方法，其中，形成所述导电层包括电镀工艺。
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