CN101740417B - 可堆叠芯片的制造方法 - Google Patents

可堆叠芯片的制造方法 Download PDF

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Publication number
CN101740417B
CN101740417B CN2009102225422A CN200910222542A CN101740417B CN 101740417 B CN101740417 B CN 101740417B CN 2009102225422 A CN2009102225422 A CN 2009102225422A CN 200910222542 A CN200910222542 A CN 200910222542A CN 101740417 B CN101740417 B CN 101740417B
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substrate
layer
conductive layer
contact pad
silicon
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CN101740417A (zh
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李柏毅
王宗鼎
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了改进的半导体芯片制造的系统和方法。优选的实施例提供了一种用于制造可堆叠芯片的方法，该方法包括：设置第一衬底；以及在第一衬底中形成硅通孔。硅通孔从第一衬底的第一表面延伸出，其中，硅通孔连接至第一衬底的第一表面上的导电层，并且导电层具有平坦表面。导电层通过粘合剂接合至载体衬底。该方法后续步骤为：将第二衬底接合至第一衬底的第二表面；去除载体衬底；去除粘结剂层；以及图样化导电层，以形成接触焊盘。

Description

可堆叠芯片的制造方法
本申请要求于2008年11月13日提交的标题为“Improved Method forProducing Stackable Dies”的第61/114,268号美国临时申请的优先权，其结合于此作为参考。
技术领域
本发明总的来说涉及集成电路，更具体地，涉及改进的可堆叠芯片制造的装置和方法。
背景技术
由于集成电路的发明，半导体工业因各种电子部件(例如，晶体管、二极管、电阻器、电容器等)集成密度的不断改进而快速增长。很大程度上，这种集成密度的改进源自最小部件尺寸再三的减小，使得更多的部件集成到给定区域中。
尝试进一步提高电路密度，已经研究出了三维(3D)集成电路(IC)。在典型的3D IC形成工艺中，两个芯片接合在一起并且在每个芯片和衬底上的接触焊盘之间形成电连接。例如，一种尝试涉及将两个芯片接合在彼此的顶部。随后，堆叠的芯片接合至载体衬底并且引线接合件电连接至每个芯片上的接触焊盘，以接触载体衬底上的接触焊盘。然而，这种尝试需要比用于引线接合的芯片更大的载体衬底。
最近的尝试着眼于硅通孔(TSV)。通常，通过将垂直通孔蚀刻穿过衬底并且用导电材料(例如，铜)填充通孔来形成TSV。使衬底的背面减薄以露出TSV，并且焊球直接设置在TSV上，以提供电接触。铜凸块被形成为另一芯片的衬底电路侧上的电接触，其中，铜凸块电连接至TSV。
通常，在衬底背面的减薄之前形成衬底电路侧上的铜凸块。为了进行背面减薄工艺以露出TSV，电路侧通过覆盖铜凸块的粘合剂与载体衬底接合。在减薄工艺以及接合两个半导体芯片之后，去除载体衬底和粘合剂。由于铜凸块所造成的不平坦的表面形貌，所以通常很难从半导体芯片去除所有的粘合剂，由此在芯片电路侧上的形貌改变处留有粘合剂残留物。
此外，在半导体器件的电路侧上形成铜凸块的工艺需要凸块底层金属(under bump metallization，UBM)。通常，铝包括大部分集成电路的最后的金属层，然而，铝并不能与用于形成半导体芯片的电路侧电接触的铜凸块很好地接合。UBM件是添加在铝金属层和铜凸块之间的芯片处的附加金属层。UBM层防止了凸块和芯片的集成电路之间的扩散，同时还提供了强且稳定的低电阻电连接。UBM材料(诸如非电镀镍/沉金(electroless nickelimmersion gold))是非常昂贵的材料，其显著提高了半导体芯片生产的成本和生产要求。
从而，需要一种更好的可堆叠芯片的制造方法，以减小在形成之后残留在芯片上的粘合剂残留物的量，同时还降低对UBM的需求。
发明内容
通过本发明的优选实施例，普遍解决或避免了这些或其他问题并且普遍实现了技术优势，本发明的优选实施例提供了一种可堆叠芯片的制造方法，该方法包括：设置第一衬底；在第一衬底中形成从第一衬底的第一表面延伸出的硅通孔，其中，硅通孔连接至第一衬底的第一表面上的导电层，并且导电层具有平坦的表面；以及利用粘合剂将载体衬底接合至导电层。该方法后续步骤为：将第二衬底接合至第一衬底的第二表面；去除载体衬底；去除粘合剂层；以及图样化导电层以形成接触焊盘。
本发明的另一实施例提供了一种半导体器件的制造方法，该方法包括：设置第一衬底；在第一衬底中形成硅通孔；在第一衬底的电路侧上形成导电层；将第二衬底接合至第一衬底的第二表面；以及在接合之后，图样化导电层以形成电接触。
本发明的又一实施例提供了一种半导体器件，其包括：第一衬底，具有形成在其上的电路；一个或多个介电层，形成在第一衬底上方；硅通孔，穿过一个或多个介电层延伸至第一衬底中；以及第一接触焊盘，在介电层上方，其中，第一接触焊盘和硅通孔包括单个导电层。
附图说明
为了更全面地了解本发明及其优势，下面将以与附图相结合的以下描述作为参考，其中：
图1-20示出了制造可堆叠半导体芯片的改进工艺中的中间状态。
具体实施方式
下面，将详细论述本发明优选实施例的制造和使用。然而，应该理解，本发明提供了许多包含在广泛的多种特定范围内的适用发明理念。所论述的特定实施例仅仅描述制造和使用本发明的特定方式，并不限制本发明的范围。贯穿本发明的各个附图以及所述实施例，相同的参考标号用于表示相同的元件。
图1-20是在制造本发明实施例的中间状态的截面图。首选，参照图1，所示第一衬底112具有形成在其上的电路113。例如，第一衬底112可包括绝缘体上半导体(SOI)衬底的体硅、掺杂或未掺杂、或有源层。通常，SOI衬底包括形成在绝缘层上的半导体材料(诸如，硅)层。例如，绝缘层可以为氧化埋层(BOX)或二氧化硅层。绝缘层设置在通常为硅衬底或玻璃衬底的衬底上。也可使用其他衬底，诸如多层或梯度衬底(gradientsubstrate)。
形成在第一衬底112上的电路113可以是适用于特定应用的任何一种电路。在一个实施例中，该电路包括电器件，该电器件形成在具有上覆电器件的一个或多个介电层的衬底上。金属层可形成在介电层之间，以在电器件之间发送电信号。电器件还可形成在一个或多个介电层中。
例如，电路113可包括各种N型金属氧化物半导体(NMOS)器件和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔断器等，它们互连以形成一种或多种功能。这些功能可包括存储器结构、处理结构、传感器、放大器、配电器、输入/输出电路等。本领域普通技术人员应该理解，上述所提供的实例仅是为了说明的目的，以对本发明的实施作进一步解释并不意味着以任何的方式限制本发明。还可以根据需要使用其他电路以适于给定的应用。
图1还示出了蚀刻终止层114和层间介电(ILD)层116。优选地，蚀刻终止层114由具有与相邻层(例如，下面的第一衬底112和上覆的ILD层116)不同的蚀刻选择性的介电材料形成。在一个实施例中，蚀刻终止层114可以由通过化学汽相沉积(CVD)或等离子体增强型CVD(PECVD)技术沉积的SiN、SiCN、SiCO、CN或其组合等而形成。
例如，ILD层116可由低K介电材料(例如，二氧化硅、磷硅酸玻璃(PSG)、硼磷硅酸玻璃(BPSG)、氟化硅玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物(Spin-On-Polymer)、碳化硅材料、其化合物、其复合物、其组合物等)通过本领域已知的任何适合的方法(诸如，旋涂、CVD和PECVD)而形成。应该注意到，蚀刻终止层114和ILD层116中的每一个均可包括多个介电层，具有或不具有形成在相邻介电层之间的蚀刻终止层。
接触件118穿透ILD层116形成，以提供与电路113的电接触。例如，可通过使用光刻技术在ILD层116上沉积并图样化光刻材料以露出ILD层116中将成为接触件118的部分，来形成接触件118。蚀刻工艺(例如，各向异性干蚀刻工艺)可被用于在ILD层116中创建开口。优选地，开口加衬有(line)扩散势垒层和/或粘合剂层(未示出)并被填充有导电材料。优选地，扩散势垒层包括一个或多个TaN、Ta、TiN、Ti、CoW等的层，并且导电材料层包括铜、钨、铝、银及其组合等，从而形成如图1所示的接触件118。
一个或多个层间金属介电(IMD)层120以及相关的金属化层(未示出)形成在ILD层116的上方。通常，一个或多个IMD层120以及相关的金属化层被用于使电路113彼此互连并提供外部的电连接。优选地，IMD层120由通过PECVD技术或高密度等离子体化学汽相沉积(HDPCVD)等形成的低K介电材料(例如，氟化硅玻璃(FSG))形成，并且可包括与蚀刻终止层114相类似的中间蚀刻终止层。
现在，参照图2，示出了上覆IMD层120而形成的第一掩模层102。在一个实施例中，第一掩模层102包括已经在下层IMD层120上涂覆并图样化的光刻材料，但是也可以使用相对于IMD层120的下层材料具有高蚀刻选择性的其他材料。通常，第一掩模层102可由光刻材料通过沉积光刻材料层并根据期望的图案曝光光刻材料而形成。在曝光光刻材料之后，光刻材料被显影以去除光刻材料中不想要的部分，从而形成如图2所示的第一掩模层102。诸如SiN、SiO2等的其他材料也可被用于形成掩模层。
此后，可执行一个或多个蚀刻工艺来创建如图3所示的开口103。在一个实施例中，执行定时的蚀刻工艺(诸如，各向异性干蚀刻工艺)，直到在第一衬底112中得到期望深度的开口103。应该理解，可以以单个蚀刻工艺或多个蚀刻工艺来完成这里所描述的蚀刻工艺。例如，可以执行第一蚀刻工艺以蚀刻穿过IMD层120和/或ILD层116，并且可执行一个或多个第二蚀刻工艺以蚀刻穿过蚀刻终止层114和/或第一衬底112。应该理解，可通过其他方法(诸如，研磨、激光技术等)形成开口103。
图4示出了根据本发明实施例的填充开口103的导电层104。导电层104优选为铜，但是也可以是任何适合的导电材料，诸如铜合金、铝、钨、银及其组合。尽管可以使用其他适合形成导电层104的机构，但是优选地，使用电镀机构涂覆导电层104。在导电层104的表面上执行平坦化工艺，以创建基本平滑的表面。用导电层104填充开口103来创建硅通孔(TSV)104a。
在一个实施例中，TSV 104a可包括夹置在导电层104和周围材料(例如，IMD层120、ILD层116、蚀刻终止层114和第一衬底112)之间的势垒层(未示出)。势垒层降低了放置在开口103中的后续导电材料与周围材料之间的扩散发生率。开口103可加衬有一个或多个层的SiN、氧化物、聚合物等。也可以使用包括导电扩散势垒层的其他材料，诸如TaN、Ta、TiN、Ti、CoW等。
应该注意到，尽管示出TSV 104a从最上边的IMD层120延伸到第一衬底112中，但是也可使用其他TSV配置。例如，本发明的实施例可以利用从第一衬底112的表面、ILD层116、IMD层120的中间层等延伸出的TSV。
如图5所示，载体衬底106使用粘合剂105附看至导电层104的顶面。通常，在后续处理阶段期间，载体衬底106提供临时的机械和结构支撑。例如，载体衬底106可包括玻璃、二氧化硅、氧化铝等。粘合剂105可以为任何适合的粘合剂，例如，紫外线(UV)胶，该紫外线胶在暴露于UV光时失去其粘着性。优选地，粘合剂105以层压工艺进行涂覆，但是本发明尝试其他的方式来将粘合剂105接合至导电层104和载体衬底106。载体衬底106的优选厚度为使载体衬底106对所描述的半导体结构提供足够的机械支撑。
对于本领域普通技术人员而言，明显地，在形成与导电层104的电接触之前针对载体衬底106的粘合为粘合剂105的涂覆创建了基本平坦的接触区域。如下面更加详细所描述的，将粘合剂105涂覆至基本平坦的表面使得以在导电层104的表面上残留物很少或没有的方式来去除粘合剂105。
图6示出了根据本发明实施例的在第一衬底112的背面101a上执行的以露出TSV 104a的减薄工艺。可使用机械磨削工艺、化学机械抛光(CMP)工艺、蚀刻工艺和/或其组合来执行减薄工艺。例如，首先可执行平坦化工艺(例如，磨削或CMP)以首先露出TSV 104a。随后，可执行在TSV 104a的材料和第一衬底112的材料之间具有高蚀刻率选择性的湿或干蚀刻工艺以使第一衬底112凹陷，从而如图6所示，使TSV 104a从第一衬底112的下侧突出。在TSV 104a由铜形成的实施例中，例如，可通过使用HBr/O2、HBr/Cl2/O2、SF6/CL2、SF6等离子体等执行干蚀刻工艺来使第一衬底112的背面101a凹陷。
图6还示出了形成在TSV 104a的突出部分上方的扩散势垒层107。在一个实施例中，扩散势垒层107为非电镀镍/沉金(ENIG)层，但是也可使用任何适合的扩散势垒层。
图7示出了利用粘合剂203将第二衬底204的导电凸块202接合至对应的TSV 104a。第二衬底204可以为包括如参照图1所述的电路的晶片或芯片，其中，导电凸块202和粘合剂203提供外部电连接。优选地，导电凸块202包括铜，但是也可以为任何合适的导电材料，诸如铜合金、铝、钨、银及其组合。粘合剂203优选为焊料，但是本发明还可尝试适于在导电凸块202和对应TSV 104a之间传送电信号的任何接合介质。
如图8所示，底部填充(underfill)材料301被放置在第一衬底112和第二衬底204之间的空间中，以创建无缝结构以及更强的机械强度。优选地，底部填充材料301包括注入第一衬底112和第二衬底204之间的环氧树脂。然而，也可使用其他工艺和材料。
现在参照图9，通过任何适合的方法在第二衬底204周围涂覆密封剂302，密封剂302基本上覆盖第二衬底204和第一衬底112的背面101a。优选地，密封剂302包括任何合适的密封剂，诸如环氧基材料。图10示出了安装至膜框(film frame)401的组合后的第二衬底204和第一衬底112。通过任何适合的方法，密封剂302接合至膜框401以在去除载体106和粘合剂105期间确保与膜框401的组合结构牢固。
如图11所示，执行剥离工艺(例如，UV光曝光)，以从粘合剂105去除载体衬底106。剥离工艺优选地包括任何合适的剥离工艺，使得下层的半导体结构保持其完整性。
参照图12，从导电层104去除粘合剂105。优选使用机械器具以剥落的方式完成。本发明尝试使用任何适合的方法来去除粘合剂105，包括附件的化学或物理方法。有利地，在导电层104的表面上没有导电凸块，从而创建了平坦的表面。由于该平坦的表面，所以很容易去除粘合剂105，使得在导电凸块或可形成在导电层104的表面上的其他结构周围缝隙中残留的残留物很少或没有。如图13所示，膜框401随后与密封剂302分离。
现在参照图14，示出了上覆在导电层104上形成的第二掩模层108。在一个实施例中，第二掩模层108包括已经在下层导电层104上涂覆并图样化的光刻材料，尽管还可以使用其他相对于下层导电层104具有高蚀刻选择性的材料。通常，第二掩模层108可由光刻材料通过沉积光刻材料层并根据期望图案曝光光刻材料而形成。在曝光光刻材料之后，光刻材料被显影以去除光刻材料不想要的部分，从而形成如图14所示的第二掩模层108。也可使用其他材料和工艺，包括使用一个或多个硬掩模。
随后，如图15所示，可执行一个或多个蚀刻工艺以去除部分导电层104。在一个实施例中，蚀刻工艺(诸如，各向异性干蚀刻工艺)从导电层104中创建出导电元件104b。导电元件104b形成再分布层和导电凸块的基础，其使得电信号从TSV 104a的位置传输至这里所述结构外部的其他器件。一旦完成了导电层104的蚀刻，就去除第二掩模层108。应该理解，这里所述的蚀刻工艺可以以单个蚀刻工艺或多个蚀刻工艺来完成。应该理解，可通过其他方式来形成开口。
现在参照图16，示出了上覆在IMD层120和部分导电元件104b上形成的第三掩模层109。在一个实施例中，第三掩模层109包括已经在下层IMD层120和导电元件104b上涂覆并图样化的光刻材料，尽管还可以使用相对于下层导电元件104b具有高蚀刻选择性的其他材料。
随后，如图17所示，可执行一个或多个蚀刻工艺来去除部分导电元件104b。在一个实施例中，定时的蚀刻工艺(诸如，干蚀刻工艺)减薄了部分导电元件104b，从而形成导电凸块104c和再分布层104d。一旦完成了导电元件104b的蚀刻，就去除第三掩模层109。应该理解，这里的蚀刻工艺可以以单个蚀刻工艺或多个蚀刻工艺来完成。
如图18所示，通过任何合适的方法在IMD层120的顶面上沉积缓冲层110，覆盖再分布层104d和导电凸块104c。缓冲层110释放由于热膨胀所造成的半导体结构中不同材料的膨胀和收缩而引起的机械应力。在一个实施例中，缓冲层110是聚酰亚胺层，但是还可以将任何适合的材料用于形成缓冲层110。
现在参照图19，示出了上覆在缓冲层110上形成的第四掩模层111。在一个实施例中，第四掩模层111包括已经在下层缓冲层110上涂覆并图样化的光刻材料，尽管还可以使用相对于下层缓冲层110具有高蚀刻选择性的其他材料。
随后，如图20所示，可执行一个或多个蚀刻工艺，以去除部分缓冲层110。在一个实施例中，蚀刻工艺(诸如，干蚀刻工艺)露出用于与外部器件(未示出)电连接的导电凸块104c。一旦完成缓冲层110的蚀刻，就去除第四掩模层111。应该理解，这里所述的蚀刻工艺可以以单个蚀刻工艺或多个蚀刻工艺来完成。
应该理解，除了提供了具有平坦表面的半导体衬底(其使得对于将半导体衬底固定至载体衬底的粘合剂的去除在半导体衬底上的残留物很少或者没有)，本发明还消除了对于凸块底层金属(UBM)的需要。这里所描述的工艺将分离的TSV、再分布层和导电凸块结构组合成单个结构。通过组合分离的结构，在不需要昂贵的UBM材料的情况下，创建了低电阻电连接。这考虑到了重要的成本。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造，材料组分、装置、方法或步骤的范围内。此外，每项权利要求构成一个独立的实施例，各个权利要求和实施例的组合包含在本发明的范围内。

Claims (15)

1.一种用于制造可堆叠芯片的方法，所述方法包括：
设置第一衬底；
在所述第一衬底中形成从所述第一衬底的第一表面延伸出的硅通孔，其中，所述硅通孔连接至所述第一衬底的所述第一表面上的导电层，并且所述导电层具有平坦的表面；
利用粘合剂将载体衬底接合至所述导电层；
将第二衬底接合至所述第一衬底的第二表面；
去除所述载体衬底；
去除所述粘合剂；以及
图样化所述导电层，以形成接触焊盘。
2.根据权利要求1所述的方法，其中，将第二衬底接合至所述第一衬底的所述第二表面包括：
去除所述第一衬底的所述第二表面的一部分，以露出所述硅通孔；
在所述硅通孔的上方形成扩散势垒层；以及
将所述第二衬底的接触焊盘接合至所述第一衬底的相应硅通孔。
3.根据权利要求2所述的方法，还包括：在所述第二衬底周围形成密封剂层，其中，所述密封剂层基本覆盖所述第二衬底以及所述第一衬底的所述第二表面，
其中，所述扩散势垒层包括非电镀镍/沉金(ENIG)层。
4.根据权利要求1所述的方法，其中，图样化所述导电层以形成所述接触焊盘包括：
图样化所述导电层，以形成导电元件；以及
图样化所述导电元件，以限定再分布层和所述接触焊盘。
5.根据权利要求4所述的方法，其中，图样化所述导电层以形成所述接触焊盘还包括：
在所述再分布层和所述接触焊盘的上方形成缓冲层；以及
图样化所述缓冲层，以露出所述接触焊盘，
其中，所述缓冲层包括聚酰亚胺层。
6.一种制造半导体器件的方法，所述方法包括：
设置第一衬底；
在所述第一衬底中形成硅通孔；
在所述第一衬底的第一表面的电路侧上形成导电层；
将第二衬底接合至所述第一衬底的第二表面，其中，所述第一衬底的第二表面与所述第一衬底的第一表面的相对；以及
在接合之后，图样化所述导电层，以形成接触焊盘。
7.根据权利要求6所述的方法，其中，所述硅通孔从所述第一衬底的第一表面的电路侧延伸出并连接至所述第一衬底的第一表面的电路侧上的所述导电层，并且所述导电层具有平坦表面。
8.根据权利要求6所述的方法，其中，所述第一衬底中的所述硅通孔和所述第一衬底的第一表面的电路侧上的所述导电层包括单个导电层，并且所述导电层具有平坦表面。
9.根据权利要求6所述的方法，还包括：
将粘合剂涂覆至所述导电层的表面；以及
将载体衬底接合至所述粘合剂。
10.根据权利要求6所述的方法，其中，所述将第二衬底接合至所述第一衬底的第二表面包括：
去除所述第一衬底的第二表面的一部分，以露出所述硅通孔；
在所述第一衬底的第二表面上形成扩散层，用于覆盖部分露出的硅通孔；
将所述第二衬底的接触焊盘电连接至所述第一衬底的所述硅通孔；以及
在所述第二衬底的周围形成密封剂，其中，所述密封剂基本覆盖所述第二衬底以及所述第一衬底的第二表面，
其中，所述扩散层包括非电镀镍/沉金(ENIG)层。
11.根据权利要求6所述的方法，其中，图样化所述导电层以形成所述电接触包括：
在所述导电层的上方形成第一掩模层，以在所述导电层上露出第一图案；
根据露出的所述第一图案图样化所述导电层，以形成导电元件；
在所述导电元件的上方形成第二掩模层，以在所述导电元件上露出第二图案；以及
根据露出的所述第二图案图样化所述导电元件，以限定再分布层和接触焊盘。
12.根据权利要求11所述的方法，还包括：
在所述再分布层和所述接触焊盘上方形成缓冲层；以及
图样化所述缓冲层，以露出所述接触焊盘，
其中，所述缓冲层包括聚酰亚胺层。
13.一种半导体器件，包括：
第一衬底，具有形成在其第一表面上的电路；
一个或多个介电层，形成在所述第一衬底的上方；
硅通孔，穿过所述一个或多个介电层延伸到所述第一衬底中；以及
第一接触焊盘，在所述一个或多个介电层的上方，其中，所述第一接触焊盘和所述硅通孔包括单个导电结构；
第二衬底，接合至所述第一衬底与第一表面相对的第二表面上。
14.根据权利要求13所述的半导体器件，还包括缓冲层，所述缓冲层在所述第一衬底的第一表面上方。
15.根据权利要求13所述的半导体器件，还包括：
减薄的所述第一衬底的第二表面，用于露出所述硅通孔；
第二接触焊盘，位于所述第二衬底的第一表面上，所述第二接触焊盘连接至所述第一衬底所述的硅通孔；
扩散势垒层，夹置在所述第一衬底的第二表面上的所述硅通孔和位于所述第二衬底的第一表面上的所述第二接触焊盘之间；以及
密封剂，覆盖所述第二衬底以及所述第一衬底的第二表面。
CN2009102225422A 2008-11-13 2009-11-13 可堆叠芯片的制造方法 Expired - Fee Related CN101740417B (zh)

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