US20220223565A1 - Package and method of fabricating the same - Google Patents
Package and method of fabricating the same Download PDFInfo
- Publication number
- US20220223565A1 US20220223565A1 US17/337,594 US202117337594A US2022223565A1 US 20220223565 A1 US20220223565 A1 US 20220223565A1 US 202117337594 A US202117337594 A US 202117337594A US 2022223565 A1 US2022223565 A1 US 2022223565A1
- Authority
- US
- United States
- Prior art keywords
- isolation
- die
- layer
- vias
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000002955 isolation Methods 0.000 claims abstract description 213
- 238000000034 method Methods 0.000 claims abstract description 120
- 238000005538 encapsulation Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims description 114
- 239000010410 layer Substances 0.000 description 333
- 230000008569 process Effects 0.000 description 90
- 239000000463 material Substances 0.000 description 52
- 238000001465 metallisation Methods 0.000 description 34
- 239000004020 conductor Substances 0.000 description 31
- 229920002120 photoresistant polymer Polymers 0.000 description 28
- 238000005530 etching Methods 0.000 description 26
- 239000005360 phosphosilicate glass Substances 0.000 description 24
- 239000010949 copper Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 229910052802 copper Inorganic materials 0.000 description 21
- 150000004767 nitrides Chemical class 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 17
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 15
- 229920002577 polybenzoxazole Polymers 0.000 description 15
- 239000004642 Polyimide Substances 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 14
- 239000008393 encapsulating agent Substances 0.000 description 14
- 229920001721 polyimide Polymers 0.000 description 14
- 229920000642 polymer Polymers 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 13
- 238000005240 physical vapour deposition Methods 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 239000010936 titanium Substances 0.000 description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 239000005388 borosilicate glass Substances 0.000 description 12
- 150000001875 compounds Chemical class 0.000 description 12
- 239000010931 gold Substances 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 11
- 238000000231 atomic layer deposition Methods 0.000 description 11
- 239000000945 filler Substances 0.000 description 11
- 229910052737 gold Inorganic materials 0.000 description 11
- 229910052719 titanium Inorganic materials 0.000 description 11
- 239000004593 Epoxy Substances 0.000 description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 238000000227 grinding Methods 0.000 description 10
- 238000000059 patterning Methods 0.000 description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 9
- 238000012545 processing Methods 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 9
- 229910010271 silicon carbide Inorganic materials 0.000 description 9
- 239000004332 silver Substances 0.000 description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 239000002131 composite material Substances 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000004528 spin coating Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000007772 electroless plating Methods 0.000 description 7
- 239000012778 molding material Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 230000004907 flux Effects 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 229910052718 tin Inorganic materials 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000003575 carbonaceous material Substances 0.000 description 4
- 239000011162 core material Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- -1 silicon nitride Chemical class 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011152 fibreglass Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910002808 Si–O–Si Inorganic materials 0.000 description 1
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000012798 spherical particle Substances 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05181—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05684—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
- H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/13124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/8036—Bonding interfaces of the semiconductor or solid state body
- H01L2224/80379—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/85424—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85484—Tungsten (W) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- SoIC System on Integrate Chip
- the SoIC may include device dies formed using different technologies and have different functions bonded to the same device die, thus forming a system. This may save manufacturing cost and optimize device performance.
- FIG. 1A to FIG. 1J are schematic cross-sectional views illustrating a method of forming a 3DIC structure according to some embodiments of the disclosure.
- FIG. 2A to FIG. 12 are schematic various views illustrating 3DIC structures according to some embodiments of the disclosure.
- FIGS. 13A through 13E illustrate cross-sectional views of forming a package, in accordance with some embodiments.
- FIG. 14 illustrates a process flow for forming a 3DIC structure 111 accordance with some embodiments.
- first and first features are formed in direct contact
- additional features may be formed between the second and first features, such that the second and first features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- the package structure is a System on Integrated Chip (SoIC) package.
- SoIC System on Integrated Chip
- the intermediate stages of forming the SoIC package are illustrated in accordance with some embodiments.
- like reference numbers are used to designate like elements. It is appreciated that although the formation of SoIC packages is used as examples to explain the concept of the embodiments of the present disclosure, the embodiments of the present disclosure are readily applicable to other package structures and packaging methods in which the a surface of an encapsulation surrounding a top die is covered to prevent/reduce etching of the encapsulation. Therefore, the top surface of the encapsulation may be protected from pit defects and chamber contamination may be reduced during through substrate vias (TSVs) of the top die are revealed.
- TSVs through substrate vias
- FIG. 1A to FIG. 1J are schematic cross-sectional views illustrating a method of forming a 3DIC structure according to some embodiments of the disclosure.
- FIG. 2A is a top view of FIG. 1G .
- FIG. 2B is an enlarge view of a region in FIG. 2A .
- FIG. 2C is a schematic cross-sectional view of FIG. 2B .
- FIG. 1A to FIG. 1J are also reflected schematically in the process flow shown in FIG. 14 .
- FIG. 1A through FIG. 1C illustrate a die 204 bonded to a wafer 100 and laterally encapsulating by an encapsulation 127 .
- the dies 104 include IC dies, and may be logic dies (e.g., central processing unit, graphics processing unit, system-on-a-chip, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof.
- the dies 104 may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the dies
- the wafer 100 includes a substrate 105 and a bonding structure 120 over the substrate 105 .
- the substrate 105 may be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements or compounds, such as silicon, germanium, gallium, arsenic, and combinations thereof.
- the substrate 105 may also be in the form of silicon-on-insulator (SOI).
- SOI substrate may include a layer of a semiconductor material (e.g., silicon, germanium and/or the like) formed over an insulator layer (e.g., buried oxide and/or the like), which is formed on a semiconductor (such as silicon) substrate.
- other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like.
- the wafer 100 may further include one or more integrated circuit devices, an interconnection structure 114 , contact pads 115 , a passivation layer 116 , and a dielectric layer 117 between the substrate 105 and the bonding structure 120 .
- the integrated circuit devices may include active and/or passive devices.
- the one or more active and/or passive devices may be formed on and/or in the substrate 105 .
- the one or more active and/or passive devices may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and/or the like.
- NMOS n-type metal-oxide semiconductor
- PMOS p-type metal-oxide semiconductor
- the interconnection structure 114 is formed over the substrate 105 and the one or more active and/or passive devices.
- the interconnection structure 114 may provide electrical connections between the one or more integrated circuit devices formed on the substrate 105 .
- the interconnection structure 114 may include a metallization structure 113 formed in a dielectric structure 111 .
- the dielectric structure 111 may include a plurality of dielectric layers, such as inter-layer dielectric layers (ILDs) and inter-metal dielectric layers (IMDs). In some embodiments, the dielectric structure 111 comprises one or more layers of inorganic and/or organic dielectric material.
- ILDs inter-layer dielectric layers
- IMDs inter-metal dielectric layers
- the material of the dielectric structure 111 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-K dielectric material, such as un-doped silicate glass (USG), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), fluorinated silica glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like.
- USG un-doped silicate glass
- PSG phosphosilicate glass
- BPSG boron-doped phosphosilicate glass
- FSG fluorinated silica glass
- SiOxCy SiOxCy
- Spin-On-Glass Spin-On-Polymers
- silicon carbon material compounds thereof, composites thereof, combinations thereof, or the like.
- the metallization structure 113 includes a plurality of conductive features interconnected to each other and embedded in the dielectric structure 111 .
- the conductive features may include multi-layers of conductive lines, conductive vias, and conductive contacts.
- the conductive contacts may be formed in the ILDs to electrically connect the conductive lines to the devices; the conductive vias may be formed in the IMDs to electrically connect the conductive lines in different layers.
- the conductive features of the metallization structure 113 may include metal, metal alloy or a combination thereof.
- the conductive features may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof.
- the topmost conductive features of the metallization structure 113 have top surfaces substantially coplanar with a top surface of the dielectric structure 111 , but the disclosure is not limited thereto.
- the passivation layer 116 is formed on the interconnection structure 114 to cover the dielectric structure 111 and the metallization structure 113 .
- the passivation layer 116 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.
- the material of the passivation layer 116 is different from an underlying dielectric layer of the dielectric structure 111 .
- the topmost dielectric layer of the dielectric structure 111 includes silicon oxide
- the passivation layer 116 includes silicon nitride.
- the disclosure is not limited thereto.
- the contact pads 115 are formed over the interconnection structure 114 .
- the contact pads 115 are formed on and penetrating through the passivation layer 116 to electrically connect to a top conductive feature of the interconnection structure 114 , and may be electrically coupled to the one or more active and/or passive devices through the metallization structure 113 .
- the contact pads 115 may include a conductive material such as aluminum, copper, tungsten, silver, gold, a combination thereof, or the like.
- the dielectric layer 117 is formed over the interconnection structure 114 and the contact pads 115 .
- the dielectric layer 117 may include one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like.
- the dielectric layer may include one or more layers of photo-patternable insulating materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like,
- PBO polybenzoxazole
- PI polyimide
- BCB benzocyclobutene
- the dielectric layer is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like.
- the bonding structure 120 is formed on the dielectric layer 117 .
- the bonding structure 120 includes an insulating layer 119 formed on the dielectric layer 117 and the bond pads 123 formed in the insulating layers 119 .
- the bonding structure 120 further includes dummy pads 125 formed in the insulating layer 119 .
- the bond pads 123 are in direct electrical contact with vias 121 formed in the dielectric layer 117 and penetrating through the passivation layer 116 to electrically connect to the topmost conductive features of the metallization structure 113 .
- the bond pads 123 are in direct electrical contact with vias (not shown) landing on the contact pad 115 .
- the insulating layer 119 includes one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like.
- the insulating layer 119 is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like.
- the insulating layer 119 and the underlying dielectric layer may include a same material. In other embodiments, the insulating layer 119 and the underlying dielectric layer may include different materials.
- the bond pads 123 , dummy pads 125 and the vias 121 may include a conductive material such as aluminum, copper, tungsten, silver, gold, a combination thereof, or the like.
- a conductive material may be formed over the interconnection structure using, for example, PVD, ALD, electro-chemical plating, electroless plating, a combination thereof, or the like. Subsequently, the conductive material is patterned to form the contact pads using suitable photolithography and etching methods.
- the bond pads 123 , dummy pads 125 and the vias 121 may be formed in the insulating layer 119 using, for example, a damascene process, a dual damascene process, a combination thereof, or the like.
- the bond pads 123 , the dummy pads 125 and the insulating layer 119 are planarized, such that topmost surfaces of the bond pads 123 and the dummy pads 125 are substantially level or coplanar with a topmost surface of the insulating layer 119 .
- the die 204 is bonded to the die 104 on the first side of the wafer 100 to start forming a wafer-level die structure moo.
- the respective process is illustrated as step S 10 in the process flow shown in FIG. 14 .
- the die 204 may be a die which has been singulated from another semiconductor wafer. Although one die 104 and one die 204 are shown in the figures, the number of the die 104 and 204 are not limited in the disclosure.
- the die 204 and the die 104 may be the same types of dies or different types of dies, and the types of the dies are not limited in the disclosure.
- the die 204 may be a logic die (e.g., central processing unit, graphics processing unit, system-on-a-chip, microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor dies, micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), the like, or a combination thereof.
- a logic die e.g., central processing unit, graphics processing unit, system-on-a-chip, microcontroller, etc.
- a memory die
- the dies 204 may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the dies 204 may be the same size (e.g., same heights and/or surface areas).
- the die 204 may include substrate 205 , one or more active and/or passive devices (not shown), and interconnection structure 214 , contact pads 215 , a dielectric layer 217 , vias 221 , and a bonding structure 220 .
- the bonding structure 220 includes bond pads 223 , dummy pads 225 and an insulating layer 219 .
- the material and the formation method of the substrate 205 , the interconnection structure 214 , the contact pads 215 , the dielectric layer 217 , the vias 221 , and the bonding structure 220 of the die 204 may be similar to the substrate 105 , the interconnection structure 114 , the contact pads 115 , the dielectric layer 117 , the vias 121 and the bonding structure 120 of the wafer 100 , and hence the details are not repeated herein.
- the die 204 further include conductive vias 209 formed in the substrate 205 and electrically connected to the interconnection structure 214 .
- the conductive vias 209 may be arranged as an array, a plurality of arrays, irregularly, or a combination thereof.
- the conductive vias 209 may extend into the interconnection structure 214 to be in physical and electrical contact with the conductive features of the interconnection structure 214 .
- the conductive vias 209 are be formed by forming openings in the substrate 205 and filling the openings with suitable conductive materials. In some embodiments, the openings may be formed using suitable photolithography and etching methods.
- the openings may be filled with copper, a copper alloy, silver, gold, tungsten, tantalum, aluminum, aluminum alloys, a combination thereof, or the like, using physical vapor deposition (PVD), atomic layer deposition (ALD), electro-chemical plating, electroless plating, or a combination thereof, the like.
- PVD physical vapor deposition
- ALD atomic layer deposition
- electro-chemical plating electroless plating
- a combination thereof the like.
- a liner 209 j and/or an adhesive layer 209 i may be formed in the openings before filling the openings with the suitable conductive materials.
- the liner 209 j may include dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or the like, or combinations thereof.
- the adhesive layer 209 i may include Ta, TaN, Ti, TiN, or combinations thereof.
- the die 204 may be bonded to the wafer 100 through hybrid bonding, fusion bonding, or the like, or combinations thereof.
- the bonding of the die 204 to the wafer 100 may be achieved through hybrid bonding involving at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding such as dielectric-to-dielectric bonding, for example.
- the bond pads 223 are bonded to the bond pads 123 of the die (or referred to as bottom die) 104 , and the dummy pads 225 are bonded to the dummy pads 125 of the die 104 through metal-to-metal direct bonding.
- the metal-to-metal direct bonding is copper-to-copper direct bonding.
- the bond pads 223 may have sizes greater than, equal to, or smaller than the sizes of the respective the bond pads 123 .
- the dummy pads 225 may have sizes greater than, equal to, or smaller than, the sizes of the respective dummy bond pads 125 .
- the insulating layer 219 may be bonded to the insulating layer 119 through dielectric-to-dielectric bonding, which may be fusion bonding, for example, with Si—O—Si bonds generated.
- the bonding process may be performed as discussed below.
- the to-be-bonded surfaces of the die 204 and the die 104 are processed to be sufficiently clean and smooth.
- the die 204 is picked-and-placed on the die 10
- the die 204 and the die 104 are aligned and placed in physical contact at room temperature with slight pressure to initiate a bonding operation.
- a thermal treatment such as an annealing process at elevated temperatures is performed to strengthen the chemical bonds between the to-be-bonded surfaces of the die 204 and the die 104 and to transform the chemical bonds into covalent bonds.
- a bonding interface is formed between the bonding structure 120 of the die 104 and the bonding structure 220 of the device die 20 .
- the bonding interface is a hybrid bonding interface including a metal-to-metal bonding interface between the bonding pads 123 and the bonding pads 223 , the dummy pads 125 and the dummy pads 225 , and a dielectric-to-dielectric bonding interface between the dielectric layer 119 and the dielectric layer 219 .
- the die 204 is bonded to the die 104 in a face-to-face configuration. That is, the front surface of the die 204 faces the front surface 104 a of the die 104 .
- the disclosure is not limited thereto.
- the die 204 may be bonded to a die 104 ′ in a face-to-back configuration as shown in FIG. 12 . In other words, the front surface of the one of the dies 104 ′ and 204 may face the back surface of the other one of the dies 104 ′ and 204 , or the back surface of the die 204 may face the back surface of the die 104 ′.
- a “front surface” of a die refers to a surface close to contact pads, and may also be referred to as an active surface;
- a “back surface” of a die is a surface opposite to the front surface and may be a surface of the substrate, which may also be referred to as a rear surface.
- a backside grinding process may be performed to thin the die 204 , and the conductive vias 209 may not be revealed after the backside grinding process.
- the conductive vias 209 may not be revealed from the top surface (e.g. back surface) 204 b of the die 204 , the backside grinding is stopped when there is a thin layer of the substrate 205 covering the conductive via 209 .
- the disclosure is not limited thereto.
- the conductive vias 209 are revealed at this time, and the top surfaces of the conductive vias 209 and the top surfaces of the liners 209 j may be substantially coplanar with the top surface (e.g. back surface) of the substrate 205 . In some embodiments, the backside grinding process may be skipped. In some embodiments, the conductive vias 209 may be revealed after a planarization process is performed to remove a portion of an encapsulation 127 (shown in FIG. 1B ) over the top of the die 204 .
- an encapsulation 127 is formed over and surrounding the die 204 .
- the respective process is illustrated as step S 12 in the process flow shown in FIG. 14 .
- the encapsulation 127 includes one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like.
- the encapsulation 127 includes one or more layers of photo-patternable insulating materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, and may be formed using a spin-on coating process, or the like. Such photo-patternable insulating materials may be patterned using similar photolithography methods as a photoresist material.
- the encapsulation 127 includes a molding compound, such as an epoxy, a resin, a moldable polymer, a combination thereof, or the like. The molding compound may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin.
- the molding compound is an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around and between the die 204 .
- UV ultraviolet
- thermally cured polymer applied as a gel or malleable solid capable of being disposed around and between the die 204 .
- the encapsulation 127 and the die 204 are planarized, such that backside surface 204 c of the die 204 is substantially level or coplanar with a topmost surface 127 b of the encapsulation 127 .
- the conductive vias 209 are revealed at this time, and the top surfaces 209 b of the conductive vias 209 and the top surfaces of the liners 209 j may be substantially coplanar with the top surface (e.g. back surface) 205 b of the substrate 205 .
- the conductive vias 209 may also be referred to as through vias (TVs) 209 or through substrate vias (TSVs) 209 .
- the planarization process may include a CMP process, a grinding process, an etching process, a combination thereof, or the like.
- the layers, the contact pads and elements between the substrate 105 and the insulating layer 119 , and between the substrate 205 and the insulating layer 219 are not shown in FIG. 1D through FIG. 1I .
- FIG. 1D through FIG. 1E illustrate the formation of a recess 205 R in the die 204 according to some embodiments of the disclosure.
- the recess 205 R is formed through a patterning process by using a mask layer 129 .
- the respective process is illustrated as step S 14 to S 18 in the process flow shown in FIG. 14 .
- the mask layer 129 is formed on the die 104 to cover the top surface 127 b of the encapsulation 127 and portions of the top surface 204 b of the die 204 .
- the mask layer 129 includes a photoresist layer, and may be formed by spin coating.
- the photoresist layer is then patterned by an acceptable process, such as by using exposing the photoresist layer to light.
- the patterning forms the opening 101 that exposes the top surfaces 209 b of the TSVs 209 and a center portion of the top surface 205 b of the substrate 205 around the TSVs 209 .
- the substrate 205 exposed by the opening 101 is recessed such that a recess 205 R is formed across the substrate 205 , and the TSVs 209 protrude from the substrate 205 .
- portions of the substrate 205 laterally aside the TSVs 209 may be removed by an etching process, such as wet etching process, dry etching process, or a combination thereof.
- the etching process may utilize a high etching selectivity ratio between the substrate 205 and other adjacent materials (i.e. the TSVs 209 and the liners 209 j ).
- the liner 209 j may be substantially remaining after the etching process, but the disclosure is not limited thereto.
- portions of the liners 209 j may also be removed by the etching process.
- the remaining substrate 205 covered by the mask layer 129 forms sidewalls of the recess 205 R, and a surface 205 c of the remaining substrate 205 exposed by the opening 101 form a bottom 205 -BS of the recess 205 R.
- the recess 205 R may have the depth of 1 ⁇ m to 3 ⁇ m, for example.
- the sidewalls of the recess 205 R may be straight, and perpendicular to front surface 205 a of the substrates 205 as shown in FIG. 1E .
- the sidewalls of the recess 205 R may be inclined, and tapered toward the front surface 205 a of the substrates 205 as shown in FIG. 3 .
- the bottom of the recess 205 R exposes the surface 205 c of the substrate 205 , and the surface 205 c of the substrate 205 are lower than the top surface 205 b of the substrate 205 , and have a step 205 S therebetween. Furthermore, the surface 205 c of the substrate 205 are lower than the top surfaces 209 a of the TSVs 209 , so that the TSVs 209 has portions protruded from the surface 205 c of the substrate 205 (e.g. the bottom 205 -BS of the recess 205 R).
- the top surface 127 b of the encapsulation 127 and the top surface 205 b of the portion 205 M of the substrate 205 are covered by the mask layer 129 to prevent/reduce etching of the encapsulation 127 , and not exposed by the recess 205 R during the etching process. Therefore, the top surface 127 b of the encapsulation 127 may be protected from pit defects and chamber contamination may be reduced during the TSVs 209 are revealed.
- FIG. 1F through FIG. 1G illustrate the formation of an isolation layer 130 embedded in the substrate 205 of the die 204 according to some embodiments of the disclosure.
- the isolation layer 130 is formed as a bulk layer and separated from the encapsulation 127 .
- the respective process is illustrated as step S 18 to step S 24 in the process flow shown in FIG. 14 .
- the mask layer 129 is removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like.
- An isolation material layer 130 ′ is formed on the die 204 and the encapsulation 127 to cover the top surface 205 a of the substrate 205 , the top surfaces 209 a of the TSVs 209 and the top surface 127 b of the encapsulation 127 and fill the recess 205 R.
- the isolation material layer 130 ′ is formed to have a thickness at least equal to the height of the recess 205 R (e.g. the thickness of the portion of the TSVs 209 protruded from the surface 205 c of the substrate 205 ).
- the isolation material layer 130 ′ fully fills the recess 205 R.
- the isolation material layer 130 ′ is a conformal layer, that is, the isolation material layer 130 ′ has a substantially equal thickness within process variations extending along the region on which the isolation material layer 130 ′ is formed.
- the isolation material layer 130 ′ may include a dielectric material such as silicon nitride, although other dielectric materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer, which may be a photo-sensitive material such as PBO, polyimide, or BCB, a low-K dielectric material such as PSG, BPSG, FSG, SiOxCy, SOG, spin-on polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like may also be used for the isolation material layer 130 ′.
- a dielectric material such as silicon nitride, although other dielectric materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer, which may be a photo-sensitive material such as PBO, polyimide, or BCB, a
- the isolation material layer 130 ′ may be formed using a suitable deposition process, such as CVD, atomic layer deposition (ALD), or the like. In some embodiments, the isolation material layer 130 ′ may be a single layer as shown in FIG. 1F . In some embodiments, the isolation material layer 130 ′ may be multiple layers as shown in FIG. 4C , which will be described in detail later.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- a planarization process is performed to remove a portion of the isolation material layer 130 ′ over the top surface 209 a of the TSVs 209 and the top surface 205 b of the substrate 205 , so as to reveal the TSVs 209 , and an isolation layer 130 A is formed.
- the planarization process may include a CMP process.
- FIG. 2A illustrates a top view of FIG. 1G .
- FIG. 2B shows an enlarged view of the region A in FIG. 2A .
- FIG. 2C shows a cross-sectional view of a line I-I in FIG. 2B .
- the isolation layer 130 A is embedded in the substrate 205 and laterally around the TSVs 209 .
- the isolation layer 130 A surrounds the upper sidewalls of the TSVs 209 .
- the sidewalls and the bottom of the isolation layer 130 A are surrounded by the substrate 205 .
- the portion 205 M of the substrate 205 surrounded by the encapsulation 127 .
- the isolation layers 130 are laterally separated from the encapsulation 127 by the portion 205 M of the substrate 205 which are covered by the mask layer 129 previously, and the sidewalls 130 S of the isolation layer 130 A and sidewalls 127 S of the encapsulation 127 have a non-zero distance d 1 .
- the sidewalls 130 S of the isolation layers 130 may be straight, and perpendicular to front surface 205 a of the substrates 205 , but the disclosure is not limited thereto.
- a top surface 130 a of the isolation layer 130 A may be substantially coplanar within process variations with the top surfaces 209 a of the TSVs 209 , the top surface 205 b of the substrate 205 , and the top surface 127 b of the encapsulation 127 .
- the isolation layer 130 A may further extend to cover the top surface 127 b of the encapsulation 127 (not shown).
- the isolation layer 130 A is a bulk layer (or referred to as a whole layer or a continuous layer).
- the isolation layer 130 A may have various shapes, such as a square, a rectangle, a circle, and an ellipse, or a combination thereof.
- the upper sidewalls of the TSVs 209 is surrounded by the isolation 130 A, the middle sidewalls of the TSVs 209 is surrounded by the substrate 205 , and the lower sidewalls of the TSVs 209 is surrounded by the interconnection structure 214 .
- the adhesive layer 209 i and the liner 209 j may be sandwiched between the TSVs 209 and the isolation 130 A, the TSVs 209 and the substrate 205 , and the TSVs 209 and interconnection structure 214 .
- FIG. 1H through FIG. 1J illustrate the formation of a buffer layer 137 , conductive terminals 143 , and an insulating layer 147 over the encapsulation 127 and the die 204 according to some embodiments of the disclosure.
- the respective process is illustrated as step S 20 in the process flow shown in FIG. 14 .
- the buffer layer 137 is formed over the encapsulation 127 and the die 204 .
- the buffer layer 137 may include a single layer or multiple layers.
- the buffer layer 137 may include silicon oxide, silicon nitride, silicon oxynitride, USG, TEOS, a polymer, or a combination thereof.
- the polymer includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like.
- the forming method of the buffer layer 137 include suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), lamination or the like.
- openings 151 are formed in the buffer layer 137 .
- the openings 121 may have sizes greater than, equal to, or smaller than the sizes of the TSVs 209 .
- the openings 151 are via holes and penetrate through the buffer layer 137 to expose the corresponding TSVs 209 .
- the openings 151 are trenches and penetrate through the buffer layer 137 to expose the TSVs 209 .
- the openings 151 are formed to further expose the isolation layer 130 A around the TSVs 209 .
- the forming method of the openings 151 may include photolithography and etching processes, a laser drilling process, or a combination thereof.
- the isolation layer 130 A and the buffer layer 137 have different materials, so the isolation layer 130 A may be used as an etching stop layer during the etching process for forming the openings 151 .
- the sidewalls of the openings 151 may be straight or inclined. In some embodiments, the sidewalls of the openings 151 is inclined, and the taper toward the front surface 205 a of the substrates 205 , but the disclosure is not limited thereto
- the conductive terminals 143 are formed on the buffer layer 137 and in the openings 151 to electrically couple to the TSVs 209 .
- the conductive terminals 143 may be referred to as die connectors 143 .
- the conductive terminals 143 are metal pillars such as a copper pillar.
- the material of the conductive terminal 143 may include copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys).
- the conductive terminals 143 may be formed of a Sn—Ag alloy, a Sn—Cu alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing.
- the conductive terminal 143 may include a seed layer 139 in the openings 151 , and a conductive material 141 on the seed layer 139 .
- the seed layer 139 is formed on the surfaces of the openings 151 and a portion of the top surface of the buffer layer 137 .
- the seed layer 139 is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials.
- the seed layer 139 may include copper, titanium, titanium nitride, tantalum, tantalum nitride, or the like and may be formed by ALD, CVD, Physical Vapor Deposition (PVD), or the like.
- the seed layer 139 comprises a titanium layer and a copper layer over the titanium layer.
- the seed layer 139 may be formed using, for example, PVD or the like.
- a photoresist is formed and patterned on the seed layer 139 .
- the photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The patterning forms openings through the photoresist to expose the seed layer 139 .
- the conductive material 141 is formed in the openings of the photoresist and on the exposed portions of the seed layer 139 .
- the conductive material 141 may be formed by plating, such as electroplating or electroless plating, or the like.
- the conductive material 141 may comprise a metal, like copper, titanium, tungsten, aluminum, or the like.
- the photoresist and portions of the seed layer 139 on which the conductive material 141 is not formed are removed.
- the photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like.
- exposed portions of the seed layer 139 are removed, such as by using an acceptable etching process, such as by wet or dry etching.
- the remaining portions of the seed layer 139 and conductive material 141 form the conductive terminals 143 .
- the bottoms of the conductive terminals 143 land on the TSVs 209 as shown in an enlarge view 303 . In some embodiments, the bottoms of the conductive terminals 143 land on the TSVs 209 and the liners 209 j as shown in an enlarge view 302 . In some embodiment, the bottoms of the conductive terminals 143 land on the TSVs 209 , the liners 209 j and the isolation layer 130 A, and the conductive terminals 143 is isolated from the substrate 205 by the isolation layer 130 A as shown in an enlarge view 301 .
- the metal pillars may be solder free and have substantially vertical sidewalls.
- conductive caps 145 are formed on the top of the conductive terminals 143 .
- the conductive caps may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.
- a chip-probing process or other suitable chip testing process is performed on the wafer 100 to identify known good dies and bad dies.
- the conductive caps 145 are removed after the chip-probing process.
- the insulating layer 147 is formed on the conductive terminals 143 and the buffer layer 137 .
- the insulating layer 147 may include one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like.
- non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like.
- the insulating layer 147 may include one or more layers of photo-patternable insulating materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, and may be formed using a spin-on coating process, or the like. Such photo-patternable insulating materials may be patterned using similar photolithography methods as a photoresist material. In some embodiments, the insulating layer 147 is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like.
- the wafer 100 is singulated, for example, by sawing, laser ablation, etching, a combination thereof, or the like to form individual 3DIC structures 1002 and one of the 3DIC structures 1002 is shown in FIG. 1J .
- the 3DIC structures 1002 is also referred to as a SoIC structure.
- the respective process is illustrated as step S 26 in the process flow shown in FIG. 10 .
- FIG. 3 to FIG. 12 are schematic cross-sectional views illustrating various 3DIC structures 1003 , 1004 , 1004 1 , 1004 2 , 1004 3 , 1004 4 , 1006 , 1007 , 1008 , 1009 , 1010 , 1011 and 1012 according to other some embodiments of the disclosure.
- the 3DIC structure 1003 is similar to the 3DIC structure 1002 , the difference is that sidewalls 130 S of an isolation layer 130 B of the 3DIC structure 1003 is inclined, and tapered toward the front surface 205 a of the substrates 205 , but the disclosure is not limited thereto.
- the shape of the sidewalls 130 S of the isolation layer 130 B may be formed by tuning etching parameters of an etching process for forming recess 205 R in the substrate 205 .
- the 3DIC structures 1004 is similar to the 3DIC structure 1002 , wherein an isolation layer 130 C of the 3DIC structures 1004 includes multiple layers.
- the multiple layers includes dielectric materials such as silicon nitride, although other dielectric materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer, which may be a photo-sensitive material such as PBO, polyimide, or BCB, a low-K dielectric material such as PSG, BPSG, FSG, SiOxCy, SOG, spin-on polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like.
- dielectric materials such as silicon nitride, although other dielectric materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer, which may be a photo-sensitive
- the isolation layer 130 C of the 3DIC structure 1004 includes a nitride layer 130 1 such as a silicon nitride layer, and an oxide layer 130 2 such as a silicon oxide layer.
- the nitride layer 130 1 is formed on the substrate 205 to provide good water resistance, while the oxide layer 130 2 is formed on the nitride layer 130 1 to release the stress form the nitride layer 130 1 .
- FIG. 4A to FIG. 4C are schematic cross-sectional views illustrating a method of forming a 3DIC structure 1004 according to some embodiments of the disclosure.
- the oxide layer 130 2 and the nitride layer 130 1 may be formed by various method.
- a nitride material layer 130 1 ′ is conformally formed and has a substantially equal thickness extending along the top surfaces 127 b of the insulation 127 , the top surface 205 b of the substrate, the sidewalls and bottom of recess 205 R, the sidewalls of the liners 209 j, and the top surface 209 a of the TSVs 209 .
- An oxide material layer 130 2 ′ is then formed on the nitride layer 130 1 as shown in FIG. 4A .
- a planarization process is performed to remove a portion of the oxide material layer 130 2 ′ and the nitride material layer 130 1 ′, so as to reveal the TSVs 209 , and the oxide layer 130 2 and the nitride layer 130 1 are formed as shown in FIG. 4B . Thereafter, a buffer layer 137 , conductive terminals 143 , and an insulating layer 147 over the encapsulation 127 and the die 204 as shown in FIG. 4C .
- the 3DIC structure 1004 may be a 3DIC structure 1004 1 , 1004 2 , 1004 3 , or 1004 4 shown in FIG. 5A to FIG. 5D .
- FIG. 5A to FIG. 5D show enlarged views of a region B in FIG. 4C in accordance with various embodiments.
- the nitride layer 130 1 is filled in a space of the recess 205 R, so that the bottom surface of the nitride layer 130 1 is in contact with the substrate 205 , and the sidewalls of the nitride layer 130 1 is in contact with the liner 209 j.
- the oxide layer 130 2 is filled in a space of the recess 205 R remained from the nitride layer 130 1 .
- the top surfaces of the nitride layer 130 1 and the oxide layer 130 2 are in contact with the buffer layer 137 , and not in contact with the conductive terminal 143 as shown in FIG. 5A . In some embodiments, the top surfaces of the nitride layer 130 1 is in contact with the conductive terminal 143 , and the oxide layer 130 2 are in contact with the buffer layer 137 as shown in FIG. 5B . In some embodiments, the top surfaces of the nitride layer 130 1 is in contact with the conductive terminal 143 , and the oxide layer 130 2 is in contact with the conductive terminal 143 and the buffer layer 137 as shown in FIG. 5C .
- the top surface of the nitride layer 130 1 is in contact with the conductive terminals 143 , and the buffer layer 137 , and the oxide layer 130 2 is in contact with the buffer layer 137 as shown in FIG. 5D .
- the top surface of the oxide layer 130 2 is substantially coplanar with the top surface of the nitride layer 130 1 , the top surface 205 b of the substrate 205 , the top surface 207 a of the encapsulation 127 , and the top surfaces of the liner 209 j , the adhesive layer 209 i, and the TSVs 209 .
- FIG. 6A to FIG. 6G are schematic various views illustrating 3DIC structures 1006 according to some embodiments of the disclosure.
- FIG. 6B to FIG. 6D show top views of a line II-II in FIG. 6A .
- FIG. 6F and FIG. 6G show top views of a line II-II in FIG. 6E .
- the 3DIC structures 1006 are similar to the 3DIC structure 1002 , wherein a plurality of isolation parts 130 D is utilized.
- Each of the plurality of isolation parts 130 D may have a form such as those discussed above with reference to 130 A, 130 B, and/or 130 C.
- one or each of the plurality of isolation parts 130 D may be a circle around a corresponding one or more of the TSVs 209 as shown in FIG. 6B and FIG. 6F , a strip around a corresponding one or more of the TSVs 209 as shown in FIG. 6D and FIG. 6G , or a bend line around a corresponding one or more of the TSVs 209 as shown in FIGS. 6D and 6H .
- the embodiment of the present disclosure is not limited to these, the plurality of isolation parts 130 D may include a variety of shapes, and these shapes may be regular or irregular.
- Each of the plurality of isolation parts 130 D may surround the same number(s) of the TSVs 209 .
- each of the plurality of isolation parts 130 D surrounds one TSV 209 as shown in FIG. 6B and FIG. 6F .
- each of the plurality of isolation parts 130 D surrounds four TSVs 209 as shown in FIG. 6C and FIG. 6G .
- the plurality of isolation parts 130 D may have approximately the same width W and the same area.
- the width w 1 or w 2 of a portion of the plurality of isolation parts 130 D between the sidewall of a corresponding dielectric layer 209 j to a nearest edge of the isolation part 130 D is about 0.5 ⁇ m to 1.5 ⁇ m, for example.
- each of the plurality of isolation parts 130 D is arranged to align with the center or center line C of the corresponding TSV 209 as shown in FIG. 6A to FIG. 6D . In some embodiments, each of the plurality of isolation parts 130 D is arranged to be offset from the center or center line C of the corresponding TSV 209 as shown in FIG. 6E to FIG. 6H .
- the distance d pp between adjacent ones of the plurality of isolation parts 130 D may be the same as or different.
- FIG. 7A and FIG. 7B are schematic various views illustrating 3DIC structures 1007 according to some embodiments of the disclosure.
- FIG. 7B shows a top view of a line II-II in FIG. 7A .
- the 3DIC structures 1007 is similar to the 3DIC structure 1006 , wherein an isolation layer 130 E of the 3DIC structure 1006 includes isolation parts 130 E 1 and 130 E 2 separated from each other.
- Each of the plurality of isolation parts 130 E 1 and 130 E 2 may have a structure such as those discussed above with reference to 130 A, 130 B, and/or 130 C.
- the isolation parts 130 E 1 and 130 E 2 may surround different numbers of TSVs 209 . Further, the isolation parts 130 E 1 and 130 E 2 may have different widths W 1 and W 2 , different areas, or different shapes which is convenient for layout design.
- the isolation part 130 E 1 surrounds one column TSVs 209
- the isolation part 130 E 2 surrounds two columns TSVs 209
- the width W 1 of the isolation part 130 E 1 is less than the width W 2 of the isolation part 130 E 2 , but the disclosure is not limited thereto.
- the 3DIC structure 1007 further includes a dummy terminal 143 P disposed between conductive terminal 143 as shown in FIG. 7A .
- the dummy terminal 143 P is floating disposed on the buffer layer 137 , and does not penetrate into the buffer layer 137 .
- the TSVs 209 are not disposed below the dummy terminal 143 P and the isolation layer 130 E does not extend below the dummy terminal 143 P.
- the distance d pp between the isolation parts P 1 and P 2 is greater than the width W DT of the dummy terminal 143 P in some embodiments as shown in FIGS. 7A and 7B .
- the 3DIC structures 1008 is similar to the 3DIC structure 1007 , wherein an isolation layer 130 F of the 3DIC structure 1009 includes isolation parts 130 F 1 , 130 F 2 , 130 F 3 , and 130 F 4 separated from each other.
- Each of the plurality of isolation parts 130 F 1 , 130 F 2 , 130 F 3 , and 130 F 4 may have a structure such as those discussed above with reference to 130 A, 130 B, and/or 130 C.
- the die 205 of the 3DIC structure 1008 includes a first region R 1 and a second region R 2 .
- the density of the TSVs 209 in the first region R 1 is lower than the density of the TSVs 209 in the second region R 2 .
- each of the isolation parts 130 F 1 , 130 F 2 , 130 F 3 , and 130 F 4 is formed as a strip surrounding the same number of TSVs 209 as shown in FIG. 8B .
- each of the isolation parts 130 F 1 , and 130 F 2 is formed as a rectangle surrounding two TSVs 209
- each of the isolation parts 130 F 3 and 130 F 4 is formed as a strip surrounding four TSVs 209 as shown in FIG. 8C .
- the isolation parts 130 F 1 , 130 F 2 , 130 F 3 , and 130 F 4 may be formed to have different widths W 1 , W 2 , W 3 and W 4 , and different areas, respectively.
- the width W 1 is greater than the width W 2
- the width W 2 is greater than W 3
- the width W 3 is greater than W 4 , but the disclosure is not limited thereto.
- the isolation parts 130 F 1 and 130 F 2 may extend below the dummy terminal 143 P to further improve CMP uniformity.
- the isolation parts 130 F 1 , 130 F 2 , and 130 F 3 are arranged to align with the center lines C 1 , C 3 and C 4 of the corresponding TSVs 209 respectively.
- the isolation part 130 F 2 is arranged to be offset from the center line C 2 of the corresponding TSVs 209 .
- FIG. 9A to FIG. 9C are schematic various views illustrating 3DIC structures 1009 according to some embodiments of the disclosure.
- FIG. 9B and FIG. 9C show top views of a line II-II in FIG. 9A .
- an isolation layer 130 G of the 3DIC structure 1009 includes isolation parts 130 G 1 , 130 G 2 , and 130 G 3 and dummy parts 130 P separated from each other.
- Each of the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 and dummy parts 130 P may have a structure such as those discussed above with reference to 130 A, 130 B, and/or 130 C.
- the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 surround the same number of TSVs 209 .
- the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 have approximately the same width W, but the disclosure is not limited thereto.
- the dummy parts 130 P includes dummy parts 130 P 1 and 130 P 2 .
- the dummy parts 130 P 1 and 130 P 2 do not surround any TSV 209 .
- the dummy part 130 P 1 is disposed below the dummy terminal 143 P, and laterally separated from the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 .
- the dummy parts 130 P 2 include a dummy part 130 P 2 1 and dummy parts 130 P 2 2 .
- Each dummy part 130 P 2 1 and 130 P 2 2 is laterally separated from the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 and the encapsulation 127 .
- the dummy terminal 143 P and the conductive terminals 143 are not provided on the dummy parts 130 P 2 1 and 130 P 2 2 , and the TSVs 209 are not provided to penetrate through the dummy part 130 P 2 .
- the dummy parts 130 P 1 , 130 P 2 1 and 130 P 2 2 may have the same shape or different shapes.
- the shape of the dummy parts 130 P 1 , 130 P 2 1 and 130 P 2 2 may be the same as or different from the shape of the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 .
- the dummy parts 130 P 1 , 130 P 2 1 and 130 P 2 2 , and the isolation parts P are strips as shown in FIG. 9B .
- the dummy parts 130 P 1 , 130 P 2 1 and 130 P 2 2 , and the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 are circles as shown in FIG. 9C .
- the embodiments of the present disclosure are not limited thereto, and the shapes of the dummy parts 130 P 1 , 130 P 2 1 and 130 P 2 2 , and the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 are not particularly limited, and can be adjusted and changed according to design.
- the dummy parts 130 P 1 , 130 P 2 1 and 130 P 2 2 have widths W 1 ′, W 2 ′ and W 3 ′, and the widths W 1 ′, W 2 ′ and W 3 ′ may be the same or different. Further, the widths W 1 ′, W 2 ′ and W 3 ′may be the same as or different from the width W of the isolation parts 130 G 1 , 130 G 2 , and 130 G 3 .
- the distance d 1 L between the dummy parts 130 P 1 and the isolation part 130 G 1 may be the same as or different from the distance d 1 R between the dummy parts 130 P 1 and the isolation part P 2 .
- the distance d 2 L between the dummy parts 130 P 2 1 and the encapsulation 127 may be the same as or different from the distance d 2 R between the dummy parts 130 P 2 1 and the isolation part 130 G 1 .
- the distance d 3 L between the dummy parts 130 P 2 2 and the isolation part 130 G 3 may be the same as or different from the distance d 3 R between the dummy parts 130 P 2 2 and the encapsulation 127 .
- FIG. 10 to FIG. 12 are schematic cross-sectional views illustrating 3DIC structures 1010 , 1011 and 1012 according to some embodiments of the disclosure.
- the 3DIC structures 1010 and 1011 are similar to the 3DIC structure 1002 , wherein the 3DIC structures 1010 and 1011 each further includes a redistribution structure 131 formed over the backside surface 204 c of the die 204 to electrically connect the TSVs 209 of the die 204 and/or to external devices.
- a 3DIC structure similar to the 3DIC structure 1002 discussed above is shown for illustrative purposes, and in some embodiments, other 3DIC structures such as those discussed above may be used.
- the redistribution structure 131 may include one or more dielectric layer(s) 133 and respective metallization pattern(s) 135 in the one or more dielectric layer(s) 133 .
- the metallization patterns 135 are sometimes referred to as redistribution lines (RDLs).
- the dielectric layers 133 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material, such as PSG, BPSG, FSG, SiO x C y , Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like.
- the dielectric layers 133 may be deposited by any suitable method, such as spinning, CVD, PECVD, HDP-CVD, or the like.
- the metallization patterns 135 include conductive lines 135 M as shown in FIG. 10 .
- the metallization patterns 135 include conductive lines 135 M and conductive vias CV as shown in FIG. 11 .
- the sidewalls of the conductive vias 135 V and the conductive lines 135 M may be straight or inclined.
- the conductive via V has inclined sidewall and is tapered toward the substrate 205 .
- the metallization patterns 135 may be formed in the dielectric layer 133 , for example, by using photolithography techniques to deposit and pattern a photoresist material on the dielectric layer 133 to expose portions of the dielectric layer 133 that are to become the metallization pattern 135 .
- An etch process such as an anisotropic dry etch process, may be used to create recesses and/or openings in the dielectric layer 133 corresponding to the exposed portions of the dielectric layer 133 .
- the recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material.
- the diffusion barrier layer may include one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, deposited by ALD, or the like, and the conductive material may include copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVD, or the like. Any excessive diffusion barrier layer and/or conductive material on the dielectric layer may be removed, such as by using a CMP.
- An isolation layer 130 G of the 3DIC structures 1010 may be similar to isolation layer 130 A, 130 B, or 130 C.
- An isolation layer 130 H of the 3DIC structures 1011 may be similar to isolation layer 130 A, 130 B, 130 C, 130 D, 130 E, or 130 F.
- At least one Integrated Passive Device may also be disposed on the redistribution structure 131 .
- the IPD may be fabricated using standard wafer fabrication technologies such as thin film and photolithography processing, and may be mounted on the redistribution structure 131 through, for example, flip-chip bonding or wire bonding, etc.
- the 3DIC structure 1012 is similar to the 3DIC structure 1002 , 1003 , 1004 , 1006 , 1007 , 1008 , 1009 , 1010 or 1011 , and an isolation layer 130 I of the 3DIC structures 1012 may be similar to isolation layer 130 A, 130 B, 130 C, 130 D, 130 E, or 130 F.
- the die 204 is bonded to a die 104 ′ in a face-to-back configuration. That is, the front surface 204 a of the die 204 faces the back surface 104 b ′ of the die 104 ′.
- the die 104 ′ is similar to the die 104 , wherein the die 104 ′ further includes TSVs 109 ′ in the substrate 105 ′ and a bonding structure 120 ′ on the back surface 105 b ′ of the substrate 105 .
- the TSVs 109 ′ is similar to the TSVs 209 .
- the TSVs 109 ′ penetrate through the substrate 105 ′ and are connected to an interconnection structure 114 ′ formed on the front surface 105 a ′ of the substrate 105 ′.
- a liner 109 j ′ and/or an adhesive layer 109 i ′ may be formed before forming the TSVs 109 ′, so that the TSVs 109 ′ may be separated from the substrate 105 ′.
- the bonding structure 120 ′ is formed on the back surface 105 b ′ of the substrate 105 ′ and bonded with the bonding structure 220 of the die 204 .
- the bonding structure 120 ′ is similar to the bonding structure 120 .
- the bonding structure 120 ′ may include bond pads 123 ′ and dummy pads 125 ′.
- the bond pads 123 ′ and dummy pads 125 ′ may connect the bond pads 223 and the dummy pads 225 of the die 204 to the interconnection structure 114 ′ of the die 104 ′ as the 3DIC structure 1002 .
- the bond pads 123 ′ of the bonding structure 120 ′ are connected to the interconnection structure 114 ′ through the TSVs 109 ′.
- FIG. 13A through FIG. 13E illustrate cross-sectional views of forming a package, in accordance with some embodiments.
- a carrier substrate 102 is provided, and a release layer 124 is formed on the carrier substrate 102 .
- the carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like.
- the carrier substrate 102 may be a wafer, such that multiple packages may be formed on the carrier substrate 102 simultaneously.
- the release layer 124 may be formed of a polymer-based material, which may be removed along with the carrier substrate 102 from the overlying structures that will be formed in subsequent steps.
- the release layer 124 is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating.
- LTHC light-to-heat-conversion
- the release layer 124 may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights.
- the release layer 124 may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate 102 , or may be the like.
- the top surface of the release layer 124 may be leveled and may have a high degree of planarity.
- a dielectric layer 108 is formed on the release layer 124 .
- the dielectric layer 108 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like.
- the dielectric layer 108 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like.
- the dielectric layer 108 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof.
- conductive pillars 118 are formed on the release layer 124 .
- a seed layer is formed over the release layer 124 .
- the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials.
- the seed layer comprises a titanium layer and a copper layer over the titanium layer.
- the seed layer may be formed using, for example, PVD or the like.
- a photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The patterning forms openings through the photoresist to expose the seed layer.
- a conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer.
- the conductive material may be formed by plating, such as electroplating or electroless plating, or the like.
- the conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like.
- the photoresist and portions of the seed layer on which the conductive material is not formed are removed.
- the photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like.
- exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.
- the remaining portions of the seed layer and conductive material form the conductive pillars 118 .
- the 3DIC structures 1002 are adhered to the dielectric layer 108 by an adhesive 128 .
- the 3DIC structures 1002 are shown for illustrative purposes, and in some embodiments, other 3DIC structures discussed above may be used.
- the adhesive 128 is on back-side surfaces of the 3DIC structures 1002 and adheres the 3DIC structures 1002 to the release layer 124 .
- the adhesive 128 may be any suitable adhesive, epoxy, die attach film (DAF), or the like.
- an encapsulant 142 is formed on the various components. After formation, the encapsulant 142 laterally encapsulates the conductive pillars 118 and 3DIC structures 1002 .
- the encapsulant 142 includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like.
- the encapsulant 142 includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process.
- PBO polybenzoxazole
- PI polyimide
- BCB benzocyclobutene
- the encapsulant 142 includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like.
- nitride such as silicon nitride
- oxide such as silicon oxide
- BSG borosilicate glass
- BPSG boron-doped phosphosilicate glass
- the encapsulant 142 includes a composite material including a base material (such as polymer) and a plurality of fillers in the base material.
- the filler may be a single element, a compound such as nitride, oxide, or a combination thereof.
- the fillers may include silicon oxide, aluminum oxide, boron nitride, alumina, silica, or the like, for example.
- the cross-section shape of the filler may be circle, oval, or any other shape.
- the fillers are spherical particles, or the like.
- the cross-section shape of the filler may be circle, oval, or any other shape.
- the fillers include solid fillers, but the disclosure is not limited thereto. In some embodiments, a small portion of the fillers may be hollow fillers.
- the encapsulant 142 may be applied by compression molding, transfer molding, spin-coating, lamination, deposition, or similar processes, and may be formed over the carrier substrate 102 such that the conductive pillars 118 and/or the 3DIC structures 1002 are buried or covered. The encapsulant 142 is then cured. The conductive pillars 118 penetrate the encapsulant 142 , and the conductive pillars 118 are sometimes referred to as through vias 118 or through integrated fan-out vias (TIVs) 118 .
- TIVs integrated fan-out vias
- a planarization process is then performed on the encapsulant 142 to remove a portion of the encapsulant 142 , such that the top surfaces of the through vias 118 and the conductive terminals (die connectors) 143 are exposed.
- portions of the through vias 118 or/and portions of the dielectric material 140 may also be removed by the planarization process.
- top surfaces of the through vias 118 , the conductive terminals 143 , the insulating layer 147 , and the encapsulant 142 are substantially coplanar after the planarization process.
- the planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like.
- CMP chemical-mechanical polish
- the planarization may be omitted, for example, if the through vias 118 and the conductive terminals 143 are already exposed.
- a front-side redistribution structure 144 is formed over front-side surfaces of the through vias 118 , the encapsulant 142 , and the 3DIC structures 1002 .
- the front-side redistribution structure 144 includes dielectric layers 146 , 150 , 154 , and 158 ; metallization patterns 148 , 152 , and 156 ; and under bump metallurgies (UBMs) 160 .
- the metallization patterns 148 , 152 , and 156 may also be referred to as conductive redistribution layers or redistribution lines.
- the front-side redistribution structure 144 is shown as an example.
- More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure 144 . If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed below may be repeated.
- the dielectric layer 146 is deposited on the encapsulant 142 , the through vias 118 , and the conductive terminals 143 .
- the dielectric layer 146 is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask.
- the dielectric layer 146 may be formed by spin coating, lamination, CVD, the like, or a combination thereof.
- the dielectric layer 146 is then patterned. The patterning forms openings exposing portions of the through vias 118 and the conductive terminals 143 .
- the patterning may be by an acceptable process, such as by exposing the dielectric layer 146 to light when the dielectric layer 146 is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer 146 is a photo-sensitive material, the dielectric layer 146 may be developed after the exposure.
- the metallization pattern 148 is then formed.
- the metallization pattern 148 includes conductive lines CL on and extending along the top surface of the dielectric layer 146 .
- the metallization pattern 148 further includes conductive vias V extending through the dielectric layer 146 to be physically and electrically connected to the through vias 118 and the 3DIC structures 1002 .
- the sidewalls of the conductive vias 148 V and the conductive lines 148 C may be straight or inclined. In some embodiments, the conductive via V has inclined sidewall and is tapered toward the 3DIC structures 1002 .
- a seed layer is formed over the dielectric layer 146 and in the openings extending through the dielectric layer 146 .
- the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials.
- the seed layer comprises a titanium layer and a copper layer over the titanium layer.
- the seed layer may be formed using, for example, PVD or the like.
- a photoresist is then formed and patterned on the seed layer.
- the photoresist may be formed by spin coating or the like and may be exposed to light for patterning.
- the pattern of the photoresist corresponds to the metallization pattern 148 .
- the patterning forms openings through the photoresist to expose the seed layer.
- a conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer.
- the conductive material may be formed by plating, such as electroplating or electroless plating, or the like.
- the conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like.
- the combination of the conductive material and underlying portions of the seed layer form the metallization pattern 148 .
- the photoresist and portions of the seed layer on which the conductive material is not formed are removed.
- the photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.
- the dielectric layers 150 , 154 , 158 , and the metallization patterns 152 , 156 are formed alternately.
- the dielectric layer 150 , 154 , and 158 may be formed in a manner similar to the dielectric layer 146 , and may be formed of the same material as the dielectric layer 146 .
- the metallization patterns 152 and 156 may include conductive lines 152 C and 156 C on the underlying dielectric layer and conductive vias 152 V and 156 V extending through the underlying dielectric layer respectively.
- the metallization patterns 152 and 156 may be formed in a manner similar to the metallization pattern 148 , and may be formed of the same material as the metallization pattern 148 .
- the UBMs 160 are optionally formed on and extending through the dielectric layer 158 .
- the UBMs 160 may be formed in a manner similar to the metallization pattern 148 , and may be formed of the same material as the metallization pattern 148 .
- conductive connectors 162 are formed on the UBMs 160 .
- the conductive connectors 162 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like.
- the conductive connectors 162 comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like.
- the metal pillars may be solder free and have substantially vertical sidewalls.
- a metal cap layer is formed on the top of the metal pillars.
- the metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.
- the conductive connectors 162 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof.
- the conductive connectors 162 are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow process may be performed in order to shape the material into the desired bump shapes.
- a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate 102 from the dielectric layer 108 to form a package 166 .
- the de-bonding includes projecting a light such as a laser light or an UV light on the release layer 124 so that the release layer 124 decomposes under the heat of the light and the carrier substrate 102 may be removed.
- the package 166 is then flipped over and placed on a tape (not shown).
- a top package 500 may be bonded to package 166 .
- the top package 500 includes a substrate 502 and one or more stacked dies (or dies) 508 coupled to the substrate 502 .
- the substrate 502 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate 502 may be a SOI substrate.
- the substrate 502 may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the top package 500 .
- the devices may be formed using any suitable methods.
- the substrate 502 may have bond pads 503 on a first side the substrate 502 to couple to the stacked dies 508 , and bond pads 504 on a second side of the substrate 502 , the second side being opposite the first side of the substrate 502 , to couple to the conductive connectors 168 .
- the bond pads 503 and 504 are formed by forming recesses (not shown) into dielectric layers (not shown) on the first and second sides of the substrate 502 .
- the recesses may be formed to allow the bond pads 503 and 504 to be embedded into the dielectric layers.
- the recesses are omitted as the bond pads 503 and 504 may be formed on the dielectric layer.
- the bond pads 503 and 504 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof.
- the conductive material of the bond pads 503 and 504 may be deposited over the thin seed layer.
- the conductive material may be formed by an electro-chemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof.
- the conductive material of the bond pads 503 and 504 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.
- the bond pads 503 and 504 are UBMs that are formed using the same or similar processes as described earlier in connection with UBMs 160 .
- the stacked dies 508 are coupled to the substrate 502 by wire bonds 510 , although other connections may be used, such as conductive bumps.
- the stacked dies 508 are stacked memory dies.
- the stacked memory dies 508 may include low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules.
- the stacked dies 508 and the wire bonds 510 may be encapsulated by a molding material 512 .
- the molding material 512 may be molded on the stacked dies 508 and the wire bonds 510 , for example, using compression molding.
- the molding material 512 is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof.
- a curing step may be performed to cure the molding material 512 , wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof.
- the stacked dies 508 and the wire bonds 510 are buried in the molding material 512 , and after the curing of the molding material 512 , a planarization step, such as a grinding, is performed to remove excess portions of the molding material 512 and provide a substantially planar surface for the top packages 500 .
- a planarization step such as a grinding
- the top packages 500 are bonded to the InFO packages 166 by way of the conductive connectors 168 and the bond pads 504 .
- the stacked memory dies 508 may be coupled to the 3DIC structure 1002 through the wire bonds 510 , the bond pads 503 and 504 , through vias 506 , the conductive connectors 168 , and the through vias 118 .
- the conductive connectors 168 may be similar to the conductive connectors 162 described above and the description is not repeated herein, although the conductive connectors 168 and 162 need not be the same.
- the conductive connectors 168 are coated with a flux (not shown), such as a no-clean flux.
- the conductive connectors 168 may be dipped in the flux or the flux may be jetted onto the conductive connectors 168 .
- the conductive connectors 168 may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the top package 500 is attached to the package 166 . This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors 168 .
- an underfill 170 may be formed between the top package 500 and the package 166 and surrounding the conductive connectors 168 . The underfill 170 may be formed by a capillary flow process after the top package 500 is attached or may be formed by a suitable deposition method before the top package 500 is attached.
- the bonding between the top package 500 and the package 166 may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding.
- the top package 500 is bonded to the package 166 by a reflow process. During this reflow process, the conductive connectors 168 are in contact with the bond pads 504 and the through vias 118 to physically and electrically couple the top package 500 to the package 166 .
- the present disclosure offers various advantages. It is understood, however, that not all advantages are necessarily discussed herein, and other embodiments may offer different advantages, and that no particular advantage is required for all embodiments.
- the top surface of the encapsulation and the top surface of the portion of the substrate are covered by the mask layer to prevent/reduce etching of the encapsulation, and not exposed by the recess during the etching process. Therefore, the top surface of the encapsulation may be protected from pit defects and chamber contamination may be reduced during the TSVs is revealed.
- testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices.
- the testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like.
- the verification testing may be performed on intermediate structures as well as the final structure.
- the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
- a package comprises a first die, wherein the first die comprises a plurality of through vias from a first surface of the first die toward a second surface of the first die; a second die disposed below the first die, wherein the second surface of the first die is bonded to the second die; an isolation layer disposed in the first die, wherein the plurality of through vias extend through the isolation layer; an encapsulation laterally surrounding the first die, wherein the encapsulation is laterally separated from the isolation layer; a buffer layer disposed over the first die, the isolation layer, and the encapsulation; and a plurality of conductive terminals disposed over the isolation layer, wherein the plurality of conductive terminals is electrically connected to corresponding ones of the plurality of through vias.
- the isolation layer comprises a bulk layer surrounding the plurality of through vias in the first die.
- the isolation layer comprises a plurality of isolation parts, wherein each isolation part of the plurality of isolation parts surround at least one through via of the plurality of through vias.
- each isolation part of the plurality of isolation parts surrounds a same number of the plurality of through vias.
- the plurality of isolation parts comprises a first isolation part and a second isolation part, wherein the first isolation part surrounds a first number of through vias of the plurality of through vias, wherein the second isolation part surrounds a second number of through vias of the plurality of through vias, wherein the first number is different than the second number.
- the isolation layer comprises a dummy isolation part separate from the plurality of isolation parts, the dummy isolation part being disposed between a first isolation part of the plurality of isolation parts and the encapsulation, wherein the first isolation part is an isolation part closest to an edge of the first die, and wherein no through via of the plurality of through vias penetrate the dummy isolation part.
- a package comprises a first die, wherein the first die comprises first substrate, the first die further comprising a first through via and a second through via extending from a top surface of the first substrate toward a bottom surface of the first die; an isolation layer disposed in a recess in the top surface of the first substrate, the isolation layer surrounding the first through via and the second through via, wherein the first substrate surrounds the isolation layer in a top view; and a first encapsulation laterally surrounding the first die, wherein the first substrate is interposed between the first isolation layer and the first encapsulation.
- the top surface of the first substrate is level with a top surface of the first encapsulation and a top surface of the isolation layer.
- the package further comprises a buffer layer disposed over the first encapsulation, the first die and the isolation layer, wherein a bottom surface of the buffer layer is in contact with the top surfaces of the first encapsulation, the first die and the isolation layer.
- the package further comprises a dummy terminal over the buffer layer, wherein the isolation layer extends below the dummy terminal.
- the package further comprises a dummy terminal over the buffer layer, wherein the isolation layer does not extend below the dummy terminal.
- the isolation layer comprises multiple layers.
- a method of manufacturing a package structure comprises bonding a first surface of a first die to a second die, wherein the first die comprises a first through via; forming an encapsulation laterally aside the first die; forming a first recess in a second surface of the first die, the first recess extending around the first through via; and forming an isolation layer in the first recess, wherein the isolation layer is separated from the encapsulation by the first die.
- the first die comprises a second through via, wherein the first recess extends continuously around the first through via and the second through via.
- the first die comprises a second through via, further comprising forming a second recess surrounding the second through via, wherein forming the isolation layer comprises forming a first isolation part in the first recess and forming a second isolation part in the second recess, wherein the first isolation part is separated from the second isolation part.
- the method further comprises forming a second recess, wherein the second recess does not expose a conductive feature; and forming the isolation layer in the second recess.
- the method further comprises forming a buffer layer on the encapsulation, the isolation layer, the plurality of through vias, and the first die; and forming a conductive terminal on the buffer layer, wherein the conductive terminal is electrically connected to the first through via.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Led Device Packages (AREA)
Abstract
Description
- This application claims the benefit of U.S. Provisional Application No. 63/136,776 filed on Jan. 13, 2021, entitled “Package and Method of Fabricating the Same,” which application is hereby incorporated by reference.
- The packages of integrated circuits are becoming increasing complex, with more device dies packaged in the same package to achieve more functions. For example, System on Integrate Chip (SoIC) has been developed to include a plurality of device dies such as processors and memory cubes in the same package. The SoIC may include device dies formed using different technologies and have different functions bonded to the same device die, thus forming a system. This may save manufacturing cost and optimize device performance.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1A toFIG. 1J are schematic cross-sectional views illustrating a method of forming a 3DIC structure according to some embodiments of the disclosure. -
FIG. 2A toFIG. 12 are schematic various views illustrating 3DIC structures according to some embodiments of the disclosure. -
FIGS. 13A through 13E illustrate cross-sectional views of forming a package, in accordance with some embodiments. -
FIG. 14 illustrates a process flow for forming a3DIC structure 111 accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- A package structure and the method of forming the same are provided in accordance with various embodiments. In some embodiments, the package structure is a System on Integrated Chip (SoIC) package. The intermediate stages of forming the SoIC package are illustrated in accordance with some embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is appreciated that although the formation of SoIC packages is used as examples to explain the concept of the embodiments of the present disclosure, the embodiments of the present disclosure are readily applicable to other package structures and packaging methods in which the a surface of an encapsulation surrounding a top die is covered to prevent/reduce etching of the encapsulation. Therefore, the top surface of the encapsulation may be protected from pit defects and chamber contamination may be reduced during through substrate vias (TSVs) of the top die are revealed.
-
FIG. 1A toFIG. 1J are schematic cross-sectional views illustrating a method of forming a 3DIC structure according to some embodiments of the disclosure.FIG. 2A is a top view ofFIG. 1G .FIG. 2B is an enlarge view of a region inFIG. 2A .FIG. 2C is a schematic cross-sectional view ofFIG. 2B .FIG. 1A toFIG. 1J are also reflected schematically in the process flow shown inFIG. 14 . -
FIG. 1A throughFIG. 1C illustrate a die 204 bonded to awafer 100 and laterally encapsulating by anencapsulation 127. - Referring to
FIG. 1A , thewafer 100 having a plurality ofdies 104 is provided. In accordance with some embodiments of the present disclosure, thedies 104 include IC dies, and may be logic dies (e.g., central processing unit, graphics processing unit, system-on-a-chip, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. Also, in some embodiments, thedies 104 may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, thedies 104 may be the same size (e.g., same heights and/or surface areas). - The
wafer 100 includes asubstrate 105 and abonding structure 120 over thesubstrate 105. In some embodiments, thesubstrate 105 may be formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements or compounds, such as silicon, germanium, gallium, arsenic, and combinations thereof. Thesubstrate 105 may also be in the form of silicon-on-insulator (SOI). The SOI substrate may include a layer of a semiconductor material (e.g., silicon, germanium and/or the like) formed over an insulator layer (e.g., buried oxide and/or the like), which is formed on a semiconductor (such as silicon) substrate. In addition, other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates, any combinations thereof and/or the like. - The
wafer 100 may further include one or more integrated circuit devices, aninterconnection structure 114,contact pads 115, apassivation layer 116, and adielectric layer 117 between thesubstrate 105 and thebonding structure 120. The integrated circuit devices may include active and/or passive devices. The one or more active and/or passive devices may be formed on and/or in thesubstrate 105. In some embodiments, the one or more active and/or passive devices may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and/or the like. Theinterconnection structure 114 is formed over thesubstrate 105 and the one or more active and/or passive devices. Theinterconnection structure 114 may provide electrical connections between the one or more integrated circuit devices formed on thesubstrate 105. Theinterconnection structure 114 may include ametallization structure 113 formed in adielectric structure 111. - The
dielectric structure 111 may include a plurality of dielectric layers, such as inter-layer dielectric layers (ILDs) and inter-metal dielectric layers (IMDs). In some embodiments, thedielectric structure 111 comprises one or more layers of inorganic and/or organic dielectric material. For example, the material of thedielectric structure 111 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-K dielectric material, such as un-doped silicate glass (USG), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), fluorinated silica glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. - The
metallization structure 113 includes a plurality of conductive features interconnected to each other and embedded in thedielectric structure 111. The conductive features may include multi-layers of conductive lines, conductive vias, and conductive contacts. The conductive contacts may be formed in the ILDs to electrically connect the conductive lines to the devices; the conductive vias may be formed in the IMDs to electrically connect the conductive lines in different layers. The conductive features of themetallization structure 113 may include metal, metal alloy or a combination thereof. For example, the conductive features may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. In some embodiments, the topmost conductive features of themetallization structure 113 have top surfaces substantially coplanar with a top surface of thedielectric structure 111, but the disclosure is not limited thereto. - In some embodiments, the
passivation layer 116 is formed on theinterconnection structure 114 to cover thedielectric structure 111 and themetallization structure 113. Thepassivation layer 116 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In an embodiment, the material of thepassivation layer 116 is different from an underlying dielectric layer of thedielectric structure 111. For example, the topmost dielectric layer of thedielectric structure 111 includes silicon oxide, while thepassivation layer 116 includes silicon nitride. However, the disclosure is not limited thereto. - The
contact pads 115 are formed over theinterconnection structure 114. Thecontact pads 115 are formed on and penetrating through thepassivation layer 116 to electrically connect to a top conductive feature of theinterconnection structure 114, and may be electrically coupled to the one or more active and/or passive devices through themetallization structure 113. In some embodiments, thecontact pads 115 may include a conductive material such as aluminum, copper, tungsten, silver, gold, a combination thereof, or the like. - The
dielectric layer 117 is formed over theinterconnection structure 114 and thecontact pads 115. In some embodiments, thedielectric layer 117 may include one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. In other embodiments, the dielectric layer may include one or more layers of photo-patternable insulating materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, In some embodiments, the dielectric layer is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. - Referring to
FIG. 1A , thebonding structure 120 is formed on thedielectric layer 117. Thebonding structure 120 includes an insulatinglayer 119 formed on thedielectric layer 117 and thebond pads 123 formed in the insulating layers 119. In some embodiments, thebonding structure 120 further includesdummy pads 125 formed in the insulatinglayer 119. In some embodiments, thebond pads 123 are in direct electrical contact withvias 121 formed in thedielectric layer 117 and penetrating through thepassivation layer 116 to electrically connect to the topmost conductive features of themetallization structure 113. In alternative embodiments, thebond pads 123 are in direct electrical contact with vias (not shown) landing on thecontact pad 115. - In some embodiments, the insulating
layer 119 includes one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like. In some embodiments, the insulatinglayer 119 is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. In some embodiments, the insulatinglayer 119 and the underlying dielectric layer may include a same material. In other embodiments, the insulatinglayer 119 and the underlying dielectric layer may include different materials. - In some embodiments, the
bond pads 123,dummy pads 125 and thevias 121 may include a conductive material such as aluminum, copper, tungsten, silver, gold, a combination thereof, or the like. In some embodiments, a conductive material may be formed over the interconnection structure using, for example, PVD, ALD, electro-chemical plating, electroless plating, a combination thereof, or the like. Subsequently, the conductive material is patterned to form the contact pads using suitable photolithography and etching methods. Thebond pads 123,dummy pads 125 and thevias 121 may be formed in the insulatinglayer 119 using, for example, a damascene process, a dual damascene process, a combination thereof, or the like. In some embodiments, thebond pads 123, thedummy pads 125 and the insulatinglayer 119 are planarized, such that topmost surfaces of thebond pads 123 and thedummy pads 125 are substantially level or coplanar with a topmost surface of the insulatinglayer 119. - Referring to
FIG. 1A , thedie 204 is bonded to the die 104 on the first side of thewafer 100 to start forming a wafer-level die structure moo. The respective process is illustrated as step S10 in the process flow shown inFIG. 14 . Thedie 204 may be a die which has been singulated from another semiconductor wafer. Although onedie 104 and one die 204 are shown in the figures, the number of thedie - The
die 204 and thedie 104 may be the same types of dies or different types of dies, and the types of the dies are not limited in the disclosure. Thedie 204 may be a logic die (e.g., central processing unit, graphics processing unit, system-on-a-chip, microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor dies, micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), the like, or a combination thereof. Also, in some embodiments in which a plurality of dies 204 are bonded to thewafer 100, the dies 204 may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the dies 204 may be the same size (e.g., same heights and/or surface areas). - The
die 204 may includesubstrate 205, one or more active and/or passive devices (not shown), andinterconnection structure 214,contact pads 215, adielectric layer 217, vias 221, and abonding structure 220. Thebonding structure 220 includesbond pads 223,dummy pads 225 and an insulatinglayer 219. In some embodiments, the material and the formation method of thesubstrate 205, theinterconnection structure 214, thecontact pads 215, thedielectric layer 217, thevias 221, and thebonding structure 220 of thedie 204 may be similar to thesubstrate 105, theinterconnection structure 114, thecontact pads 115, thedielectric layer 117, thevias 121 and thebonding structure 120 of thewafer 100, and hence the details are not repeated herein. - In some embodiments, the
die 204 further includeconductive vias 209 formed in thesubstrate 205 and electrically connected to theinterconnection structure 214. In some embodiments, theconductive vias 209 may be arranged as an array, a plurality of arrays, irregularly, or a combination thereof. Theconductive vias 209 may extend into theinterconnection structure 214 to be in physical and electrical contact with the conductive features of theinterconnection structure 214. In some embodiments, theconductive vias 209 are be formed by forming openings in thesubstrate 205 and filling the openings with suitable conductive materials. In some embodiments, the openings may be formed using suitable photolithography and etching methods. The openings may be filled with copper, a copper alloy, silver, gold, tungsten, tantalum, aluminum, aluminum alloys, a combination thereof, or the like, using physical vapor deposition (PVD), atomic layer deposition (ALD), electro-chemical plating, electroless plating, or a combination thereof, the like. In some embodiments, aliner 209 j and/or anadhesive layer 209 i may be formed in the openings before filling the openings with the suitable conductive materials. Theliner 209 j may include dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or the like, or combinations thereof. Theadhesive layer 209 i may include Ta, TaN, Ti, TiN, or combinations thereof. - Various suitable bonding techniques may be applied for the bonding of the die 204 to the
wafer 100. For example, thedie 204 may be bonded to thewafer 100 through hybrid bonding, fusion bonding, or the like, or combinations thereof. For example, the bonding of the die 204 to thewafer 100 may be achieved through hybrid bonding involving at least two types of bonding, including metal-to-metal bonding and non-metal-to-non-metal bonding such as dielectric-to-dielectric bonding, for example. In some embodiments, thebond pads 223 are bonded to thebond pads 123 of the die (or referred to as bottom die) 104, and thedummy pads 225 are bonded to thedummy pads 125 of the die 104 through metal-to-metal direct bonding. In accordance with some embodiments of the present disclosure, the metal-to-metal direct bonding is copper-to-copper direct bonding. Thebond pads 223 may have sizes greater than, equal to, or smaller than the sizes of the respective thebond pads 123. Thedummy pads 225 may have sizes greater than, equal to, or smaller than, the sizes of the respectivedummy bond pads 125. Furthermore, the insulatinglayer 219 may be bonded to the insulatinglayer 119 through dielectric-to-dielectric bonding, which may be fusion bonding, for example, with Si—O—Si bonds generated. - In some embodiments, the bonding process may be performed as discussed below. First, to avoid the occurrence of the unbonded areas (e.g. interface bubbles), the to-be-bonded surfaces of the
die 204 and thedie 104 are processed to be sufficiently clean and smooth. Then, thedie 204 is picked-and-placed on the die 10, thedie 204 and thedie 104 are aligned and placed in physical contact at room temperature with slight pressure to initiate a bonding operation. Thereafter, a thermal treatment such as an annealing process at elevated temperatures is performed to strengthen the chemical bonds between the to-be-bonded surfaces of thedie 204 and thedie 104 and to transform the chemical bonds into covalent bonds. In some embodiments, a bonding interface is formed between thebonding structure 120 of thedie 104 and thebonding structure 220 of the device die 20. In some embodiments, the bonding interface is a hybrid bonding interface including a metal-to-metal bonding interface between thebonding pads 123 and thebonding pads 223, thedummy pads 125 and thedummy pads 225, and a dielectric-to-dielectric bonding interface between thedielectric layer 119 and thedielectric layer 219. - In some embodiments, the
die 204 is bonded to thedie 104 in a face-to-face configuration. That is, the front surface of the die 204 faces thefront surface 104 a of thedie 104. However, the disclosure is not limited thereto. In some embodiments, thedie 204 may be bonded to a die 104′ in a face-to-back configuration as shown inFIG. 12 . In other words, the front surface of the one of the dies 104′ and 204 may face the back surface of the other one of the dies 104′ and 204, or the back surface of thedie 204 may face the back surface of the die 104′. Throughout the specification, a “front surface” of a die refers to a surface close to contact pads, and may also be referred to as an active surface; a “back surface” of a die is a surface opposite to the front surface and may be a surface of the substrate, which may also be referred to as a rear surface. - Referring to
FIG. 1A , after thedie 204 is bonded to thedie 104, a backside grinding process may be performed to thin thedie 204, and theconductive vias 209 may not be revealed after the backside grinding process. As shown inFIG. 1A , in some embodiments, theconductive vias 209 may not be revealed from the top surface (e.g. back surface) 204 b of thedie 204, the backside grinding is stopped when there is a thin layer of thesubstrate 205 covering the conductive via 209. However, the disclosure is not limited thereto. In some other embodiments, theconductive vias 209 are revealed at this time, and the top surfaces of theconductive vias 209 and the top surfaces of theliners 209 j may be substantially coplanar with the top surface (e.g. back surface) of thesubstrate 205. In some embodiments, the backside grinding process may be skipped. In some embodiments, theconductive vias 209 may be revealed after a planarization process is performed to remove a portion of an encapsulation 127 (shown inFIG. 1B ) over the top of thedie 204. - Referring to
FIG. 1B , anencapsulation 127 is formed over and surrounding thedie 204. The respective process is illustrated as step S12 in the process flow shown inFIG. 14 . In some embodiments, theencapsulation 127 includes one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like. In other some embodiments, theencapsulation 127 includes one or more layers of photo-patternable insulating materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, and may be formed using a spin-on coating process, or the like. Such photo-patternable insulating materials may be patterned using similar photolithography methods as a photoresist material. In some embodiments, theencapsulation 127 includes a molding compound, such as an epoxy, a resin, a moldable polymer, a combination thereof, or the like. The molding compound may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In some embodiments, the molding compound is an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around and between the die 204. - Referring to
FIG. 1C , theencapsulation 127 and thedie 204 are planarized, such thatbackside surface 204 c of thedie 204 is substantially level or coplanar with atopmost surface 127 b of theencapsulation 127. In some embodiments, theconductive vias 209 are revealed at this time, and thetop surfaces 209 b of theconductive vias 209 and the top surfaces of theliners 209 j may be substantially coplanar with the top surface (e.g. back surface) 205 b of thesubstrate 205. In such embodiments, theconductive vias 209 may also be referred to as through vias (TVs) 209 or through substrate vias (TSVs) 209. In some embodiments, the planarization process may include a CMP process, a grinding process, an etching process, a combination thereof, or the like. For the sake of simplicity, the layers, the contact pads and elements between thesubstrate 105 and the insulatinglayer 119, and between thesubstrate 205 and the insulatinglayer 219 are not shown inFIG. 1D throughFIG. 1I . -
FIG. 1D throughFIG. 1E illustrate the formation of arecess 205R in thedie 204 according to some embodiments of the disclosure. In some embodiments, therecess 205R is formed through a patterning process by using amask layer 129. The respective process is illustrated as step S14 to S18 in the process flow shown inFIG. 14 . - Referring to
FIG. 1D , themask layer 129 is formed on thedie 104 to cover thetop surface 127 b of theencapsulation 127 and portions of thetop surface 204 b of thedie 204. In some embodiments, themask layer 129 includes a photoresist layer, and may be formed by spin coating. The photoresist layer is then patterned by an acceptable process, such as by using exposing the photoresist layer to light. The patterning forms theopening 101 that exposes thetop surfaces 209 b of theTSVs 209 and a center portion of thetop surface 205 b of thesubstrate 205 around theTSVs 209. - Referring to
FIG. 1D andFIG. 1E , in some embodiments, thesubstrate 205 exposed by theopening 101 is recessed such that arecess 205R is formed across thesubstrate 205, and theTSVs 209 protrude from thesubstrate 205. For example, portions of thesubstrate 205 laterally aside theTSVs 209 may be removed by an etching process, such as wet etching process, dry etching process, or a combination thereof. The etching process may utilize a high etching selectivity ratio between thesubstrate 205 and other adjacent materials (i.e. theTSVs 209 and theliners 209 j). In some embodiments, theliner 209 j may be substantially remaining after the etching process, but the disclosure is not limited thereto. In some embodiments, portions of theliners 209 j may also be removed by the etching process. - After the recessing process is performed, the remaining
substrate 205 covered by themask layer 129 forms sidewalls of therecess 205R, and asurface 205 c of the remainingsubstrate 205 exposed by theopening 101 form a bottom 205-BS of therecess 205R. Therecess 205R may have the depth of 1 μm to 3 μm, for example. In some embodiments, the sidewalls of therecess 205R may be straight, and perpendicular tofront surface 205 a of thesubstrates 205 as shown inFIG. 1E . In some embodiments, the sidewalls of therecess 205R may be inclined, and tapered toward thefront surface 205 a of thesubstrates 205 as shown inFIG. 3 . - The bottom of the
recess 205R exposes thesurface 205 c of thesubstrate 205, and thesurface 205 c of thesubstrate 205 are lower than thetop surface 205 b of thesubstrate 205, and have astep 205S therebetween. Furthermore, thesurface 205 c of thesubstrate 205 are lower than thetop surfaces 209 a of theTSVs 209, so that theTSVs 209 has portions protruded from thesurface 205 c of the substrate 205 (e.g. the bottom 205-BS of therecess 205R). - The
top surface 127 b of theencapsulation 127 and thetop surface 205 b of theportion 205M of thesubstrate 205 are covered by themask layer 129 to prevent/reduce etching of theencapsulation 127, and not exposed by therecess 205R during the etching process. Therefore, thetop surface 127 b of theencapsulation 127 may be protected from pit defects and chamber contamination may be reduced during theTSVs 209 are revealed. -
FIG. 1F throughFIG. 1G illustrate the formation of anisolation layer 130 embedded in thesubstrate 205 of thedie 204 according to some embodiments of the disclosure. In some embodiments, theisolation layer 130 is formed as a bulk layer and separated from theencapsulation 127. The respective process is illustrated as step S18 to step S24 in the process flow shown inFIG. 14 . - Referring to
FIG. 1F , themask layer 129 is removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Anisolation material layer 130′ is formed on thedie 204 and theencapsulation 127 to cover thetop surface 205 a of thesubstrate 205, thetop surfaces 209 a of theTSVs 209 and thetop surface 127 b of theencapsulation 127 and fill therecess 205R. In some embodiments, theisolation material layer 130′ is formed to have a thickness at least equal to the height of therecess 205R (e.g. the thickness of the portion of theTSVs 209 protruded from thesurface 205 c of the substrate 205). In other words, theisolation material layer 130′ fully fills therecess 205R. In some embodiments, theisolation material layer 130′ is a conformal layer, that is, theisolation material layer 130′ has a substantially equal thickness within process variations extending along the region on which theisolation material layer 130′ is formed. - The
isolation material layer 130′ may include a dielectric material such as silicon nitride, although other dielectric materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer, which may be a photo-sensitive material such as PBO, polyimide, or BCB, a low-K dielectric material such as PSG, BPSG, FSG, SiOxCy, SOG, spin-on polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like may also be used for theisolation material layer 130′. Theisolation material layer 130′ may be formed using a suitable deposition process, such as CVD, atomic layer deposition (ALD), or the like. In some embodiments, theisolation material layer 130′ may be a single layer as shown inFIG. 1F . In some embodiments, theisolation material layer 130′ may be multiple layers as shown inFIG. 4C , which will be described in detail later. - Referring to
FIG. 1F andFIG. 1G , a planarization process is performed to remove a portion of theisolation material layer 130′ over thetop surface 209 a of theTSVs 209 and thetop surface 205 b of thesubstrate 205, so as to reveal theTSVs 209, and anisolation layer 130A is formed. The planarization process may include a CMP process. -
FIG. 2A illustrates a top view ofFIG. 1G .FIG. 2B shows an enlarged view of the region A inFIG. 2A .FIG. 2C shows a cross-sectional view of a line I-I inFIG. 2B . - Referring to
FIG. 1G andFIG. 2A toFIG. 2C , theisolation layer 130A is embedded in thesubstrate 205 and laterally around theTSVs 209. Theisolation layer 130A surrounds the upper sidewalls of theTSVs 209. The sidewalls and the bottom of theisolation layer 130A are surrounded by thesubstrate 205. Theportion 205M of thesubstrate 205 surrounded by theencapsulation 127. In other words, the isolation layers 130 are laterally separated from theencapsulation 127 by theportion 205M of thesubstrate 205 which are covered by themask layer 129 previously, and thesidewalls 130S of theisolation layer 130A and sidewalls 127S of theencapsulation 127 have a non-zero distance d1. In some embodiments, thesidewalls 130S of the isolation layers 130 may be straight, and perpendicular tofront surface 205 a of thesubstrates 205, but the disclosure is not limited thereto. - Referring to
FIG. 1G , in some embodiments, atop surface 130 a of theisolation layer 130A may be substantially coplanar within process variations with thetop surfaces 209 a of theTSVs 209, thetop surface 205 b of thesubstrate 205, and thetop surface 127 b of theencapsulation 127. In some embodiments, theisolation layer 130A may further extend to cover thetop surface 127 b of the encapsulation 127 (not shown). - Referring to
FIGS. 1G, 2A, 2B and 2C , theisolation layer 130A is a bulk layer (or referred to as a whole layer or a continuous layer). Theisolation layer 130A may have various shapes, such as a square, a rectangle, a circle, and an ellipse, or a combination thereof. The upper sidewalls of theTSVs 209 is surrounded by theisolation 130A, the middle sidewalls of theTSVs 209 is surrounded by thesubstrate 205, and the lower sidewalls of theTSVs 209 is surrounded by theinterconnection structure 214. Further, in some embodiments, theadhesive layer 209 i and theliner 209 j may be sandwiched between theTSVs 209 and theisolation 130A, theTSVs 209 and thesubstrate 205, and theTSVs 209 andinterconnection structure 214. -
FIG. 1H throughFIG. 1J illustrate the formation of abuffer layer 137,conductive terminals 143, and an insulatinglayer 147 over theencapsulation 127 and thedie 204 according to some embodiments of the disclosure. The respective process is illustrated as step S20 in the process flow shown inFIG. 14 . - Referring to
FIG. 1H , thebuffer layer 137 is formed over theencapsulation 127 and thedie 204. Thebuffer layer 137 may include a single layer or multiple layers. Thebuffer layer 137 may include silicon oxide, silicon nitride, silicon oxynitride, USG, TEOS, a polymer, or a combination thereof. The polymer includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. The forming method of thebuffer layer 137 include suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), lamination or the like. - Thereafter,
openings 151 are formed in thebuffer layer 137. Theopenings 121 may have sizes greater than, equal to, or smaller than the sizes of theTSVs 209. In some embodiments, theopenings 151 are via holes and penetrate through thebuffer layer 137 to expose thecorresponding TSVs 209. In some embodiments, theopenings 151 are trenches and penetrate through thebuffer layer 137 to expose theTSVs 209. Theopenings 151 are formed to further expose theisolation layer 130A around theTSVs 209. The forming method of theopenings 151 may include photolithography and etching processes, a laser drilling process, or a combination thereof. In some embodiments, theisolation layer 130A and thebuffer layer 137 have different materials, so theisolation layer 130A may be used as an etching stop layer during the etching process for forming theopenings 151. The sidewalls of theopenings 151 may be straight or inclined. In some embodiments, the sidewalls of theopenings 151 is inclined, and the taper toward thefront surface 205 a of thesubstrates 205, but the disclosure is not limited thereto - Referring to
FIG. 1I , theconductive terminals 143 are formed on thebuffer layer 137 and in theopenings 151 to electrically couple to theTSVs 209. Theconductive terminals 143 may be referred to as dieconnectors 143. In some embodiment, theconductive terminals 143 are metal pillars such as a copper pillar. The material of theconductive terminal 143 may include copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). For example, theconductive terminals 143 may be formed of a Sn—Ag alloy, a Sn—Cu alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free or lead-containing. - In some embodiments in which the
conductive terminals 143 are metal pillars, theconductive terminal 143 may include aseed layer 139 in theopenings 151, and aconductive material 141 on theseed layer 139. As an example to form theconductive terminals 143, theseed layer 139 is formed on the surfaces of theopenings 151 and a portion of the top surface of thebuffer layer 137. In some embodiments, theseed layer 139 is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. Theseed layer 139 may include copper, titanium, titanium nitride, tantalum, tantalum nitride, or the like and may be formed by ALD, CVD, Physical Vapor Deposition (PVD), or the like. For example, theseed layer 139 comprises a titanium layer and a copper layer over the titanium layer. Theseed layer 139 may be formed using, for example, PVD or the like. A photoresist is formed and patterned on theseed layer 139. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The patterning forms openings through the photoresist to expose theseed layer 139. Theconductive material 141 is formed in the openings of the photoresist and on the exposed portions of theseed layer 139. Theconductive material 141 may be formed by plating, such as electroplating or electroless plating, or the like. Theconductive material 141 may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of theseed layer 139 on which theconductive material 141 is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of theseed layer 139 are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of theseed layer 139 andconductive material 141 form theconductive terminals 143. - In some embodiments, the bottoms of the
conductive terminals 143 land on theTSVs 209 as shown in an enlargeview 303. In some embodiments, the bottoms of theconductive terminals 143 land on theTSVs 209 and theliners 209 j as shown in an enlargeview 302. In some embodiment, the bottoms of theconductive terminals 143 land on theTSVs 209, theliners 209 j and theisolation layer 130A, and theconductive terminals 143 is isolated from thesubstrate 205 by theisolation layer 130A as shown in an enlargeview 301. - In some embodiments, the metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments,
conductive caps 145 are formed on the top of theconductive terminals 143. The conductive caps may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. - Referring to
FIG. 1I andFIG. 1J , a chip-probing process or other suitable chip testing process is performed on thewafer 100 to identify known good dies and bad dies. Theconductive caps 145 are removed after the chip-probing process. Thereafter, the insulatinglayer 147 is formed on theconductive terminals 143 and thebuffer layer 137. In some embodiments, the insulatinglayer 147 may include one or more layers of non-photo-patternable insulating materials such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and may be formed using CVD, PVD, ALD, a spin-on coating process, a combination thereof, or the like. In other embodiments, the insulatinglayer 147 may include one or more layers of photo-patternable insulating materials such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, and may be formed using a spin-on coating process, or the like. Such photo-patternable insulating materials may be patterned using similar photolithography methods as a photoresist material. In some embodiments, the insulatinglayer 147 is planarized using a CMP process, a grinding process, an etching process, a combination thereof, or the like. - In some embodiments, thereafter, the
wafer 100 is singulated, for example, by sawing, laser ablation, etching, a combination thereof, or the like to formindividual 3DIC structures 1002 and one of the3DIC structures 1002 is shown inFIG. 1J . The3DIC structures 1002 is also referred to as a SoIC structure. The respective process is illustrated as step S26 in the process flow shown inFIG. 10 . -
FIG. 3 toFIG. 12 are schematic cross-sectional views illustratingvarious 3DIC structures - Referring to
FIG. 3 , the3DIC structure 1003 is similar to the3DIC structure 1002, the difference is thatsidewalls 130S of anisolation layer 130B of the3DIC structure 1003 is inclined, and tapered toward thefront surface 205 a of thesubstrates 205, but the disclosure is not limited thereto. The shape of the sidewalls 130S of theisolation layer 130B may be formed by tuning etching parameters of an etching process for formingrecess 205R in thesubstrate 205. - Referring to
FIG. 4C , the3DIC structures 1004 is similar to the3DIC structure 1002, wherein anisolation layer 130C of the3DIC structures 1004 includes multiple layers. The multiple layers includes dielectric materials such as silicon nitride, although other dielectric materials such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, oxygen-doped silicon carbide, nitrogen-doped silicon carbide, a polymer, which may be a photo-sensitive material such as PBO, polyimide, or BCB, a low-K dielectric material such as PSG, BPSG, FSG, SiOxCy, SOG, spin-on polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. In some embodiments, theisolation layer 130C of the3DIC structure 1004 includes anitride layer 130 1 such as a silicon nitride layer, and anoxide layer 130 2 such as a silicon oxide layer. Thenitride layer 130 1 is formed on thesubstrate 205 to provide good water resistance, while theoxide layer 130 2 is formed on thenitride layer 130 1 to release the stress form thenitride layer 130 1. -
FIG. 4A toFIG. 4C are schematic cross-sectional views illustrating a method of forming a3DIC structure 1004 according to some embodiments of the disclosure. - Referring to
FIG. 4A toFIG. 4C , theoxide layer 130 2 and thenitride layer 130 1 may be formed by various method. In some embodiments, anitride material layer 130 1′ is conformally formed and has a substantially equal thickness extending along thetop surfaces 127 b of theinsulation 127, thetop surface 205 b of the substrate, the sidewalls and bottom ofrecess 205R, the sidewalls of theliners 209 j, and thetop surface 209 a of theTSVs 209. Anoxide material layer 130 2′ is then formed on thenitride layer 130 1 as shown inFIG. 4A . A planarization process is performed to remove a portion of theoxide material layer 130 2′ and thenitride material layer 130 1′, so as to reveal theTSVs 209, and theoxide layer 130 2 and thenitride layer 130 1 are formed as shown inFIG. 4B . Thereafter, abuffer layer 137,conductive terminals 143, and an insulatinglayer 147 over theencapsulation 127 and thedie 204 as shown inFIG. 4C . - The
3DIC structure 1004 may be a3DIC structure FIG. 5A toFIG. 5D .FIG. 5A toFIG. 5D show enlarged views of a region B inFIG. 4C in accordance with various embodiments. - Referring to
FIG. 5A toFIG. 5 D, thenitride layer 130 1 is filled in a space of therecess 205R, so that the bottom surface of thenitride layer 130 1 is in contact with thesubstrate 205, and the sidewalls of thenitride layer 130 1 is in contact with theliner 209 j. Theoxide layer 130 2 is filled in a space of therecess 205R remained from thenitride layer 130 1. - In some embodiments, the top surfaces of the
nitride layer 130 1 and theoxide layer 130 2 are in contact with thebuffer layer 137, and not in contact with theconductive terminal 143 as shown inFIG. 5A . In some embodiments, the top surfaces of thenitride layer 130 1 is in contact with theconductive terminal 143, and theoxide layer 130 2 are in contact with thebuffer layer 137 as shown inFIG. 5B . In some embodiments, the top surfaces of thenitride layer 130 1 is in contact with theconductive terminal 143, and theoxide layer 130 2 is in contact with theconductive terminal 143 and thebuffer layer 137 as shown inFIG. 5C . In some embodiments, the top surface of thenitride layer 130 1 is in contact with theconductive terminals 143, and thebuffer layer 137, and theoxide layer 130 2 is in contact with thebuffer layer 137 as shown inFIG. 5D . In some embodiments, the top surface of theoxide layer 130 2 is substantially coplanar with the top surface of thenitride layer 130 1, thetop surface 205 b of thesubstrate 205, the top surface 207 a of theencapsulation 127, and the top surfaces of theliner 209 j, theadhesive layer 209 i, and theTSVs 209. -
FIG. 6A toFIG. 6G are schematic various views illustrating3DIC structures 1006 according to some embodiments of the disclosure.FIG. 6B toFIG. 6D show top views of a line II-II inFIG. 6A .FIG. 6F andFIG. 6G show top views of a line II-II inFIG. 6E . - Referring to
FIG. 6A toFIG. 6G , the3DIC structures 1006 are similar to the3DIC structure 1002, wherein a plurality ofisolation parts 130D is utilized. Each of the plurality ofisolation parts 130D may have a form such as those discussed above with reference to 130A, 130B, and/or 130C. In some embodiments, one or each of the plurality ofisolation parts 130D may be a circle around a corresponding one or more of theTSVs 209 as shown inFIG. 6B andFIG. 6F , a strip around a corresponding one or more of theTSVs 209 as shown inFIG. 6D andFIG. 6G , or a bend line around a corresponding one or more of theTSVs 209 as shown inFIGS. 6D and 6H . However, the embodiment of the present disclosure is not limited to these, the plurality ofisolation parts 130D may include a variety of shapes, and these shapes may be regular or irregular. - Each of the plurality of
isolation parts 130D may surround the same number(s) of theTSVs 209. In some embodiments, each of the plurality ofisolation parts 130D surrounds oneTSV 209 as shown inFIG. 6B andFIG. 6F . In some embodiments, each of the plurality ofisolation parts 130D surrounds fourTSVs 209 as shown inFIG. 6C andFIG. 6G . The plurality ofisolation parts 130D may have approximately the same width W and the same area. The width w1 or w2 of a portion of the plurality ofisolation parts 130D between the sidewall of a correspondingdielectric layer 209 j to a nearest edge of theisolation part 130D is about 0.5 μm to 1.5 μm, for example. - In some embodiments, each of the plurality of
isolation parts 130D is arranged to align with the center or center line C of thecorresponding TSV 209 as shown inFIG. 6A toFIG. 6D . In some embodiments, each of the plurality ofisolation parts 130D is arranged to be offset from the center or center line C of thecorresponding TSV 209 as shown inFIG. 6E toFIG. 6H . The distance dpp between adjacent ones of the plurality ofisolation parts 130D may be the same as or different. -
FIG. 7A andFIG. 7B are schematic various views illustrating3DIC structures 1007 according to some embodiments of the disclosure.FIG. 7B shows a top view of a line II-II inFIG. 7A . - Referring to
FIGS. 7A and 7B , the3DIC structures 1007 is similar to the3DIC structure 1006, wherein anisolation layer 130E of the3DIC structure 1006 includesisolation parts isolation parts isolation parts TSVs 209. Further, theisolation parts isolation part 130E1 surrounds onecolumn TSVs 209, and theisolation part 130E2 surrounds twocolumns TSVs 209, and the width W1 of theisolation part 130E1 is less than the width W2 of theisolation part 130E2, but the disclosure is not limited thereto. - The
3DIC structure 1007 further includes adummy terminal 143P disposed between conductive terminal 143 as shown inFIG. 7A . Thedummy terminal 143P is floating disposed on thebuffer layer 137, and does not penetrate into thebuffer layer 137. TheTSVs 209 are not disposed below thedummy terminal 143P and theisolation layer 130E does not extend below thedummy terminal 143P. In some embodiments, the distance dpp between the isolation parts P1 and P2 is greater than the width WDT of thedummy terminal 143P in some embodiments as shown inFIGS. 7A and 7B . -
FIG. 8A toFIG. 8C are schematic various views illustrating3DIC structures 1008 according to some embodiments of the disclosure.FIG. 8B andFIG. 8C show top views of a line II-II inFIG. 8A . - Referring to
FIG. 8A toFIG. 8C , the3DIC structures 1008 is similar to the3DIC structure 1007, wherein anisolation layer 130F of the3DIC structure 1009 includesisolation parts isolation parts - The die 205 of the
3DIC structure 1008 includes a first region R1 and a second region R2. The density of theTSVs 209 in the first region R1 is lower than the density of theTSVs 209 in the second region R2. In some embodiments, for CMP uniformity, each of theisolation parts TSVs 209 as shown inFIG. 8B . In some embodiments, for CMP uniformity, each of theisolation parts TSVs 209, and each of theisolation parts TSVs 209 as shown inFIG. 8C . Theisolation parts isolation parts dummy terminal 143P to further improve CMP uniformity. In some embodiments, theisolation parts TSVs 209 respectively. Theisolation part 130F2 is arranged to be offset from the center line C2 of thecorresponding TSVs 209. -
FIG. 9A toFIG. 9C are schematic various views illustrating3DIC structures 1009 according to some embodiments of the disclosure.FIG. 9B andFIG. 9C show top views of a line II-II inFIG. 9A . - Referring to
FIG. 9A toFIG. 9C , the3DIC structures 1009 is similar to the3DIC structure 1006, the difference is that anisolation layer 130G of the3DIC structure 1009 includesisolation parts dummy parts 130P separated from each other. Each of theisolation parts dummy parts 130P may have a structure such as those discussed above with reference to 130A, 130B, and/or 130C. Theisolation parts TSVs 209. Theisolation parts dummy parts 130P includes dummy parts 130P1 and 130P2. The dummy parts 130P1 and 130P2 do not surround anyTSV 209. - The dummy part 130P1 is disposed below the
dummy terminal 143P, and laterally separated from theisolation parts dummy part 130 P2 1 and 130P2 2 is laterally separated from theisolation parts encapsulation 127. Thedummy terminal 143P and theconductive terminals 143 are not provided on the dummy parts 130P2 1 and 130P2 2, and theTSVs 209 are not provided to penetrate through the dummy part 130P2. - The dummy parts 130P1, 130P2 1 and 130P2 2 may have the same shape or different shapes. The shape of the dummy parts 130P1, 130P2 1 and 130P2 2 may be the same as or different from the shape of the
isolation parts FIG. 9B . In some embodiments, the dummy parts 130P1, 130P2 1 and 130P2 2, and theisolation parts FIG. 9C . However, the embodiments of the present disclosure are not limited thereto, and the shapes of thedummy parts 130 P1, 130P2 1 and 130 P2 2, and theisolation parts - The dummy parts 130P1, 130P2 1 and 130P2 2 have widths W1′, W2′ and W3′, and the widths W1′, W2′ and W3′ may be the same or different. Further, the widths W1′, W2′ and W3′may be the same as or different from the width W of the
isolation parts isolation part 130G1 may be the same as or different from the distance d1 R between the dummy parts 130P1 and the isolation part P2. The distance d2 L between the dummy parts 130P2 1 and theencapsulation 127 may be the same as or different from the distance d2 R between the dummy parts 130P2 1 and theisolation part 130G1. The distance d3 L between the dummy parts 130P2 2 and theisolation part 130G3 may be the same as or different from the distance d3 R between the dummy parts 130P2 2 and theencapsulation 127. -
FIG. 10 toFIG. 12 are schematic cross-sectional views illustrating3DIC structures - Referring to
FIG. 10 andFIG. 11 , the3DIC structures 3DIC structure 1002, wherein the3DIC structures redistribution structure 131 formed over thebackside surface 204 c of the die 204 to electrically connect theTSVs 209 of thedie 204 and/or to external devices. A 3DIC structure similar to the3DIC structure 1002 discussed above is shown for illustrative purposes, and in some embodiments, other 3DIC structures such as those discussed above may be used. Theredistribution structure 131 may include one or more dielectric layer(s) 133 and respective metallization pattern(s) 135 in the one or more dielectric layer(s) 133. Themetallization patterns 135 are sometimes referred to as redistribution lines (RDLs). Thedielectric layers 133 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material, such as PSG, BPSG, FSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. Thedielectric layers 133 may be deposited by any suitable method, such as spinning, CVD, PECVD, HDP-CVD, or the like. Themetallization patterns 135 includeconductive lines 135M as shown inFIG. 10 . In some embodiments, themetallization patterns 135 includeconductive lines 135M and conductive vias CV as shown inFIG. 11 . The sidewalls of theconductive vias 135V and theconductive lines 135M may be straight or inclined. In some embodiments, the conductive via V has inclined sidewall and is tapered toward thesubstrate 205. - The
metallization patterns 135 may be formed in thedielectric layer 133, for example, by using photolithography techniques to deposit and pattern a photoresist material on thedielectric layer 133 to expose portions of thedielectric layer 133 that are to become themetallization pattern 135. An etch process, such as an anisotropic dry etch process, may be used to create recesses and/or openings in thedielectric layer 133 corresponding to the exposed portions of thedielectric layer 133. The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may include one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, deposited by ALD, or the like, and the conductive material may include copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVD, or the like. Any excessive diffusion barrier layer and/or conductive material on the dielectric layer may be removed, such as by using a CMP. - An
isolation layer 130G of the3DIC structures 1010 may be similar toisolation layer isolation layer 130H of the3DIC structures 1011 may be similar toisolation layer - In some embodiments, at least one Integrated Passive Device (IPD) (not shown) may also be disposed on the
redistribution structure 131. The IPD may be fabricated using standard wafer fabrication technologies such as thin film and photolithography processing, and may be mounted on theredistribution structure 131 through, for example, flip-chip bonding or wire bonding, etc. - Referring to
FIG. 12 , the3DIC structure 1012 is similar to the3DIC structure 3DIC structures 1012 may be similar toisolation layer FIG. 12 , thedie 204 is bonded to a die 104′ in a face-to-back configuration. That is, thefront surface 204 a of the die 204 faces theback surface 104 b′ of the die 104′. The die 104′ is similar to thedie 104, wherein thedie 104′ further includesTSVs 109′ in thesubstrate 105′ and abonding structure 120′ on the back surface 105 b′ of thesubstrate 105. TheTSVs 109′ is similar to theTSVs 209. In some embodiments, theTSVs 109′ penetrate through thesubstrate 105′ and are connected to aninterconnection structure 114′ formed on the front surface 105 a′ of thesubstrate 105′. In some embodiments, aliner 109 j′ and/or anadhesive layer 109 i′ may be formed before forming theTSVs 109′, so that theTSVs 109′ may be separated from thesubstrate 105′. - The
bonding structure 120′ is formed on the back surface 105 b′ of thesubstrate 105′ and bonded with thebonding structure 220 of thedie 204. Thebonding structure 120′ is similar to thebonding structure 120. In some embodiments, thebonding structure 120′ may includebond pads 123′ anddummy pads 125′. Thebond pads 123′ anddummy pads 125′ may connect thebond pads 223 and thedummy pads 225 of the die 204 to theinterconnection structure 114′ of the die 104′ as the3DIC structure 1002. As shown inFIG. 12 , thebond pads 123′ of thebonding structure 120′ are connected to theinterconnection structure 114′ through theTSVs 109′. -
FIG. 13A throughFIG. 13E illustrate cross-sectional views of forming a package, in accordance with some embodiments. - Referring to
FIG. 13A , acarrier substrate 102 is provided, and arelease layer 124 is formed on thecarrier substrate 102. Thecarrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. Thecarrier substrate 102 may be a wafer, such that multiple packages may be formed on thecarrier substrate 102 simultaneously. Therelease layer 124 may be formed of a polymer-based material, which may be removed along with thecarrier substrate 102 from the overlying structures that will be formed in subsequent steps. In some embodiments, therelease layer 124 is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In some embodiments, therelease layer 124 may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. Therelease layer 124 may be dispensed as a liquid and cured, may be a laminate film laminated onto thecarrier substrate 102, or may be the like. The top surface of therelease layer 124 may be leveled and may have a high degree of planarity. - A
dielectric layer 108 is formed on therelease layer 124. In some embodiments, thedielectric layer 108 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, thedielectric layer 108 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. Thedielectric layer 108 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. - Referring to
FIG. 13A ,conductive pillars 118 are formed on therelease layer 124. As an example to form theconductive pillars 118, a seed layer is formed over therelease layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. For example, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form theconductive pillars 118. - Referring to
FIG. 13B , the3DIC structures 1002 are adhered to thedielectric layer 108 by an adhesive 128. The3DIC structures 1002 are shown for illustrative purposes, and in some embodiments, other 3DIC structures discussed above may be used. The adhesive 128 is on back-side surfaces of the3DIC structures 1002 and adheres the3DIC structures 1002 to therelease layer 124. The adhesive 128 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. - Referring to
FIG. 13C , anencapsulant 142 is formed on the various components. After formation, theencapsulant 142 laterally encapsulates theconductive pillars 118 and3DIC structures 1002. In some embodiments, theencapsulant 142 includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In some other embodiments, theencapsulant 142 includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process. In alternative embodiments, theencapsulant 142 includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. - In some embodiments, the
encapsulant 142 includes a composite material including a base material (such as polymer) and a plurality of fillers in the base material. The filler may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers may include silicon oxide, aluminum oxide, boron nitride, alumina, silica, or the like, for example. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the fillers are spherical particles, or the like. The cross-section shape of the filler may be circle, oval, or any other shape. In some embodiments, the fillers include solid fillers, but the disclosure is not limited thereto. In some embodiments, a small portion of the fillers may be hollow fillers. - The
encapsulant 142 may be applied by compression molding, transfer molding, spin-coating, lamination, deposition, or similar processes, and may be formed over thecarrier substrate 102 such that theconductive pillars 118 and/or the3DIC structures 1002 are buried or covered. Theencapsulant 142 is then cured. Theconductive pillars 118 penetrate theencapsulant 142, and theconductive pillars 118 are sometimes referred to as throughvias 118 or through integrated fan-out vias (TIVs) 118. - Referring to
FIG. 13C , a planarization process is then performed on theencapsulant 142 to remove a portion of theencapsulant 142, such that the top surfaces of the throughvias 118 and the conductive terminals (die connectors) 143 are exposed. In some embodiments in which the top surfaces of the throughvias 118 and the front-side surfaces of the3DIC structures 1002 are not coplanar, portions of the throughvias 118 or/and portions of the dielectric material 140 may also be removed by the planarization process. In some embodiments, top surfaces of the throughvias 118, theconductive terminals 143, the insulatinglayer 147, and theencapsulant 142 are substantially coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted, for example, if the throughvias 118 and theconductive terminals 143 are already exposed. - Referring to
FIG. 13D , a front-side redistribution structure 144 is formed over front-side surfaces of the throughvias 118, theencapsulant 142, and the3DIC structures 1002. The front-side redistribution structure 144 includesdielectric layers metallization patterns metallization patterns - As an example to form the front-side redistribution structure 144, the
dielectric layer 146 is deposited on theencapsulant 142, the throughvias 118, and theconductive terminals 143. In some embodiments, thedielectric layer 146 is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. Thedielectric layer 146 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. Thedielectric layer 146 is then patterned. The patterning forms openings exposing portions of the throughvias 118 and theconductive terminals 143. The patterning may be by an acceptable process, such as by exposing thedielectric layer 146 to light when thedielectric layer 146 is a photo-sensitive material or by etching using, for example, an anisotropic etch. If thedielectric layer 146 is a photo-sensitive material, thedielectric layer 146 may be developed after the exposure. - The
metallization pattern 148 is then formed. Themetallization pattern 148 includes conductive lines CL on and extending along the top surface of thedielectric layer 146. Themetallization pattern 148 further includes conductive vias V extending through thedielectric layer 146 to be physically and electrically connected to the throughvias 118 and the3DIC structures 1002. The sidewalls of theconductive vias 148V and theconductive lines 148C may be straight or inclined. In some embodiments, the conductive via V has inclined sidewall and is tapered toward the3DIC structures 1002. To form themetallization pattern 148, a seed layer is formed over thedielectric layer 146 and in the openings extending through thedielectric layer 146. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to themetallization pattern 148. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form themetallization pattern 148. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. - The
dielectric layers metallization patterns 152, 156 are formed alternately. Thedielectric layer dielectric layer 146, and may be formed of the same material as thedielectric layer 146. Themetallization patterns 152 and 156 may includeconductive lines conductive vias metallization patterns 152 and 156 may be formed in a manner similar to themetallization pattern 148, and may be formed of the same material as themetallization pattern 148. TheUBMs 160 are optionally formed on and extending through thedielectric layer 158. TheUBMs 160 may be formed in a manner similar to themetallization pattern 148, and may be formed of the same material as themetallization pattern 148. - Referring to
FIG. 13D ,conductive connectors 162 are formed on theUBMs 160. Theconductive connectors 162 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. Theconductive connectors 162 comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. In another embodiment, theconductive connectors 162 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, theconductive connectors 162 are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow process may be performed in order to shape the material into the desired bump shapes. - Referring to
FIGS. 13D and 13E , a carrier substrate de-bonding is performed to detach (or “de-bond”) thecarrier substrate 102 from thedielectric layer 108 to form apackage 166. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on therelease layer 124 so that therelease layer 124 decomposes under the heat of the light and thecarrier substrate 102 may be removed. Thepackage 166 is then flipped over and placed on a tape (not shown). - Referring to
FIG. 13E , atop package 500 may be bonded topackage 166. Thetop package 500 includes asubstrate 502 and one or more stacked dies (or dies) 508 coupled to thesubstrate 502. Thesubstrate 502 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, thesubstrate 502 may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Thesubstrate 502 is, in some embodiments, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Other materials that may be used for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used forsubstrate 502. - The
substrate 502 may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for thetop package 500. The devices may be formed using any suitable methods. - The
substrate 502 may also include metallization layers (not shown) and throughvias 506. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, thesubstrate 502 is substantially free of active and passive devices. - The
substrate 502 may havebond pads 503 on a first side thesubstrate 502 to couple to the stacked dies 508, andbond pads 504 on a second side of thesubstrate 502, the second side being opposite the first side of thesubstrate 502, to couple to theconductive connectors 168. In some embodiments, thebond pads substrate 502. The recesses may be formed to allow thebond pads bond pads bond pads bond pads bond pads bond pads UBMs 160. - In the illustrated embodiment, the stacked dies 508 are coupled to the
substrate 502 bywire bonds 510, although other connections may be used, such as conductive bumps. In some embodiments, the stacked dies 508 are stacked memory dies. For example, the stacked memory dies 508 may include low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like memory modules. - In some embodiments, the stacked dies 508 and the
wire bonds 510 may be encapsulated by amolding material 512. Themolding material 512 may be molded on the stacked dies 508 and thewire bonds 510, for example, using compression molding. In some embodiments, themolding material 512 is a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure themolding material 512, wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof. - In some embodiments, the stacked dies 508 and the
wire bonds 510 are buried in themolding material 512, and after the curing of themolding material 512, a planarization step, such as a grinding, is performed to remove excess portions of themolding material 512 and provide a substantially planar surface for the top packages 500. - After the
top packages 500 are formed, thetop packages 500 are bonded to the InFO packages 166 by way of theconductive connectors 168 and thebond pads 504. In some embodiments, the stacked memory dies 508 may be coupled to the3DIC structure 1002 through thewire bonds 510, thebond pads vias 506, theconductive connectors 168, and the throughvias 118. - The
conductive connectors 168 may be similar to theconductive connectors 162 described above and the description is not repeated herein, although theconductive connectors conductive connectors 168, theconductive connectors 168 are coated with a flux (not shown), such as a no-clean flux. Theconductive connectors 168 may be dipped in the flux or the flux may be jetted onto theconductive connectors 168. - In some embodiments, the
conductive connectors 168 may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after thetop package 500 is attached to thepackage 166. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing theconductive connectors 168. In some embodiments, anunderfill 170 may be formed between thetop package 500 and thepackage 166 and surrounding theconductive connectors 168. Theunderfill 170 may be formed by a capillary flow process after thetop package 500 is attached or may be formed by a suitable deposition method before thetop package 500 is attached. - The bonding between the
top package 500 and thepackage 166 may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding. In an embodiment, thetop package 500 is bonded to thepackage 166 by a reflow process. During this reflow process, theconductive connectors 168 are in contact with thebond pads 504 and the throughvias 118 to physically and electrically couple thetop package 500 to thepackage 166. - Based on the above discussions, it can be seen that the present disclosure offers various advantages. It is understood, however, that not all advantages are necessarily discussed herein, and other embodiments may offer different advantages, and that no particular advantage is required for all embodiments. In some embodiments, the top surface of the encapsulation and the top surface of the portion of the substrate are covered by the mask layer to prevent/reduce etching of the encapsulation, and not exposed by the recess during the etching process. Therefore, the top surface of the encapsulation may be protected from pit defects and chamber contamination may be reduced during the TSVs is revealed.
- Various embodiments were discussed above. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
- In an embodiment, a package comprises a first die, wherein the first die comprises a plurality of through vias from a first surface of the first die toward a second surface of the first die; a second die disposed below the first die, wherein the second surface of the first die is bonded to the second die; an isolation layer disposed in the first die, wherein the plurality of through vias extend through the isolation layer; an encapsulation laterally surrounding the first die, wherein the encapsulation is laterally separated from the isolation layer; a buffer layer disposed over the first die, the isolation layer, and the encapsulation; and a plurality of conductive terminals disposed over the isolation layer, wherein the plurality of conductive terminals is electrically connected to corresponding ones of the plurality of through vias. In an embodiment, the isolation layer comprises a bulk layer surrounding the plurality of through vias in the first die. In an embodiment, the isolation layer comprises a plurality of isolation parts, wherein each isolation part of the plurality of isolation parts surround at least one through via of the plurality of through vias. In an embodiment, each isolation part of the plurality of isolation parts surrounds a same number of the plurality of through vias. In an embodiment, the plurality of isolation parts comprises a first isolation part and a second isolation part, wherein the first isolation part surrounds a first number of through vias of the plurality of through vias, wherein the second isolation part surrounds a second number of through vias of the plurality of through vias, wherein the first number is different than the second number. In an embodiment, each isolation part of the plurality of isolation parts has a same width. In an embodiment, the plurality of isolation parts comprises a first isolation part and a second isolation part, wherein the first isolation part has a first width, wherein the second isolation part has a second width, wherein the first width is different than the second width. In an embodiment, the isolation layer comprises a dummy isolation part separated from the plurality of isolation parts, the dummy isolation part being disposed between adjacent ones of the plurality of isolation parts, and wherein no through via of the plurality of through vias penetrate the dummy isolation part. In an embodiment, the isolation layer comprises a dummy isolation part separate from the plurality of isolation parts, the dummy isolation part being disposed between a first isolation part of the plurality of isolation parts and the encapsulation, wherein the first isolation part is an isolation part closest to an edge of the first die, and wherein no through via of the plurality of through vias penetrate the dummy isolation part.
- In an embodiment, a package comprises a first die, wherein the first die comprises first substrate, the first die further comprising a first through via and a second through via extending from a top surface of the first substrate toward a bottom surface of the first die; an isolation layer disposed in a recess in the top surface of the first substrate, the isolation layer surrounding the first through via and the second through via, wherein the first substrate surrounds the isolation layer in a top view; and a first encapsulation laterally surrounding the first die, wherein the first substrate is interposed between the first isolation layer and the first encapsulation. In an embodiment, the top surface of the first substrate is level with a top surface of the first encapsulation and a top surface of the isolation layer. In an embodiment, the package further comprises a buffer layer disposed over the first encapsulation, the first die and the isolation layer, wherein a bottom surface of the buffer layer is in contact with the top surfaces of the first encapsulation, the first die and the isolation layer. In an embodiment, the package further comprises a dummy terminal over the buffer layer, wherein the isolation layer extends below the dummy terminal. In an embodiment, the package further comprises a dummy terminal over the buffer layer, wherein the isolation layer does not extend below the dummy terminal. In an embodiment, the isolation layer comprises multiple layers.
- In an embodiment, a method of manufacturing a package structure comprises bonding a first surface of a first die to a second die, wherein the first die comprises a first through via; forming an encapsulation laterally aside the first die; forming a first recess in a second surface of the first die, the first recess extending around the first through via; and forming an isolation layer in the first recess, wherein the isolation layer is separated from the encapsulation by the first die. In an embodiment, the first die comprises a second through via, wherein the first recess extends continuously around the first through via and the second through via. In an embodiment, the first die comprises a second through via, further comprising forming a second recess surrounding the second through via, wherein forming the isolation layer comprises forming a first isolation part in the first recess and forming a second isolation part in the second recess, wherein the first isolation part is separated from the second isolation part. In an embodiment, the method further comprises forming a second recess, wherein the second recess does not expose a conductive feature; and forming the isolation layer in the second recess. In an embodiment, the method further comprises forming a buffer layer on the encapsulation, the isolation layer, the plurality of through vias, and the first die; and forming a conductive terminal on the buffer layer, wherein the conductive terminal is electrically connected to the first through via.
Claims (20)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/337,594 US11817426B2 (en) | 2021-01-13 | 2021-06-03 | Package and method of fabricating the same |
DE102021114921.5A DE102021114921A1 (en) | 2021-01-13 | 2021-06-10 | Package and method of making same |
TW110127036A TWI787917B (en) | 2021-01-13 | 2021-07-22 | Semiconductor package and method of fabricating the same |
KR1020210100044A KR102571920B1 (en) | 2021-01-13 | 2021-07-29 | Package and method of fabricating the same |
CN202210031337.3A CN114446900A (en) | 2021-01-13 | 2022-01-12 | Package and method of manufacturing package structure |
US18/362,098 US20240021583A1 (en) | 2021-01-13 | 2023-07-31 | Package and method of fabricating the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163136776P | 2021-01-13 | 2021-01-13 | |
US17/337,594 US11817426B2 (en) | 2021-01-13 | 2021-06-03 | Package and method of fabricating the same |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US18/362,098 Division US20240021583A1 (en) | 2021-01-13 | 2023-07-31 | Package and method of fabricating the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20220223565A1 true US20220223565A1 (en) | 2022-07-14 |
US11817426B2 US11817426B2 (en) | 2023-11-14 |
Family
ID=81367888
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/337,594 Active 2041-09-02 US11817426B2 (en) | 2021-01-13 | 2021-06-03 | Package and method of fabricating the same |
US18/362,098 Pending US20240021583A1 (en) | 2021-01-13 | 2023-07-31 | Package and method of fabricating the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US18/362,098 Pending US20240021583A1 (en) | 2021-01-13 | 2023-07-31 | Package and method of fabricating the same |
Country Status (5)
Country | Link |
---|---|
US (2) | US11817426B2 (en) |
KR (1) | KR102571920B1 (en) |
CN (1) | CN114446900A (en) |
DE (1) | DE102021114921A1 (en) |
TW (1) | TWI787917B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230113020A1 (en) * | 2021-10-13 | 2023-04-13 | Nanya Technology Corporation | Semiconductor device with re-fill layer |
WO2024118450A1 (en) * | 2022-11-28 | 2024-06-06 | Texas Instruments Incorporated | Sensor package with low aspect ratio through silicon via |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190148250A1 (en) * | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metallization patterns in semiconductor packages and methods of forming the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101390877B1 (en) | 2009-07-15 | 2014-04-30 | 한국과학기술원 | Semiconductor chip with low noise through silicon via penetrating guard ring and stack package using the same |
KR101688006B1 (en) | 2010-11-26 | 2016-12-20 | 삼성전자주식회사 | Semiconductor devices |
US8970023B2 (en) | 2013-02-04 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and methods of forming same |
US9666522B2 (en) | 2014-05-29 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark design for packages |
US10522526B2 (en) | 2017-07-28 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | LTHC as charging barrier in InFO package formation |
US10879214B2 (en) | 2017-11-01 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die stack structure and method of fabricating the same |
US10510650B2 (en) * | 2018-02-02 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias |
US10515848B1 (en) * | 2018-08-01 | 2019-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
US10797062B1 (en) | 2019-04-16 | 2020-10-06 | Sandisk Technologies Llc | Bonded die assembly using a face-to-back oxide bonding and methods for making the same |
-
2021
- 2021-06-03 US US17/337,594 patent/US11817426B2/en active Active
- 2021-06-10 DE DE102021114921.5A patent/DE102021114921A1/en active Pending
- 2021-07-22 TW TW110127036A patent/TWI787917B/en active
- 2021-07-29 KR KR1020210100044A patent/KR102571920B1/en active IP Right Grant
-
2022
- 2022-01-12 CN CN202210031337.3A patent/CN114446900A/en active Pending
-
2023
- 2023-07-31 US US18/362,098 patent/US20240021583A1/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20190148250A1 (en) * | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metallization patterns in semiconductor packages and methods of forming the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230113020A1 (en) * | 2021-10-13 | 2023-04-13 | Nanya Technology Corporation | Semiconductor device with re-fill layer |
WO2024118450A1 (en) * | 2022-11-28 | 2024-06-06 | Texas Instruments Incorporated | Sensor package with low aspect ratio through silicon via |
Also Published As
Publication number | Publication date |
---|---|
TW202230541A (en) | 2022-08-01 |
TWI787917B (en) | 2022-12-21 |
US11817426B2 (en) | 2023-11-14 |
KR20220102547A (en) | 2022-07-20 |
CN114446900A (en) | 2022-05-06 |
KR102571920B1 (en) | 2023-08-28 |
DE102021114921A1 (en) | 2022-07-14 |
US20240021583A1 (en) | 2024-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11342309B2 (en) | Semiconductor packages and methods of forming same | |
US11581281B2 (en) | Packaged semiconductor device and method of forming thereof | |
US11664322B2 (en) | Multi-stacked package-on-package structures | |
US11189603B2 (en) | Semiconductor packages and methods of forming same | |
TWI642157B (en) | Semiconductor package and method of forming the same | |
US11984372B2 (en) | Integrated circuit package and method | |
US11296065B2 (en) | Semiconductor packages and methods of forming same | |
US11270975B2 (en) | Semiconductor packages including passive devices and methods of forming same | |
US20240021583A1 (en) | Package and method of fabricating the same | |
TWI724653B (en) | Semiconductor device and method of forming the same | |
US20220367446A1 (en) | Package structures | |
US11955433B2 (en) | Package-on-package device | |
US20240038741A1 (en) | Package structure and method of forming thereof | |
TW202209589A (en) | Semiconductor die package and method of manufacture | |
US20230378012A1 (en) | Integrated Circuit Packages and Methods of Forming the Same | |
TW202038396A (en) | Integrated circuit package and method of manufacturing the same | |
TWI838073B (en) | Integrated circuit packages and methods of forming the same | |
US20240234400A1 (en) | Integrated circuit packages and methods of forming the same | |
US20240128218A1 (en) | Semiconductor package and manufacturing method thereof | |
CN116741730A (en) | Semiconductor device and method of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, HSIEN-WEI;CHEN, MING-FA;REEL/FRAME:056426/0386 Effective date: 20210602 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |