TWI727383B - 半導體結構、三維積體電路結構及其製作方法 - Google Patents

半導體結構、三維積體電路結構及其製作方法 Download PDF

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TWI727383B
TWI727383B TW108127379A TW108127379A TWI727383B TW I727383 B TWI727383 B TW I727383B TW 108127379 A TW108127379 A TW 108127379A TW 108127379 A TW108127379 A TW 108127379A TW I727383 B TWI727383 B TW I727383B
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Taiwan
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bonding
pad
layer
dielectric
die
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TW108127379A
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TW202044530A (zh
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陳憲偉
陳潔
陳明發
葉松峯
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台灣積體電路製造股份有限公司
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

一種三維積體電路（3DIC）結構，所述三維積體電路結構包括藉由混合接合結構而接合在一起的第一晶粒與第二晶粒。所述第一晶粒及所述第二晶粒中的一者具有焊墊以及設置在所述焊墊之上的頂蓋層。所述頂蓋層暴露出所述焊墊的頂表面的一部分，且所述焊墊的所述頂表面的所述一部分具有探針標記。所述混合接合結構的接合金屬層穿透所述頂蓋層以電連接到所述焊墊。還提供一種製作三維積體電路結構的所述第一晶粒或所述第二晶粒的方法。

Description

半導體結構、三維積體電路結構及其製作方法
本發明實施例是有關於一種半導體結構、三維積體電路結構及其製作方法。
近年來，由於各種電子元件(例如，電晶體、二極體、電阻器、電容器等)的積集密度持續提高，半導體工業已經歷快速成長。積集密度的這種提高大多歸因於最小特徵尺寸(minimum feature size)的一再減小，這使得更多元件能夠整合在一定的面積中。
與先前的封裝體相比，這些較小的電子元件也需要利用較小面積的較小的封裝體。半導體封裝體的一些類型包括四面扁平封裝(quad flat package，QFP)、針格陣列(pin grid array，PGA)、球格陣列(ball grid array，BGA)、覆晶技術(flip chip，FC)、三維積體電路(three dimensional integrated circuit，3DIC)、晶圓級封裝體(wafer level package，WLP)及疊層封裝體(package on package，PoP)裝置。一些3DIC是藉由在半導體晶圓級的晶片之 上放置晶片製備而成。由於堆疊晶片之間的內連線的長度減小，因此3DIC提供更高的積集密度及其他優點，例如較快的速度及較高的頻寬。然而，對於3DIC技術而言，存在許多要應對的挑戰。
本發明實施例提供一種半導體結構包括基底、內連結構、導電焊墊、介電頂蓋以及接合結構。內連結構設置在基底之上。導電焊墊設置在內連結構之上並電連接到內連結構。介電頂蓋設置在導電焊墊之上並暴露出導電焊墊的頂表面的一部分。導電焊墊的頂表面的一部分具有探針標記。接合結構設置在介電頂蓋之上。接合結構包括接合金屬層，接合金屬層穿透介電頂蓋以電連接到導電焊墊。
本發明實施例提供一種三維積體電路(3DIC)結構包括接合在一起的第一晶粒與第二晶粒。第一晶粒及第二晶粒中的一者具有導電焊墊及設置在導電焊墊之上的介電頂蓋。介電頂蓋暴露出導電焊墊的頂表面的一部分，且導電焊墊的頂表面的一部分具有探針標記。
本發明實施例提供一種製作半導體結構的方法包括以下步驟。在基底之上形成內連結構。在內連結構之上形成導電焊墊以及在導電焊墊之上形成介電頂蓋。對介電頂蓋進行圖案化以暴露出導電焊墊的頂表面的一部分。執行電路探針(CP)測試，以使導電焊墊的頂表面的一部分具有探針標記。在介電頂蓋之上形 成接合結構。接合結構包括接合金屬層，接合金屬層穿透介電頂蓋以電連接到導電焊墊。
10、20、30:3DIC結構
35:混合接合結構
100、100’:第一半導體結構
101、101’、501:第一晶粒
101a:第一晶粒的正面
102:第一半導體基底
103:第一元件層
104:第一內連結構
106:第一絕緣材料
108:第一金屬特徵
108a、108b:頂部金屬特徵
110:第一鈍化層
110a、110b、210a、210b:鈍化材料
111、141、241:插塞
111a、241a:第一插塞
111b、241b:第二插塞
112:導電材料
114:頂蓋材料
116、126:罩幕圖案
122、142、222、242:焊墊
122a、222a:第一焊墊
122b、222b:第二焊墊
122t1、122t2:頂部部分
123、223:殘留物
124、144、224、244、544:頂蓋層
124a、124c、224c:第一頂蓋層
124b、224b:第二頂蓋層
125、125a、145、545:開口
127、227:探針標記
128:探針
130:第一接合介電層
130a、130c、230a、230c:接合介電材料
130b:第一阻擋層
132:第一接合金屬層
133:通孔開孔
134、234:通孔插塞
135:第一接合結構
136、236:金屬特徵
137、139:溝渠
138:第一虛設金屬特徵
200、200’:第二半導體結構
201、201’:第二晶粒
201a:第二晶粒的正面
202:第二半導體基底
203:第二元件區
204:第二內連結構
206:第二絕緣材料
208:第二金屬特徵
208a、208b:頂部金屬特徵
210:第二鈍化層
230:第二接合介電層
230b:第二阻擋層
232:第二接合金屬層
235:第二接合結構
238:第二虛設金屬特徵
500:半導體結構
AM:對齊標記
CP:連接焊墊
P1:第一部分
P2:第二部分
P3:第三部分
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A到圖1G是根據第一實施例的形成三維積體電路(3DIC)結構的方法的剖視圖。
圖2A及圖2B是分別示出圖1D及圖1F所示結構的俯視圖。
圖3A到圖3C是根據第二實施例的形成3DIC結構的方法的剖視圖。
圖3D是根據第三實施例的3DIC結構的剖視圖。
圖4是示出圖3A所示結構的俯視圖。
圖5A到圖5B是根據第四實施例的形成半導體結構的方法的剖視圖。
圖6是示出圖5A所示結構的俯視圖。
以下揭露內容提供用於實施所提供的目標的不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是 為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，且也可包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件符號及/或字母。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
此外，為易於說明，本文中可能使用例如「在...下方(beneath)」、「在...下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對術語來闡述圖中所示的一個元件或特徵與另一(些)元件或特徵的關係。所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向(旋轉90度或在其他定向)，而本文所用的空間相對術語相應地作出解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明進行三維(3D)封裝體或三維積體電路裝置的驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試墊，所述測試墊使得能夠測試3D封裝體或3DIC、使用探針(probe)及/或探針卡(probe card)等。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可接合包括對已知良好晶粒(known good dies)的中間驗證的測試方法一起使用，以提高 良率(yield)及降低成本。
圖1A到圖1G是根據第一實施例的形成三維積體電路(3DIC)結構的方法的剖視圖。圖2A及圖2B是示出圖1D所示結構的俯視圖。
參照圖1A，形成3DIC結構10(如圖1G所示)的方法包括以下步驟。首先，提供圖1A所示初始結構。所述初始結構包括第一半導體基底102、第一元件層103、第一內連結構104、第一鈍化層110、導電材料112及頂蓋材料114。
在一些實施例中，第一半導體基底102可包含矽或其他半導體材料。作為另外一種選擇，或另外地，第一半導體基底102可包含其他元素半導體材料，例如鍺。在一些實施例中，第一半導體基底102是由化合物半導體(例如碳化矽、砷化鎵、砷化銦或磷化銦)製成的。在一些實施例中，第一半導體基底102是由合金半導體(例如矽鍺、碳化矽鍺、磷化鎵砷或磷化鎵銦)製成的。在一些實施例中，第一半導體基底102包括外延層。舉例來說，第一半導體基底102具有上覆在塊狀半導體上的外延層。
在一些實施例中，第一元件層103以前段(front-end-of-line，FEOL)製程形成在第一半導體基底102之上。第一元件層103包括各種各樣的元件。在一些實施例中，元件包括有源元件、無源元件或其組合。在一些實施例中，元件可包括積體電路元件。舉例來說，元件為電晶體、電容器、電阻器、二極體、光電二極體、熔絲元件(fuse device)或其他相似的元件。 在一些實施例中，第一元件層103包括柵極結構、源極及漏極區以及隔離結構(例如，淺溝渠隔離(shallow trench isolation，STI)結構(圖中未示出))。在第一元件層103中，可形成各種N型金屬氧化物半導體(N-type metal-oxide semiconductor，NMOS)元件和/或P型金屬氧化物半導體(P-type metal-oxide semiconductor，PMOS)元件(例如電晶體或記憶體等)，且可將所述元件內連在一起以執行一種或多種功能。在第一半導體基底102之上還可形成其他元件，例如電容器、電阻器、二極體、光電二極體、熔絲等。所述元件的功能可包括記憶體、處理器、感測器、放大器、功率分配(power distribution)、輸入和/或輸出電路系統等。
參照圖1A，第一內連結構104形成在第一元件層103之上。詳細來說，第一內連結構104包括第一絕緣材料106及多個第一金屬特徵108。第一金屬特徵108形成在第一絕緣材料106中且電連接到第一元件層103。第一金屬特徵108的一部分(例如頂部金屬特徵108a及108b)被第一絕緣材料106暴露出。在一些實施例中，第一絕緣材料106包括位於第一元件層103上的層間介電(inner-layer dielectric，ILD)層、以及位於ILD層之上的至少一個金屬間介電(inter-metal dielectric，IMD)層。在一些實施例中，第一絕緣材料106包括氧化矽、氮化矽、氮氧化矽、原矽酸四乙酯(tetraethylorthosilicate，TEOS)氧化物、未經摻雜的矽酸鹽玻璃或經摻雜的矽氧化物(例如，硼磷矽酸鹽玻璃 (borophosphosilicate glass，BPSG)、熔融矽石玻璃(fused silica glass，FSG)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、摻雜有硼的矽玻璃(boron doped silicon glass，BSG))、低介電常數介電材料、其他合適的介電材料或其組合。示例性低介電常數介電材料包括FSG、摻雜有碳的矽氧化物、Black Diamond®(加利福尼亞州聖克拉拉的應用材料公司)、乾凝膠(Xerogel)、氣凝膠(Aerogel)、非晶氟化碳、聚對二甲苯、雙苯並環丁烯(bis-benzocyclobutenes，BCB)、SiLK(密西根州米德蘭的陶氏化學)、聚醯亞胺、其他低介電常數介電材料或其組合。在一些替代實施例中，第一絕緣材料106可為單個層或多個層。在一些實施例中，第一金屬特徵108包括插塞(plugs)及金屬線。插塞可包括形成在ILD層中的接觸件(contacts)以及形成在IMD層中的通孔(vias)。接觸件形成在第一元件層103與底部金屬線之間，且連接第一元件層103及底部金屬線。通孔形成在兩條金屬線之間，且連接所述兩條金屬線。第一金屬特徵108可由鎢(W)、銅(Cu)、銅合金、鋁(Al)、鋁合金或其組合製成。在一些替代實施例中，可在第一金屬特徵108與第一絕緣材料106之間形成障壁層(圖中未示出)以防止第一金屬特徵108的材料遷移到或擴散到第一元件層103。舉例來說，障壁層的材料包括鉭、氮化鉭、鈦、氮化鈦、鈷鎢(cobalt-tungsten，CoW)或其組合。
參照圖1A，第一鈍化層110形成在第一內連結構104之上。在一些實施例中，第一鈍化層110包括氧化矽、氮化矽、苯 並環丁烯(benzocyclobutene，BCB)聚合物、聚醯亞胺(polyimide，PI)、聚苯並惡唑(polybenzoxazole，PBO)或其組合且藉由例如旋轉塗布、化學氣相沉積(chemical vapor deposition，CVD)等合適的製程形成。在實施例中，第一鈍化層110可為單層結構、雙層結構或多層結構。如圖1A所示，第一鈍化層110包括鈍化材料110a以及形成在鈍化材料110a之上的鈍化材料110b。鈍化材料110a與鈍化材料110b具有不同的材料。舉例來說，鈍化材料110a可包含氮化矽，而鈍化材料110b可包含聚醯亞胺(PI)或與氮化矽不同的任何材料。
參照圖1A，導電材料112形成在第一鈍化層110之上並藉由穿透過第一鈍化層110的插塞111電連接到頂部金屬特徵108a及108b。導電材料112與第一金屬特徵108可具有不同的材料。在一些實施例中，導電材料112比第一金屬特徵108軟。導電材料112與插塞111可具有相同的材料。在一些實施例中，導電材料112及插塞111分別包含金屬材料(例如鋁、銅、鎳、金、銀、鎢或其組合)，導電材料112及插塞111可藉由以下步驟形成：圖案化第一鈍化層110形成多個開口以達第一金屬特徵108；藉由合適的製程(例如電化學鍍敷製程、CVD、原子層沉積(atomic layer deposition，ALD)、PVD等)沉積金屬材料層以填充在開口中並覆蓋第一鈍化層110；接著圖案化金屬材料層。
參照圖1A，頂蓋材料114形成在導電材料112之上。舉例來說，頂蓋材料114可為介電材料。在一些實施例中，頂蓋材 料114包含含氮材料(例如氮氧化矽、氮化矽或其組合)且具有50nm到100nm的厚度。在另一實施例中，頂蓋材料114被稱為抗反射塗布(anti-reflective coating，ARC)層，頂蓋材料114可包含有機ARC材料(例如，聚合物樹脂)、無機ARC材料(例如，SiON)或其組合。在一些替代實施例中，頂蓋材料114可為單層或多層，且可藉由合適的製程(例如CVD、ALD等)形成。
參照圖1B，在頂蓋材料114之上形成罩幕圖案116。在一些實施例中，罩幕圖案116可對應於頂部金屬特徵108a及108b，以便後續形成焊墊122(如圖1C所示)。在一實施例中，罩幕圖案116包括光阻且藉由合適的製程(例如旋轉塗布及微影製程)形成。
參照圖1B及圖1C，在形成罩幕圖案116之後，使用罩幕圖案116作為蝕刻罩幕來執行第一蝕刻製程以移除部分頂蓋材料114及部分導電材料112，從而暴露出鈍化材料110b。在一些實施例中，第一蝕刻製程可包括乾式蝕刻製程、濕式蝕刻製程或其組合。在這種情形中，如圖1C所示，形成了多個焊墊122(也被稱為導電焊墊)及分別設置在焊墊122之上的多個頂蓋層124(也被稱為介電焊墊)。在本實施例中，焊墊122包括彼此隔開的第一焊墊122a與第二焊墊122b。第一焊墊122a藉由第一插塞111a電連接到頂部金屬特徵108a。在一些實施例中，第一焊墊122a可與頂部金屬特徵108a對齊或部分交疊。第二焊墊122b藉由第二插塞111b電連接到頂部金屬特徵108b。在一些實施例中，第二焊 墊122b可與頂部金屬特徵108b對齊或部分交疊。第一頂蓋層124a設置在第一焊墊122a之上，且第二頂蓋層124b設置在第二焊墊122b之上。儘管在圖1C中僅示出兩個焊墊122及兩個頂蓋層124，然而本公開的實施例並非僅限於此。在其他實施例中，焊墊122及頂蓋層124的數量可依需求來調整。在形成焊墊122及頂蓋層124之後，移除罩幕圖案116。
參照圖1C及圖1D，在焊墊122之上形成罩幕圖案126。罩幕圖案126覆蓋鈍化材料110b、第二頂蓋層124b及第二焊墊122b，並具有暴露出第一頂蓋層124a的一部分的開口125。開口125的形狀可為規則形狀或不規則形狀。開口125的形狀為例如正方形、矩形、圓形、橢圓形等，但並非僅限於此。在一實施例中，罩幕圖案126包括光阻，且藉由合適的製程(例如旋轉塗布及微影製程)形成。
在形成罩幕圖案126之後，使用罩幕圖案126作為蝕刻罩幕來執行第二蝕刻製程以移除第一頂蓋層124a的所述一部分，從而暴露出第一焊墊122a。在一實施例中，第二蝕刻製程可包括各向同性蝕刻製程。在另一實施例中，第二蝕刻製程可包括濕式蝕刻製程或濕式蝕刻製程與乾式蝕刻製程的組合。可使用包含鹵素(例如F、Cl、Br或其組合)的蝕刻溶液來執行濕式蝕刻製程。舉例來說，蝕刻溶液可包括HF溶液、HCl溶液、HBr溶液或其組合。乾式蝕刻製程可使用包含鹵素(例如F、Cl、Br或其組合)的蝕刻氣體來執行。在這種情形中，如圖1D所示，被第一頂蓋層 124c的剩餘部分(在下文中，被稱為第一頂蓋層124c)暴露出的第一焊墊122a的頂表面或頂部部分122t1可被(例如，化學地)改性或損壞，以使第一焊墊122a的頂部部分122t1的電阻值小於第一焊墊122a的其他部分的電阻值。
在替代實施例中，在第一焊墊122a中或第一焊墊122a上可形成一些殘留物123。在本文中，殘留物123可為第二蝕刻製程期間的化學殘留物。因此，殘留物123可來自第一頂蓋層124a及第一焊墊122a，殘留物123可具有含氮材料(例如氮氧化矽、氮化矽或其組合)以及金屬材料(例如鋁、銅、鎳、金、銀、鎢或其組合)。在一些替代實施例中，具有殘留物123的一焊墊122a的電阻值大於第二焊墊122b的電阻值。在本實施例中，殘留物123可毯覆地或連續地覆蓋第一焊墊122a。另外，殘留物123可部分地或非連續地覆蓋第一焊墊122a。在其他實施例中，在第一焊墊122a的頂表面或頂部部分122t1上可發生電荷累積，這可能會影響第一焊墊122a的頂部部分122t1的電阻值。
如圖1D以及圖2A的俯視圖所示，第一頂蓋層124c及第二頂蓋層124b被配置成具有不同的形狀。在一些實施例中，第一頂蓋層124c被配置成環形結構以環繞部分第一焊墊122a或殘留物123，而第二頂蓋層124b被配置成覆蓋第二焊墊122b的區塊結構。所述環可為圓形環、矩形環、橢圓形環，且所述環可具有均勻的寬度。然而，在一些實施例中，由於罩幕圖案126在微影製程期間未對齊，所述環可具有不同的寬度或變成具有間隙的環。 在一些實施例中，未被第一頂蓋層124c覆蓋的第一焊墊122a上或第一焊墊122a中具有殘留物123，而第二焊墊122b不具有殘留物123。在這種情形中，在一實施例中，第二焊墊122b的頂部部分122t2具有比第一焊墊122a的頂部部分122t1低的電阻。此外，罩幕圖案126的開口125延伸到第一頂蓋層124c中，以使第一頂蓋層124c具有開口125a，如圖1D所示。在這種情形中，被第一頂蓋層124c的開口125a暴露出的第一焊墊122a的形狀可具有不規則形狀或規則形狀，例如，正方形形狀、矩形形狀、圓形形狀、橢圓形形狀等，但並非僅限於此。
參照圖1D及圖1E，在移除罩幕圖案126之後，對第一焊墊122a執行電路探針(circuit probing，CP)測試。具體來說，可使用探針128電耦合到第一焊墊122a以進行晶圓或晶粒測試，從而檢查晶粒是否是良好晶粒。在一些實施例中，CP測試也被稱為晶圓接受度測試(wafer acceptance testing，WAT)。在一些實施例中，使用第一焊墊122a進行電測試以檢查圖1E所示第一晶粒101是否是良好晶粒，但是本公開並非僅限於此。可選擇第一晶粒101來測試晶圓或晶粒的不同屬性，例如漏電流、擊穿電壓、閾值電壓及有效溝道長度、飽和電流、接觸電阻及連接。應注意，當第一晶粒101被識別為已知良好晶粒(known good die，KGD)時，選擇第一晶粒101來進行以下製程。在這種情形中，如圖1E所示，在第一焊墊122a的頂部部分122t1處形成探針標記127，且探針標記127可為凹進或凹陷到第一焊墊122a中的凹槽。由於探針128 可在CP測試期間按壓或擠壓殘留物123以電連接到第一焊墊122a，因此在CP測試之後，探針標記127之下的殘留物123可被擠壓到探針標記127的兩側，如圖1E所示。也就是說，探針標記127之下的頂部部分122t1可具有比探針標記127旁邊的頂部部分122t1低的電阻。
參照圖1E到圖1F，在第一晶粒101的正面101a之上形成第一接合結構135。在本文中，所謂的正面101a是指第一鈍化層110的頂表面。詳細來說，如圖1F所示，在第一晶粒101被識別為已知良好晶粒之後，在第一晶粒101的正面101a之上設置接合介電材料130a(或被稱為第一接合介電材料。在一些實施例中，如圖1F所示，接合介電材料130a覆蓋第一焊墊122a、殘留物123、第一頂蓋層124c、第二焊墊122b、第二頂蓋層124b及鈍化材料110b。在一些實施例中，接合介電材料130a包含氧化矽、氮化矽、聚合物或其組合。接合介電材料130a藉由合適的製程(例如旋轉塗布、CVD等)形成。
在圖1F中，接著形成第一阻擋層130b以覆蓋接合介電材料130a。在一些實施例中，第一阻擋層130b包含介電材料(例如，氧化矽、氮化矽、氮氧化矽或其組合)且藉由合適的製程(例如CVD、ALD等)形成。在一些實施例中，第一阻擋層130b的厚度為50nm到100nm。
在圖1F中，在第一阻擋層130b之上形成另一種接合介電材料130c(或被稱為第二接合介電材料)。也就是說，第一阻擋 層130b設置在接合介電材料130a與接合介電材料130c之間。在一些實施例中，第一阻擋層130b的材料不同於接合介電材料130a及130c的材料。舉例來說，第一阻擋層130b可包含氮化矽，而接合介電材料130a及130c可包含氧化矽。然而，本公開的實施例並非僅限於此。在其他實施例中，接合介電材料130a及130c與第一阻擋層130b具有不同的材料。在一些實施例中，接合介電材料130c包含氧化矽、氮化矽、聚合物或其組合。接合介電材料130c藉由合適的製程(例如旋轉塗布，CVD等)形成。此後，可對接合介電材料130c執行平坦化製程，以使得在一些實施例中接合介電材料130c的頂表面具有平坦表面。在替代實施例中，平坦化製程包括化學機械研磨(chemical mechanical polish，CMP)製程、回蝕製程或其組合。
在形成包括接合介電材料130a及130c以及位於接合介電材料130a與接合介電材料130c之間的第一阻擋層130b的第一接合介電層130之後，在第一接合介電層130中形成第一接合金屬層132且可選擇性地在第一接合介電層130中形成第一虛設金屬特徵138，從而完成第一半導體結構100，如圖1F所示。在一些實施例中，第一半導體結構100可包括半導體晶粒、半導體晶片、半導體晶圓或其組合。在本實施例中，第一半導體結構100包括第一晶粒101以及位於第一晶粒101的正面101a之上的第一接合結構135。舉例來說，第一晶粒101可為應用專用積體電路(application-specific integrated circuit，ASIC)晶片、類比晶片、 感測器晶片、無線與射頻晶片、電壓調節器晶片或記憶體晶片。
在圖1F中，第一接合金屬層132對應於第二焊墊122b並電連接到第二焊墊122b。在一些實施例中，第一接合金屬層132包括通孔插塞134及金屬特徵136。舉例來說，金屬特徵136是面積比通孔插塞134大的通孔插塞。如圖1F所示，通孔插塞134穿透過接合介電材料130a及第二頂蓋層124b以接觸第二焊墊122b。金屬特徵136穿透過接合介電材料130c及第一阻擋層130b以連接到通孔插塞134。換句話說，金屬特徵136藉由通孔插塞134電連接到第二焊墊122b。第一接合金屬層132藉由第二焊墊122b電連接到頂部金屬特徵108b。在一些實施例中，第一接合金屬層132藉由雙重金屬鑲嵌(dual damascene)方法形成。
另一方面，第一虛設金屬特徵138可選擇性地形成在第一接合金屬層132旁邊且對應於第一焊墊122a。第一虛設金屬特徵138設置在接合介電材料130c及第一阻擋層130b中，且被接合介電材料130c暴露出。在本文中，當將元件闡述為“虛設的”時，所述元件是電浮置或與其他元件電隔離。舉例來說，如圖1F所示，第一虛設金屬特徵138是電浮置。在一些實施例中，第一虛設金屬特徵138是藉由單金屬鑲嵌(single damascene)方法形成。
在一些實施例中，第一虛設金屬特徵138與金屬特徵136(或第一接合金屬層132)處於實質上相同的水平高度處。也就是說，第一虛設金屬特徵138的頂部與金屬特徵136(或第一接合金屬層132)的頂部與接合介電材料130c的頂表面實質上共面。
在一些實施例中，第一虛設金屬特徵120可包含銅、銅合金、鎳、鋁、鎢、其組合。第一接合金屬層132可包含銅、銅合金、鎳、鋁、鎢或其組合。在一些實施例中，第一虛設金屬特徵138的材料與第一接合金屬層132的材料可為相同的。在一些替代實施例中，第一虛設金屬特徵138的材料可不同於第一接合金屬層132的材料。
在一些實施例中，第一虛設金屬特徵138與金屬特徵136同時形成。在一些其他實施例中，第一虛設金屬特徵138與金屬特徵136相繼形成。第一虛設金屬特徵138及第一接合金屬層132是藉由溝渠優先製程(trench first process)、通孔口優先製程(via hole first process)或自對齊製程(self-aligned process)形成。
在一些實施例中，第一虛設金屬特徵138及第一接合金屬層132按照以下步驟(被稱為溝渠優先製程)形成。藉由微影製程及蝕刻製程對接合介電材料130c及阻擋層130b進行圖案化以在接合介電材料130c及阻擋層130b中形成溝渠137及139。溝渠139對應於第一焊墊122a且溝渠137對應於第二焊墊122b。在蝕刻製程期間，第一阻擋層130b用作蝕刻停止層，且因此第一阻擋層130b被溝渠137及139暴露出或穿透。接下來，藉由另一微影製程及蝕刻製程對部分接合介電材料130a及部分第二頂蓋層124b進行圖案化，以形成通孔開孔133於其中。在一實施例中，蝕刻製程可包括各向異性蝕刻製程。在另一實施例中，蝕刻製程可包括乾式蝕刻製程。可使用蝕刻氣體(包括O2、N2、CH4或其 組合)來執行乾式蝕刻製程。在這種情形中，乾式蝕刻製程能夠防止第二焊墊122b的頂表面或頂部部分122t2發生化學改性或損壞。通孔開孔133可暴露出第二焊墊122b。此後，在接合介電層130c上形成導電材料層及阻擋材料層(未示出)，且導電材料層及阻擋材料層填充到溝渠137及139以及通孔開孔133中。接著藉由平坦化製程(例如CMP製程)移除接合介電材料130c上的導電材料層，從而在溝渠139中形成第一虛設金屬特徵138，且分別在通孔開孔133及溝渠137中形成通孔插塞134及金屬特徵136。在一些替代實施例中，溝渠137及139中的一者可被視為比通孔開孔133大的通孔開孔。
在一些其他實施例中，第一虛設金屬特徵138及第一接合金屬層132按照以下步驟(被稱為通孔開孔優先製程)形成。藉由微影製程及蝕刻製程，對接合介電材料130a及130c、第一阻擋層130b及第二頂蓋層124b進行圖案化以形成通孔開孔133。在一實施例中，蝕刻製程可包括各向異性蝕刻製程。在另一實施例中，蝕刻製程可包括乾式蝕刻製程。可使用蝕刻氣體(包括O2、N2、CH4或其組合)來執行乾式蝕刻製程。接下來，藉由微影製程及蝕刻製程對接合介電材料130c及第一阻擋層130b進行圖案化以在接合介電材料130c及第一阻擋層130b中形成溝渠137及139。在蝕刻製程期間，第一阻擋層130b用作蝕刻終止層，且因此第一阻擋層130b被溝渠137及139暴露出或穿透。此後，形成導電材料層且執行平坦化製程。
在替代實施例中，第一虛設金屬特徵138及第一接合金屬層132按照以下步驟(被稱為自對齊製程)形成。在形成接合介電材料130a之後，形成第一阻擋層130b且藉由微影製程及蝕刻製程對第一阻擋層130b進行圖案化以在第一阻擋層130b中形成通孔開孔圖案。接下來，利用通孔開孔圖案在第一阻擋層130b之上形成接合介電材料130c。接合介電材料130c填充到第一阻擋層130b的通孔開孔圖案中且接觸接合介電材料130a。此後，藉由微影製程在接合介電材料130c上形成具有溝渠圖案的圖案化罩幕，溝渠圖案中的一些溝渠圖案對應於第一阻擋層130b的通孔開孔圖案。之後，使用第一阻擋層130b作為蝕刻終止層來對接合介電材料130c執行蝕刻製程，以使得形成溝渠137及139。在一實施例中，蝕刻製程可包括各向異性蝕刻製程。在另一實施例中，蝕刻製程可包括乾式蝕刻製程。可使用蝕刻氣體(包括O2、N2、CH4或其組合)來執行乾式蝕刻製程。同時，使用具有通孔開孔圖案的第一阻擋層130b作為硬罩幕對接合介電材料130a進行蝕刻，以使得通孔開孔133形成在接合介電材料130a中且與溝渠137自對齊。此後，形成導電材料層且執行平坦化製程。
在圖1F中，第一阻擋層130b具有與接合介電材料130c相同的圖案且第一阻擋層130b與接合介電材料130c二者均具有溝渠137及139。然而，根據製程而定，第一阻擋層130b可具有與接合介電材料130a相同的圖案且第一阻擋層130b與接合介電材料130a二者均具有如虛線所示的通孔開孔133。換句話說，第 二焊墊122b之上的溝渠137的底部暴露出部分第一阻擋層130b，且溝渠137的底部下方的第一阻擋層130b具有通孔開孔133的圖案。第一焊墊122a之上的溝渠139的底部暴露出部分第一阻擋層130b，且溝渠139的底部下方的第一阻擋層130b不具有通孔圖案。
如圖1F所示，第一焊墊122a藉由接合介電材料130a與第一接合金屬層132及虛設金屬特徵120電隔離。在一實施例中，第一焊墊122a可被視為測試焊墊。另外，第二焊墊122b電連接到第一接合金屬層132。在另一實施例中，第二焊墊122b可被視為連接焊墊，所述連接焊墊將信號從第一晶粒101傳輸到上覆的第二晶粒201(如圖1G所示)。應注意，在一些實施例中，第二頂蓋層124b能夠保護第二焊墊122b在前述蝕刻製程期間不形成殘留物，從而維持第二焊墊122b與第一接合金屬層132之間的接觸電阻。在這種情形中，分佈在整個第一半導體結構100(或整個半導體晶圓)中的第二焊墊122b與第一接合金屬層132之間的接觸電阻具有更好的均勻性，從而提高第一半導體結構100(或圖1G所示待形成的3DIC結構10)的良率。在一些替代實施例中，第二焊墊122b藉由接合介電材料130a與虛設金屬特徵120電隔離。
如圖1F及圖2B所示，在形成通孔開孔133之後，在圖2B中示出第一頂蓋層124c及第二頂蓋層124b的俯視圖。第一頂蓋層124c及第二頂蓋層124b被配置成具有環形形狀。在一些實施例中，第一頂蓋層124c被配置成一個環結構以環繞部分第一焊 墊122a或殘留物123，而第二頂蓋層124b被配置成另一環結構以環繞部分第二焊墊122b。在一些實施例中，第一焊墊122a上具有殘留物123，而第二焊墊122b上不具有殘留物。因此，通孔插塞134可接觸不具有殘留物123的第二焊墊122b。在一些實施例中，被第一頂蓋層124c暴露出的殘留物123的面積大於被第二頂蓋層124b暴露出的第二焊墊122b的面積。
參照圖1G，提供第二半導體結構200。詳細來說，第二半導體結構200包括第二晶粒201及設置在第二晶粒201的正面201a之上的第二接合結構235。在一些實施例中，第二半導體結構200可包括半導體晶粒、半導體晶片、半導體晶圓或其組合。舉例來說，第二晶粒201可為應用專用積體電路(ASIC)晶片、類比晶片、感測器晶片、無線與射頻晶片、電壓調節器晶片或記憶體晶片。第二晶粒201與第一晶粒101可為相同類型的晶粒或不同類型的晶粒。
在一些實施例中，第二晶粒201相似於第一晶粒101。也就是說，第二晶粒201包括第二半導體基底202、第二元件區203、第二內連結構204(包括第二絕緣材料206及多個第二金屬特徵208)、第二鈍化層210(包括鈍化材料210a及210b)、焊墊222及頂蓋層224。第二晶粒201的配置、材料及形成方法與第一晶粒101的配置、材料及形成方法相似。因此，此處將省略其細節。圖1G所示第一晶粒101與第二晶粒201具有相同的尺寸。本文中的用語“尺寸”是指長度、寬度或面積。舉例來說，如圖1G所示，第 二晶粒201的長度等於第一晶粒101的長度。然而，本公開的實施例並非僅限於此。在其他實施例中，第一晶粒101的尺寸可不同於第二晶粒201的尺寸。舉例來說，第一晶粒101可為晶圓，第二晶粒201可為晶粒且作為晶圓上晶片(chip-on-wafer，CoW)結構設置在晶圓之上。
在一些實施例中，第二接合結構235包括第二接合介電層230、第二接合金屬層232及第二虛設金屬特徵238。第二虛設金屬特徵238對應於第一焊墊222a，而第二接合金屬層232對應於第二焊墊222b。第一頂蓋層224c可被配置成環形結構以環繞部分第一焊墊222a或殘留物223，而第二頂蓋層224b可被配置成覆蓋第二焊墊222b的區塊結構。部分第一焊墊222a具有探針標記227，探針標記227凹進或凹陷到第一焊墊222a的頂表面中。第二接合介電層230包括接合介電材料230a及230c以及位於接合介電材料230a與接合介電材料230c之間的第二阻擋層230b。第二接合金屬層232包括通孔插塞234及金屬特徵236，其中通孔插塞234設置在金屬特徵236與第二焊墊222b之間。
參照圖1G，將第二半導體結構200進一步上下翻轉並安裝到第一半導體結構100上。也就是說，第一晶粒101與第二晶粒201藉由第一接合結構135及第二接合結構235面對面地接合在一起以形成3DIC結構10(或被稱為晶粒堆疊結構10)。然而，本公開的實施例並非僅限於此。在其他實施例中，第一晶粒101與第二晶粒201可面對背地接合在一起。
在一些實施例中，在將第一晶粒101接合到第二晶粒201之前，將第一接合結構135與第二接合結構235對齊，以使第一虛設金屬特徵138可接合到第二虛設金屬特徵238、第一接合金屬層132可接合到第二接合金屬層232且第一接合介電層130可接合到第二接合介電層230。在一些實施例中，第一接合結構135與第二接合結構235的對齊可使用光學感測方法實現。在實現對齊之後，藉由混合接合將第一接合結構135與第二接合結構235接合在一起以形成混合接合結構35。
第一接合結構135與第二接合結構235藉由施加壓力及熱而混合接合在一起。應注意，混合接合涉及至少兩種類型的接合，所述至少兩種類型的接合包括金屬對金屬接合以及非金屬對非金屬接合(例如，介電質對介電質接合或熔融接合)。如圖1G所示，混合接合結構35包括藉由金屬對金屬接合而接合在一起的第一虛設金屬特徵138與第二虛設金屬特徵238、藉由金屬對金屬接合而接合在一起的第一接合金屬層132與第二接合金屬層232、以及藉由非金屬對非金屬接合而接合在一起的第一接合介電層130與第二接合介電層230。然而，本公開的實施例並非僅限於此。在其他實施例中，第一接合結構135與第二接合結構235可藉由其他接合(例如熔融接合)接合在一起。
另一方面，混合接合結構35包括第一部分P1、第二部分P2及第三部分P3。如圖1G所示，第一部分P1包括接合在一起的第一接合金屬層132與第二接合金屬層232；第二部分P2包括接 合在一起的第一接合介電層130與第二接合介電層230；且第三部分P3包括接合在一起的第一虛設金屬特徵138與第二虛設金屬特徵238。
圖3A到圖3C是根據第二實施例的形成3DIC結構的方法的剖視圖。圖4是示出圖3A所示結構的俯視圖。
參照圖3A，結構101’是藉由圖1A所示結構而形成的。在形成圖1A所示結構之後，對導電材料112及頂蓋材料114進行圖案化以形成焊墊142及焊墊142之上的頂蓋層144。如圖3A及圖4的俯視圖所示，焊墊142可被配置成沿著從頂部金屬特徵108a到頂部金屬特徵108b的方向延伸的區塊結構。從另一個角度來看，在一些實施例中，焊墊142被視為如圖1C所示的彼此連接的第一焊墊122a與第二焊墊122b。接著對頂蓋層144進行圖案化以形成暴露出部分焊墊142的開口145。在對頂蓋層144進行圖案化之後，殘留物123形成在被開口145暴露出的部分焊墊142中。此後，對被開口145暴露出的部分焊墊142執行電路探針(CP)測試，從而形成探針標記127，探針標記127凹進或凹陷到焊墊142的頂表面中。在這種情形中，在一些實施例中，被開口145暴露出的部分焊墊142被視為測試焊墊。
參照圖3A及圖3B，在第一晶粒101’之上形成第一接合結構135以形成半導體結構100’。在上述實施例中已示出第一接合結構135的配置、材料及形成方法，因此，此處省略其細節。如圖3B所示，第一虛設金屬特徵138對應於頂部金屬特徵108a 及探針標記127，而第一接合金屬層132對應於頂部金屬特徵108b。第一虛設金屬特徵138藉由接合介電材料130a與焊墊142電隔離。第一接合金屬層132穿透第一接合介電層130及頂蓋層144以電連接到焊墊142。在這種情形中，位於探針標記127之外的另一部分焊墊142被視為連接焊墊CP，連接焊墊CP將信號從第一晶粒101’傳輸到上覆的第二晶粒201’(如圖3C所示)。應注意，在一些實施例中，頂蓋層144能夠在前述圖案化製程期間保護連接焊墊CP不形成殘留物，從而維持連接焊墊CP與第一接合金屬層132之間的接觸電阻。由此，分佈在整個第一半導體結構100’(或整個半導體晶圓)中的連接焊墊CP與第一接合金屬層132之間的接觸電阻具有更好的均勻性，從而提高第一半導體結構100’的良率。
參照圖3C，提供第二半導體結構200’。詳細來說，第二半導體結構200’包括第二晶粒201’及設置在第二晶粒201’之上的第二接合結構235。在一些實施例中，第二半導體結構200’的配置、材料及形成方法與第一半導體結構100’的配置、材料及形成方法相似。也就是說，第二半導體結構200’也包括焊墊242與焊墊242上的頂蓋層244，其中部分焊墊242外露於頂蓋層244且探針標記227凹進或凹陷到部分焊墊242中。具有探針標記227的部分焊墊242對應於頂部金屬特徵208a，而探針標記227之外的另一部分焊墊242對應於頂部金屬特徵208b。在此省略其他細節。第二半導體結構200’與第一半導體結構100’之間的差異在於 焊墊142藉由插塞141電連接到第一內連結構104，而焊墊242藉由多個插塞241電連接到第二內連結構204，插塞241包括第一插塞241a及第二插塞241b。在一些實施例中，可視需要調整焊墊與內連結構之間的插塞的數目。
參照圖3C，將第二半導體結構200’進一步上下翻轉並安裝到第一半導體結構100’上。也就是說，第一晶粒101’與第二晶粒201’藉由第一接合結構135及第二接合結構235(即，混合接合結構35)面對面地接合在一起以形成3DIC結構20(或被稱為晶粒堆疊結構20)。然而，本公開的實施例並非僅限於此。在其他實施例中，第一晶粒101’與第二晶粒201’可面對背地接合在一起。
圖3D是根據第三實施例的3DIC結構的剖視圖。
參照圖3D，將第二半導體結構200進一步上下翻轉並安裝到第一半導體結構100’上。也就是說，第一晶粒101’與第二晶粒201藉由第一接合結構135及第二接合結構235面對面地接合在一起以形成3DIC結構30(或被稱為晶粒堆疊結構30)。也就是說，半導體結構100、100’、200及200’中的任何兩個半導體結構均可藉由混合接合結構35接合在一起以形成3DIC結構。
圖5A到圖5B是根據第四實施例的形成半導體結構的方法的剖視圖。圖6是示出圖5A所示結構的俯視圖。
參照圖5A，結構501是藉由圖1A所示結構而形成的。在形成圖1A所示結構之後，對導電材料112及頂蓋材料114進行圖案化以形成焊墊142及焊墊142之上的頂蓋層544。如圖5A及 圖6的俯視圖所示，焊墊142可被配置成沿著從頂部金屬特徵108a到頂部金屬特徵108b的方向延伸的區塊結構。接著對頂蓋層144進行圖案化以形成暴露出部分焊墊142的開口545。應注意，如圖6所示，開口545具有對齊標記AM，使得被開口545暴露出的部分焊墊142的頂表面的俯視圖形狀是多邊形。在一些實施例中，對齊標記AM可設置在開口545的任何面或隅角處，用以為探針128的對齊提供方向。在對頂蓋層544進行圖案化之後，在被開口545暴露出的部分焊墊142中形成殘留物123。此後，對被開口545暴露出的部分焊墊142執行電路探針(CP)測試，從而形成探針標記127，探針標記127凹進或凹陷到焊墊142的頂表面中。在這種情形中，在一些實施例中，被開口545暴露出的部分焊墊142被視為測試焊墊。
參照圖5A及圖5B，在第一晶粒501之上形成第一接合結構135以形成半導體結構500。在以上實施例中示出第一接合結構135的配置、材料及形成方法。因此，此處省略其細節。此後，半導體結構500可藉由混合接合結構35接合到半導體結構100、100’、200及200’中的任何一個半導體結構，從而形成新的3DIC結構。
根據一些實施例，一種半導體結構包括基底、內連結構、導電焊墊、介電頂蓋以及接合結構。所述內連結構設置在所述基底之上。所述導電焊墊設置在所述內連結構之上並電連接到所述內連結構。所述介電頂蓋設置在所述導電焊墊之上並暴露出所述 導電焊墊的頂表面的一部分。所述導電焊墊的所述頂表面的所述一部分具有探針標記。所述接合結構設置在所述介電頂蓋之上。所述接合結構包括接合金屬層，所述接合金屬層穿透所述介電頂蓋以電連接到所述導電焊墊。
根據一些實施例，一種三維積體電路(3DIC)結構包括接合在一起的第一晶粒與第二晶粒。所述第一晶粒及所述第二晶粒中的一者具有導電焊墊及設置在所述導電焊墊之上的介電頂蓋。所述介電頂蓋暴露出所述導電焊墊的頂表面的具有探針標記的一部分。
根據一些實施例，一種製作半導體結構的方法包括以下步驟。在基底之上形成內連結構。在所述內連結構之上形成導電焊墊以及在所述導電焊墊之上形成介電頂蓋。對所述介電頂蓋進行圖案化以暴露出所述導電焊墊的頂表面的一部分。執行電路探針(CP)測試，以使所述導電焊墊的所述頂表面的所述一部分具有探針標記。在所述介電頂蓋之上形成接合結構。所述接合結構包括接合金屬層，所述接合金屬層穿透所述介電頂蓋以電連接到所述導電焊墊。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識 到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
10:3DIC結構
35:混合接合結構
100:第一半導體結構
101:第一晶粒
101a:第一晶粒的正面
102:第一半導體基底
103:第一元件層
104:第一內連結構
106:第一絕緣材料
108:第一金屬特徵
110:第一鈍化層
110a、110b、210a、210b:鈍化材料
122、222:焊墊
122a、222a:第一焊墊
122b、222b:第二焊墊
123、223:殘留物
124、224:頂蓋層
124c、224c:第一頂蓋層
124b、224b:第二頂蓋層
127、227:探針標記
130:第一接合介電層
130a、130c、230a、230c:接合介電材料
130b:第一阻擋層
132:第一接合金屬層
134、234:通孔插塞
135:第一接合結構
136、236:金屬特徵
138:第一虛設金屬特徵
200:第二半導體結構
201:第二晶粒
201a:第二晶粒的正面
202:第二半導體基底
203:第二元件區
204:第二內連結構
206:第二絕緣材料
208:第二金屬特徵
210:第二鈍化層
230:第二接合介電層
230b:第二阻擋層
232:第二接合金屬層
235:第二接合結構
238:第二虛設金屬特徵
P1:第一部分
P2:第二部分
P3:第三部分

Claims (9)

  1. 一種半導體結構，包括：內連結構，設置在基底之上；導電焊墊，設置在所述內連結構之上並電連接到所述內連結構；介電頂蓋，設置在所述導電焊墊之上並暴露出所述導電焊墊的頂表面的一部分，其中所述導電焊墊的所述頂表面的所述一部分具有探針標記，且被所述介電頂蓋暴露出的所述導電焊墊的所述頂表面的所述一部分具有對齊標記在其中；以及接合結構，設置在所述介電頂蓋之上，其中所述接合結構包括接合金屬層，所述接合金屬層穿透所述介電頂蓋以電連接到所述導電焊墊。
  2. 如申請專利範圍第1項所述的半導體結構，其中所述探針標記凹陷到所述導電焊墊的所述頂表面的所述一部分中。
  3. 如申請專利範圍第1項所述的半導體結構，其中所述導電焊墊包括彼此隔開的第一焊墊與第二焊墊，所述介電頂蓋包括彼此隔開的第一頂蓋層與第二頂蓋層，所述第一頂蓋層暴露出所述第一焊墊的頂表面的一部分及所述探針標記，且所述第二頂蓋層覆蓋所述第二焊墊的頂表面。
  4. 如申請專利範圍第3項所述的半導體結構，其中所述第一焊墊與所述接合金屬層電隔離。
  5. 如申請專利範圍第3項所述的半導體結構，其中所述第二焊墊電連接到所述接合金屬層。
  6. 一種三維積體電路(3DIC)結構，包括：接合在一起的第一晶粒與第二晶粒，其中所述第一晶粒及所述第二晶粒中的一者具有導電焊墊及設置在所述導電焊墊之上的介電頂蓋，所述介電頂蓋暴露出所述導電焊墊的頂表面的一部分，且所述導電焊墊的所述頂表面的所述一部分具有探針標記以及對齊標記。
  7. 如申請專利範圍第6項所述的三維積體電路結構，其中所述第一晶粒及所述第二晶粒藉由混合接合結構而接合在一起，所述混合接合結構包括：第一部分，包括接合在一起的第一接合金屬層與第二接合金屬層；以及第二部分，包括接合在一起的第一接合介電層與第二接合介電層，其中所述第一接合金屬層設置在所述第一接合介電層中且所述第二接合金屬層設置在所述第二接合介電層中。
  8. 一種製作半導體結構的方法，包括：在基底之上形成內連結構；在所述內連結構之上形成導電焊墊以及在所述導電焊墊之上形成介電頂蓋；對所述介電頂蓋進行圖案化以暴露出所述導電焊墊的頂表面的一部分，其中被所述介電頂蓋暴露出的所述導電焊墊的所述頂 表面的所述一部分具有對齊標記在其中；執行電路探針(CP)測試，且所述導電焊墊的所述頂表面的所述一部分具有探針標記；以及在所述介電頂蓋之上形成接合結構，其中所述接合結構包括接合金屬層，所述接合金屬層穿透所述介電頂蓋以電連接到所述導電焊墊。
  9. 如申請專利範圍第8項所述的製作半導體結構的方法，其中所述形成所述導電焊墊及所述介電頂蓋包括：在所述內連結構之上依序形成導電材料及頂蓋材料；以及對所述導電材料及所述頂蓋材料進行圖案化以形成彼此隔開的第一焊墊與第二焊墊並形成彼此隔開的第一頂蓋層與第二頂蓋層，其中在對所述介電頂蓋進行圖案化之後，所述第一頂蓋層形成在所述第一焊墊上並暴露出所述第一焊墊的頂表面的一部分及所述探針標記，且所述第二頂蓋層形成在所述第二焊墊上並覆蓋所述第二焊墊的頂表面。
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