CN104051337B - 立体堆叠集成电路系统芯片封装的制造方法与测试方法 - Google Patents

立体堆叠集成电路系统芯片封装的制造方法与测试方法 Download PDF

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CN104051337B
CN104051337B CN201410168052.XA CN201410168052A CN104051337B CN 104051337 B CN104051337 B CN 104051337B CN 201410168052 A CN201410168052 A CN 201410168052A CN 104051337 B CN104051337 B CN 104051337B
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chip
bare chip
wafer
semiconductor crystal
system integration
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CN104051337A (zh
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毛剑宏
韩凤芹
王志玮
畅文芬
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China Core Integrated Circuit Ningbo Co Ltd
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Shanghai Juexin Photoelectric Technology Co Ltd
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Priority to US14/694,868 priority patent/US9570429B2/en
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Abstract

本发明提供一种集成电路芯片立体堆叠系统集成封装的制造方法和测试方法，所述制造方法包括：第一裸芯片的表面边界处的第一互连引线焊盘表面裸露；第二裸芯片的表面边界处的第二互连引线焊盘表面裸露；将第二裸芯片表面上的第二介电质层与第一裸芯片表面上的第一介电质层键合；将键合有第二裸芯片的第一半导体晶圆进行电镀，使电镀体从第二裸芯的边界纵向填充所述空腔，形成使第一互连引线焊盘和第二互连引线焊盘上下对应互连的电镀电学互连体。本发明的集成电路芯片立体堆叠系统集成封装的制造方法与测试方法，实现系统集成封装、电学互连和系统测试的晶圆化，具有工艺简单、集成度高、成本低等优点。

Description

立体堆叠集成电路系统芯片封装的制造方法与测试方法
技术领域
本发明提供一种集成电路芯片立体堆叠系统集成封装的制造方法与测试方法，涉及半导体系统集成和封装技术领域。
背景技术
在集成电路系统集成封装测试领域中，采用不同形式的三维立体堆叠模式的系统集成封装(SiP,System-in-Package)，已经得到越来越多的应用。例如，最典型的上下两个芯片立体堆叠系统封装可以：
1)通过固化胶将上下裸芯立体堆叠至基板上，并采用引线互连(wire bond)将两个裸芯接口引线至基板上来实现；
2)通过固化胶将上下裸芯立体堆叠至基板上，并采用wire bond将上裸芯接口引线至下裸芯焊接板上，再将下裸芯的接口接至基板上来实现；
3)通过预制于上裸芯表面的凸点焊与下裸芯表面的凸点焊对接倒装焊接，并采用wire bond将下裸芯的接口接至基板上来实现；
4)通过预制于上裸芯表面的凸点焊与下裸芯表面的凸点焊对接倒装焊接，并采用预制于下裸芯内的硅通孔互连(TSV)将接口连至下裸芯背面来实现。
其中，凸点倒装焊接工艺得到越来越多的应用，尤其是未来基于硅通孔互连(TSV)以及微凸点倒装焊的高密度系统集成封装。然而，通过高密度凸点倒装焊接工艺来实现立体堆叠互连，技术难度仍然很大，制造成本很高，尤其是在完成裸芯的微凸点倒装焊接之后，对裸芯间的缝隙液体介质的无微孔填充及可靠固化，仍然是非常挑战性的技术，尤其是成品率和加工成本因素。
发明内容
本发明解决的技术问题是简化封装工艺，提高器件性能。
为解决上述问题，本发明提出一种新的集成电路芯片立体堆叠系统集成封装制造主要特征包括以下基本工艺：
提供含有多个第一裸芯110的第一半导体晶圆100，其中与第一半导体晶圆100的上表面101同面的每个第一裸芯110表面大部被第一介电质层20覆盖，所含接近其边界的第一互连引线焊盘190表面裸露；
提供多个第二裸芯210，每个第二裸芯210的表面大部被第二介电质层220覆盖，所含接近其边界的第二互连引线焊盘290表面裸露；
通过第二裸芯210表面上的第二介电质层220与第一半导体晶圆100上对应的第一裸芯110表面上第一介电质层120键合，同时第二裸芯210上表面裸露的第二互连引线焊盘290和第一裸芯110上表面裸露的第一互连引线焊盘190水平对位，上下相对形成与第二裸芯210边界联通的电镀互连空腔90；
以第一半导体晶圆100为载体携带多个键合的第二裸芯210，通过电镀导电电镀体95从第二裸芯210的边界纵向填充电镀互连空腔90，形成上下对位的第一互连引线焊盘190和第二互连引线焊盘290的电镀电学互连195。
本发明还提供了一种集成电路芯片立体堆叠系统集成封装的测试方法，其特征在于，还包括步骤：
在空腔外部的第一半导体晶圆上表面形成与电镀电学互连体互连的输入输出引线焊盘；
切断所有第一互连引线焊盘的电学连接，
利用微探针接触第一裸芯片上连接电镀电学互连体的输入输出引线焊盘，完成集成的第一裸芯和第二裸芯系统电子学测试。
本发明通过含有多个表面覆盖介电质的第一裸芯的第一半导体晶圆为载片，与从第二半导体晶圆上分离的多个表面覆盖介电质的第二裸芯的介电质键合，并采用电镀方法将位于第二裸芯边缘裸露出的第二互连引线焊盘与第一半导体晶圆上相对应的第一裸芯裸露的第一互连引线焊盘连接，以实现第一裸芯和第二裸芯的立体堆叠系统集成，同时凭借微探针接触第一裸芯上覆盖电镀焊点的输入输出引线焊盘，完成对以此堆叠互连所集成的系统电子学测试。
本发明的集成电路芯片立体堆叠系统集成封装制造与测试方法，实现系统集成封装、电学互连和系统测试的晶圆化，具有工艺简单、集成度高、成本低等优点。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
图1为本发明的立体堆叠集成电路系统芯片封装制造方法流程图。
图2为本发明的立体堆叠集成电路系统芯片封装的制造方法的一个典型构造示意性剖视图；
图3-图7为本发明的立体堆叠集成电路系统芯片封装制造方法的第一实施例的示意图；
图8-图11为本发明的立体堆叠集成电路系统芯片封装制造方法的第二实施例的示意图；
图12-图15为本发明的立体堆叠集成电路系统芯片封装制造方法的第三实施例的示意图；
图16-图18为本发明的立体堆叠集成电路系统芯片封装制造方法的第四实施例的示意图；
图19-图23为本发明的立体堆叠集成电路系统芯片封装制造方法的第五实施例的示意图。
具体实施方式
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。在本发明中“第一”“第二”仅是为了区分不同的部件，不对本能理解为对本发明的限定。
在集成电路系统集成封装测试领域中，有时候需要将两种不同功能或者结构的芯片集成在一起，也就是采用三维立体堆叠模式的SIP，这种封装不仅需要将两片芯片键合在一起，同时还需要连接其互连引线，从而实现电学互连，现有技术中常用的4种SIP的方法请参见发明内容部分。下面对本发明的SIP制造方法进行详细的说明。
第一实施例
参考图1在本实施例中，集成电路芯片立体堆叠系统集成封装的制造方法，包括下列步骤：
步骤S101：参考图2和图3，提供形成有多个第一裸芯片110的第一半导体晶圆100，其中第一裸芯片110的表面与第一半导体晶圆100的上表面101为同一表面，第一裸芯片110的表面边界处的第一互连引线焊盘190表面裸露，所述第一裸芯片110的表面其余部分被第一介电质层120覆盖。具体的，在本实施例中，第一半导体晶圆100采用硅半导体基板。第一介电质层120为固化绝缘胶。在其它实施例中，第一介电质层120也可为氧化硅，氮化硅等其他介电材料。裸芯片是指封装之前的芯片，其具有器件层和互连引线，互连引线在将要封装输出输出引脚的位置预留有互连引线焊盘，通常互连引线焊盘位于芯片的边界处。通常裸芯片互连引线焊盘暴露用于封装输入输出引脚，其他位置利用介电质层进行保护防止短路，互连引线焊盘暴露是采用在形成介电质层后刻蚀的方式，因此互连引线焊盘区域的表面低于介电质层的表面，即形成有凹槽，在本实施例中可以利用现有的裸芯片的制造工艺形成这种凹槽，也可以改变介电质层的厚度和材料，形成引线焊盘所在的凹槽，例如可以为方形的孔状凹槽。
步骤S102：参考图2和图3，提供多个第二裸芯片210，每个第二裸芯片210的表面边界处的第二互连引线焊盘290表面裸露，所述第二裸芯片210的表面其余部分被第二介电质层220覆盖，且第二裸芯片的裸露区域和第一裸芯片的裸露区域面积不等。在本实施例中，第二裸芯片可以具有上述的和第一裸芯片类似的表面结构，即互连引线焊盘区域的表面低于介电质层的表面，形成有凹槽。但是由于本申请中后续步骤要将第一裸芯片和第二裸芯片对应键合，因此为了保证键合后第一互连引线焊盘和第二互连引线焊盘不被密封在凹槽形成的空腔内，本申请中要求第二裸芯片的裸露区域(即第二裸芯片表面裸露的第二互连引线焊盘290)和第一裸芯片的裸露区域(即第一裸芯片表面裸露的第一互连引线焊盘190)面积不等，这样在键合后第一互连引线焊盘所在的凹槽和第二裸芯片所在的凹槽可以扣合形成一个空腔，该空腔不密闭，留有开口。
在本实施例中，第二介电质层220为固化绝缘胶。在其它实施例中，第二介电质层220也可为氧化硅。第二裸芯片210采用硅半导体基板，在其它实施例中，第二裸芯片210也可采用三五族或二六族半导体基板。
步骤S103：参考图2和图3，将第二裸芯片210与第一裸芯片110一一对应，并将第二裸芯片210表面上的第二介电质层220与第一裸芯片110表面上的第一介电质层120键合，同时第二裸芯210表面裸露的第二互连引线焊盘290和第一裸芯110表面裸露的第一互连引线焊盘190上下相对，从而形成空腔90，所述第一互连引线焊盘190和第二互连引线焊盘290位于该空腔90内。形成空腔90的说明在步骤S102中已经进行说明不再赘述。
在本实施例中，每个第二裸芯片210单独与第一半导体晶圆100上对应的第一裸芯210实施键合。即将分立第二裸芯片210一个一个的键合到第一半导体晶圆100上。
在本实施例中，是利用可固化绝缘胶合芯片键合，具体是通过液态镀膜结合热或辐射固化并实现芯片键合。除此之外，也可以利用本领域技术人员所熟知的其他键合方法。
步骤S104：参考图2和图4，将键合有第二裸芯片210的第一半导体晶圆100进行电镀，使电镀体95从第二裸芯210的边界纵向填充所述空腔90，形成使第一互连引线焊盘190和第二互连引线焊盘290上下对应互连的电镀电学互连体195。在本实施例中，所述电镀为无极电镀即化学镀。具体的，可以将键合后的结构放到溶液中，例如可以为化学镀银、镀镍、镀铜、镀钴、镀镍磷液、镀镍磷硼液等，不需要通电，依据氧化还原反应原理，利用强还原剂在含有金属离子的溶液中，将金属离子还原成金属而沉积在暴露的第一引线焊盘190表面，形成致密金属镀层，逐步将空腔90填满，从而实现第一裸芯片和第二裸芯片的互连封装。
在本实施例中优选的，键合之后，在相邻第二裸芯片210之间的间隙中，填充间隙填充介质225，并覆盖所有电镀电学互连195，具体可以为氧化硅、氮化硅或者其他介电材料，实现对电镀电学互连的绝缘和保护。
在本实施例中优选的，在完成电镀过程、形成上下对位的第一互连引线焊盘190和第二互连引线焊盘290的电学互连之后，还包括：
步骤1041：参考图2和图5，图7，去除各第一裸芯片之间，以及各第二裸芯片之间的相互结合部，将第二裸芯片210与第一裸芯片110键合后的堆叠体一一分离，使之相互独立。具体，可以先刻蚀去除第二裸芯片210间的介电材料例如填充间隙填充介质，使第二裸芯片分离；继续刻蚀第一裸芯片110之间的第一半导体晶圆100，形成沟槽112；然后可以继续刻蚀直到第一裸芯片110分离，或者采用研磨第一半导体晶圆100下表面(背面)的方式使第一裸芯片分离。
通常半导体芯片是在半导体晶圆的一个表面上外延半导体材料形成，即为正面(上表面)，半导体晶圆的另一个表面即为背面(下表面)。
第二实施例
第二实施例与第一实施例相同的步骤不再赘述，不同在于：所述步骤S103中，包括：
步骤S1031：参考图2和图8，将多个相互分离的第二裸芯片210按照和第一裸芯片110一一对应的位置排列，所有第二裸芯片210的第二介电质层220至于同一平面上，相互间填充注塑剂209，注塑成第二晶圆200。参考图9，然后刻蚀第二互连引线焊盘290所在区域的注塑剂209，暴露第二互连引线焊盘。
步骤S1032：参考图2，图10和图11，将第二晶圆200与第一半导体晶圆100实现上下对位，以实现第二晶圆200上每个第二裸芯片210与第一半导体晶圆100上相对应的第一裸芯片110一一对应，通过第二裸芯片210上的第二介电质层220与第一裸芯片110上的第一介电质层120的键合，实现第二晶圆200与第一半导体晶圆100以及每个第二裸芯片210与相对应的第一裸芯片110一一对准键合；
步骤S1033：部分或全部去除注塑剂209。采用灰化、干法刻蚀或者湿法刻蚀去除注塑剂209。从第二晶圆200与键合表面201相对的背面202对第二晶圆200背晶减薄。
在本实施例中，第一半导体晶圆100与第二晶圆200大小相同，且第一半导体晶圆上的第一裸芯片数量与第二晶圆上的第二裸芯片数量相同，所述的第二裸芯片210表面第二介电质层220与第一裸芯片110第一介电质层120的键合，是通过第一半导体晶圆100与第二晶圆200间的光学对准晶圆级键合实现。
在本实施例中，在第二晶圆200表面上通过刻蚀形成表面刻蚀沟槽206，完成第一半导体晶圆100与第二晶圆200间的光学对准晶圆级键合之后，对第二晶圆200的背面实施背晶减薄，以暴露出表面刻蚀沟槽206和其下第一半导体晶圆100的表面，以此将各个第二芯片210相互分离。
也可以在第一半导体晶圆上预先刻蚀形成表面刻蚀沟槽，用于分离第一裸芯片。
第三实施例
与前述实施例中相同的步骤不再赘述，不同在于：
在本实施例中，参考图2，每个第一裸芯片110表面上的所有第一互连引线焊盘190电学连接。具体的，在本实施例中是采用所述第一半导体晶圆100表面形成有包含导电边框108的导电网格状互连线109，与每个第一芯片110表面上的所有第一互连引线焊盘190实现电学连接，其导电边框108覆盖第一半导体晶圆的边缘。
在芯片的制造过程中，需要沉积金属层，然后刻蚀，形成想要的金属互连引线，最后刻蚀打开芯片表面的介电层，暴露金属互连引线的输入输出连接区域，即为互连引线焊垫。在本实施例中由于后期要采用有极电镀的方式在互连引线焊点表面电镀金属层，因此可以在形成金属互连引线的步骤中，使得形成的所有第一芯片的金属互连引线都通过芯片外部的金属互连引线相连，并且一直连接到第一半导体晶圆的边缘区域，所有的互连引线即为导电网格状互连线，芯片外部的互连引线连接的部分即为导电边框108。
本实施例中，步骤S104电镀为有极电镀，实施电镀的两个电极之一在电镀过程中保持与所述第一互连引线焊盘电学连接，例如和导电边框108电学连接。在本实施例中是和第一半导体晶圆的边缘区域的一整圈金属互连引线相连。这样，在电镀的过程中，金属便沉积在第一互连引线表面，从而填充第一互连引线焊盘所在的空腔，实现第一互连引线焊盘和第二互连引线焊盘的互连。
在本实施例中优选的，有极电镀所形成的电镀体95为金属铜、镍、锌、锡、银、金、钨、镁，以及其中任何两种元素的合金。这是利用传统的气相淀积所难以达到的，现有的气相淀积通常仅可以形成单一金属或者叠层结构。
在本实施例中，参考图12-图13，还优选的，第二裸芯片210位于第二半导体晶圆200上。也就是第二裸芯片210是半导体工艺制作完成后尚未切割，全部位于第二半导体晶圆200上，这样优点在于减少了切割第二裸芯片210的步骤，并且可以更精确的实现光学对准晶圆级键合。
参考图14-15，在本实施例中，优选的从第二半导体晶圆200与键合表面201相对的背面202对第二半导体晶圆200背晶减薄。
第一半导体晶圆100与第二半导体晶圆200大小相同，且第一半导体晶圆上的第一裸芯片数量与第二半导体晶圆上的第二裸芯片数量相同，所述的第二裸芯片210表面第二介电质层220与第一裸芯片110第一介电质层120的键合，是通过第一半导体晶圆100与第二半导体晶圆间的光学对准晶圆级键合实现。
在本实施例中，优选的，所述晶圆级键合之前，在第二半导体晶圆上的每个第二裸芯210边界通过刻蚀形成表面沟槽206。完成第一半导体晶圆100与第二半导体晶圆200间的光学对准晶圆级键合之后，对第二半导体晶圆200的背面实施背晶减薄，以暴露出表面刻蚀沟槽206和其下第一半导体晶圆100的表面，以此将各个第二芯片210相互分离。
在本实施例中，步骤1041：去除各第一裸芯片之间，以及各第二裸芯片之间的相互结合部，将第二裸芯片210与第一裸芯片110键合后的堆叠体一一分离。由于本实施例中，所有的第一互连引线都是连接在一起的，因此需要切断所有第一互连引线焊盘190的电学连接，使之相互独立。例如可以通过切割芯片边缘，从而使导电边框被切除，从而断开第一互连引线焊盘190之间的互连。
第四实施例
与前述实施例中相同的步骤不再赘述，不同在于：
在本实施例中，参考图16所示，步骤101所述的第一半导体晶圆100上的所有第一裸芯片110含有与第一半导体晶圆上表面101相垂直的穿孔导电互连件130，该穿孔导电互连件130的始端131与第一裸芯片110的水平互连层140相连，穿孔导电互连件130的末端132深向第一半导体晶圆的下表面102。
步骤1041：参考图17，从第一半导体晶圆100下表面102对其减薄，暴露出穿孔导电互连件130的末端132。
参考图18，步骤104进一步包括：
步骤1042：对暴露出的第一半导体晶圆100的下表面102覆盖背晶介质覆盖层133，在背晶介质覆盖层133形成与在穿孔导电互连件130的末端132相连的背引线焊盘139。
第五实施例
与前述实施例中相同的步骤不再赘述，不同在于：
在本实施例中，参考图19和图20，步骤101所述的第二半导体晶圆上的所有第二裸芯片210含有与第二半导体晶圆上表面203相垂直的穿孔导电互连件230，该穿孔导电互连件230的始端231与第二裸芯片210的水平互连层240相连，穿孔导电互连件230的末端232深向第二晶圆的下表面202。
参考图21，步骤104进一步包括：
步骤1041：从第二半导体晶圆200下表面(背面)202对其减薄，暴露出穿孔导电互连件230的末端232。
参考图22，第二半导体晶圆200背面202形成与在穿孔导电互连件230的末端232相连的背引线焊盘239。
在上述实施例中，去除芯片间的相互结合部的方法，包括通过机械切割和激光切割中的一种或组合来实现。
去除芯片间的相互结合部的方法，包括通过预制于第一半导体晶圆100或第二晶圆200内的垂直刻蚀沟槽，凭借机械外力引发垂直刻蚀沟槽裂纹扩展来实现。
参考图23，按照以上类似的方法，还可以堆叠第三裸芯片，例如可以将第二裸芯片210和第三裸芯片310同时堆叠在第一半导体晶圆100上，通过电镀使电镀体从第二裸芯片210和第三裸芯片310的边界纵向填充空腔之后,在空腔外部的第一半导体晶圆上表面形成输入输出引线焊盘，实现第一裸芯片110与第二裸芯片210和第三裸芯片310的系统集成互连；这里需要注意的是：第二裸芯片210和第三裸芯片310可以是不同大小乃至不同种类的芯片。以此类推，采用本发明陈述的方法可以实现第一裸芯片110与一个以上种类的裸芯片的堆叠互连和集成。
另外本发明还提供了一种上述立体堆叠集成电路系统芯片封装的测试方法参考图6，除包括上述集成电路芯片立体堆叠系统集成封装的制造方法外还包括步骤：
使电镀体95从第二裸芯210的边界纵向填充所述空腔90之后在空腔外部的第一半导体晶圆100上表面形成输入输出引线焊盘192，其覆盖电镀电学互连体，与其导电互连；
切断所有第一互连引线焊盘190的电学连接；
利用微探针接触第一裸芯片110上连接导电电镀体95的输入输出引线焊盘192，完成对以此堆叠互连所集成的第一裸芯110和第二裸芯210系统电子学测试。
除此之外，也可以利用电镀的方法在第一半导体晶圆的其他位置形成与电镀体95导电互连的输入输出引线焊盘192。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (29)

1.一种集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，所述方法包括：
步骤S101：提供形成有多个第一裸芯片的第一半导体晶圆，其中第一裸芯片的表面与第一半导体晶圆的上表面位于同一平面，第一裸芯片的表面边界处的第一互连引线焊盘表面裸露，所述第一裸芯片的表面其余部分被第一介电质层覆盖；
步骤S102：提供多个第二裸芯片，每个第二裸芯片的表面边界处的第二互连引线焊盘表面裸露，所述第二裸芯片的表面其余部分被第二介电质层覆盖，且第二裸芯片的裸露区域和第一裸芯片的裸露区域面积不等；
步骤S103：将第二裸芯片与第一裸芯片一一对应，并将第二裸芯片表面上的第二介电质层与第一裸芯片表面上的第一介电质层键合，同时第二裸芯表面裸露的第二互连引线焊盘和第一裸芯表面裸露的第一互连引线焊盘上下相对，从而形成空腔，所述第一互连引线焊盘和第二互连引线焊盘位于该空腔内；
步骤S104：将键合有第二裸芯片的第一半导体晶圆进行电镀，使电镀体从第二裸芯的边界纵向填充所述空腔，形成使第一互连引线焊盘和第二互连引线焊盘上下对应互连的电镀电学互连体。
2.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，所述步骤S103中，每个第二裸芯片单独与第一半导体晶圆上对应的第一裸芯片实施键合。
3.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，在所述步骤S103中，包括：
将多个相互分离的第二裸芯片按照和第一裸芯片一一对应的位置排列，所有第二裸芯片的第二介电质层至于同一平面上，相互间填充注塑剂，注塑成第二晶圆；
将第二晶圆与第一半导体晶圆实现上下对位，以实现第二晶圆上每个第二裸芯片与第一半导体晶圆上相对应的第一裸芯片一一对应，通过第二裸芯片上的第二介电质层与第一裸芯片上的第一介电质层键合，实现第二晶圆与第一半导体晶圆以及每个第二裸芯片与相对应的第一裸芯片一一对准键合；
部分或全部去除注塑剂。
4.如权利要求3所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，在第一裸芯片和第二裸芯片键合之后还包括步骤：从第二晶圆与键合表面相对的背面对第二晶圆背晶减薄。
5.如权利要求3所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，去除注塑剂是采用灰化、干法刻蚀或者湿法刻蚀的方法。
6.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，所述步骤S103中，第二裸芯片位于第二半导体晶圆上。
7.如权利要求3-6中任意一项所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，第一半导体晶圆与第二晶圆或者第二半导体晶圆大小相同，且第一半导体晶圆上的第一裸芯片数量与第二晶圆上的第二裸芯片数量相同，所述的第二裸芯片表面的第二介电质层与第一裸芯片表面的第一介电质层的键合是通过第一半导体晶圆与第二晶圆或者第二半导体晶圆间的光学对准晶圆级键合实现。
8.如权利要求7所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，在实施所述晶圆级键合之前，在第一半导体晶圆上的每个第一裸芯边界通过刻蚀形成表面刻蚀沟槽。
9.如权利要求8所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，在第二晶圆或者第二半导体晶圆表面上通过刻蚀形成表面刻蚀沟槽，完成第一半导体晶圆与第二晶圆间的光学对准晶圆级键合之后，对第二晶圆的背面实施背晶减薄，以暴露出表面刻蚀沟槽和其下第一半导体晶圆的表面，以此将各个第二裸芯片相互分离。
10.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，步骤S101中每个第一裸芯片表面上的所有第一互连引线焊盘电学连接；
其中，步骤S104电镀为有极电镀，实施电镀的两个电极之一在电镀过程中保持与所述第一互连引线焊盘电学连接。
11.如权利要求10所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于所述第一半导体晶圆表面形成有包含导电边框的导电网格状互连线，其与每个第一裸芯片表面上的所有第一互连引线焊盘实现电学连接，所述导电边框覆盖第一半导体晶圆的边缘；
其中，步骤S104电镀为有极电镀，实施电镀的两个电极之一在电镀过程中保持与导电边框电学连接。
12.如权利要求10所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，在完成电镀过程、形成上下对位的第一互连引线焊盘和第二互连引线焊盘的电学互连之后，包括：
去除各第一裸芯片之间，以及各第二裸芯片之间的相互结合部，将第二裸芯片与第一裸芯片键合后的堆叠体一一分离，同时切断所有第一互连引线焊盘的电学连接，使之相互独立。
13.如权利要求10所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，有极电镀所形成的电镀体为金属铜、镍、锌、锡、银、金、钨、镁，以及其中任何两种元素的合金。
14.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，步骤104中的电镀为无极电镀。
15.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，步骤104进一步包括：键合之后，在相邻第二裸芯片之间的间隙中，填充间隙填充介质，并覆盖所有电镀电学互连体。
16.如权利要求3-6中任意一项所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，步骤101所述的第一半导体晶圆上的所有第一裸芯片含有与第一半导体晶圆上表面相垂直的穿孔导电互连件，该穿孔导电互连件的始端与第一裸芯片的互连层相连，末端深向第一半导体晶圆的下表面。
17.如权利要求16所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，步骤104进一步包括：
从第一半导体晶圆下表面对其减薄，暴露出穿孔导电互连件的末端。
18.如权利要求17所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，步骤104进一步包括：
对暴露出的第一半导体晶圆的下表面覆盖背晶介质覆盖层，在背晶介质覆盖层形成与穿孔导电互连件的末端相连的背引线焊盘。
19.如权利要求12所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，所述去除芯片间的相互结合部的方法，包括通过机械切割和激光切割中的一种或组合来实现。
20.如权利要求12所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，所述去除芯片间的相互结合部的方法，包括通过预制于第一半导体晶圆或第二晶圆或第二半导体晶圆内的垂直刻蚀沟槽，凭借机械外力引发垂直刻蚀沟槽裂纹扩展来实现。
21.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，第一半导体晶圆采用硅半导体基板。
22.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，第二裸芯片采用硅半导体基板。
23.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，第二裸芯片采用三五族或二六族半导体基板。
24.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，所述第一介电质层或所述第二介电质层为氧化硅或可固化绝缘胶。
25.如权利要求24所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，利用所述可固化绝缘胶键合芯片的方法是通过液态镀膜结合热或辐射固化并实现芯片键合。
26.如权利要求3-6任意一项所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，所有所述第二裸芯片含有与其表面相垂直的穿孔导电互连件，所述穿孔导电互连件的始端与第二裸芯片的互连层相连，末端深向第二裸芯片的下表面。
27.如权利要求26所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，步骤104进一步包括：
从第二半导体晶圆或者第二晶圆下表面对其减薄，暴露出穿孔导电互连件的末端。
28.如权利要求1所述的集成电路芯片立体堆叠系统集成封装的制造方法，其特征在于，包括：
提供多个不相同的第三裸芯片，其表面边界处的互连引线焊盘表面裸露，所述第三裸芯片的表面其余部分被介电质层覆盖，且所述第三裸芯片的裸露区域和第一裸芯片的裸露区域面积不等；
在步骤S104和步骤S104中进行所述第三裸芯片和所述第一裸芯片的键合和电镀。
29.一种包括权利要求1-27所述的制造方法的集成电路芯片立体堆叠系统集成封装的测试方法，其特征在于，还包括步骤：
在空腔外部的第一半导体晶圆上表面形成与电镀电学互连体互连的输入输出引线焊盘；
切断所有第一互连引线焊盘的电学连接，
利用微探针接触第一裸芯片上连接电镀电学互连体的输入输出引线焊盘，完成集成的第一裸芯和第二裸芯系统电子学测试。
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