JP4528035B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4528035B2 JP4528035B2 JP2004180628A JP2004180628A JP4528035B2 JP 4528035 B2 JP4528035 B2 JP 4528035B2 JP 2004180628 A JP2004180628 A JP 2004180628A JP 2004180628 A JP2004180628 A JP 2004180628A JP 4528035 B2 JP4528035 B2 JP 4528035B2
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Description
あるいは、ボンディングパッド下部領域の前記隣接する銅膜の各々が平面的に設けられており、銅膜がパッシベーション膜の開口領域よりも大きくなるようにしてもよい。
なお、図面の説明においては、同一要素には同一符号を付し、重複する説明を省略する。
図1は、本発明の第一の実施形態に係る半導体装置の要部を示す図であり、図2(a)は本実施形態における層間絶縁膜28の上面図であり、図2(b)は本実施形態における層間絶縁膜32の上面図であり、図2(c)は本実施形態における層間絶縁膜34の上面図である。
図3および図4は、本実施形態に係る半導体装置の製造工程を示す図である。
絶縁膜12(図3(a))上に、CVD(chemical vapor deposition)法により全面に膜厚が10〜50nmのシリコン窒化膜、300〜2000nmのSiOCなどの低誘電率膜からなる層間絶縁膜34を形成した後、フォトリソグラフィ技術を使用したプラズマエッチング法により、第2銅膜を形成するための溝を形成する。次に、スパッタ法により全面に膜厚が10〜50nmのタンタル膜とタンタル窒化膜との積層膜からなるバリアメタル膜を形成した後、続けて50〜300nmの銅シード膜を形成し、めっき法により銅膜を形成して、溝内に完全に銅膜を埋め込むようにする。続いて、CMP法により不要なバリアメタル膜および銅膜を除去して、バリアメタル膜74および第1銅膜16が形成される(図3(b))。
図5は、本発明の第二の実施形態に係る半導体装置の要部を示す図である。
本実施形態に係る半導体装置10は、図1の第一の実施形態において層間絶縁膜28に設けた第2銅膜44およびシールリング銅膜46を連続して形成して、一つの第2銅膜22とした以外は、第一の実施形態に係る半導体装置40と同様の構成を有する。
図6は、本発明の第三の実施形態に係る半導体装置の要部を示す図である。
本実施形態に係る半導体装置90は、第一の実施形態に係る半導体装置40の下側に積層配線80が設けられ、さらに最下層の層間絶縁膜82に接するように半導体基板としてのシリコン基板86が設けられている。このシリコン基板86においては、外部接続端子となる半導体装置40の開口部の直下に電子素子であるMOS(metal oxide semiconductor)84を配置することができる。
16 第1銅膜
18 接続ビア
20 シールリング
22 第2銅膜
24 ボンディングパッド
26 配線
28 層間絶縁膜
29 絶縁膜
30 パッシベーション膜
32 層間絶縁膜
34 層間絶縁膜
40 半導体装置
42 シールリング
44 第2銅膜
46 シールリング銅膜
48 ボンディングパッド下部領域
50 ボンディングパッド下部領域
Claims (6)
- 第1の層間絶縁膜に形成された第1の銅膜と、
第2の層間絶縁膜に形成されたビアおよび前記ビアの外周領域に形成された第1のシールリングと、
第3の層間絶縁膜に形成され、前記第1の銅膜に前記ビアを介して接続される第2の銅膜および前記第2の銅膜を囲み、かつ、平面視したときに、前記第1のシールリングと同一領域に形成された第2のシールリングと、
前記第3の層間絶縁膜上に形成された凹部を有する第4の層間絶縁膜および前記凹部に形成されたボンディングパッドと
を有し、
前記第1の銅膜および前記ボンディングパッドは前記第1のシールリングと前記第2のシールリングにより接続され、かつ、前記第3の層間絶縁膜に前記第2のシールリングの外側の前記第2のシールリングが形成された領域と不連続な領域に前記ボンディングパッドに接する引き出し配線を有する半導体装置。 - 前記第4の層間絶縁膜上に開口部の形成されたパッシベーション膜を有し、前記引き出し配線を前記開口部の外側の領域に有する請求項1に記載の半導体装置。
- 平面視したときに、前記第1の銅膜の占める領域よりも内側の領域に前記開口部を有する請求項2に記載の半導体装置。
- 平面視したときに、前記第1のシールリングの占める領域よりも内側の領域に前記開口部を有する請求項2または3に記載の半導体装置。
- 前記第1の層間絶縁膜、前記第2の層間絶縁膜および前記第3の層間絶縁膜は炭素を含有する低誘電率膜であることを特徴とする請求項1〜4のいずれか1つに記載の半導体装置。
- 半導体基板と、前記半導体基板と前記第1の層間絶縁膜の間に電子素子を有し、前記電子素子が前記ボンディングパッド下部に設けられている請求項1〜5のいずれか1つに記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004180628A JP4528035B2 (ja) | 2004-06-18 | 2004-06-18 | 半導体装置 |
US11/153,619 US7301244B2 (en) | 2004-06-18 | 2005-06-16 | Semiconductor device |
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JP2004180628A JP4528035B2 (ja) | 2004-06-18 | 2004-06-18 | 半導体装置 |
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JP2006005202A JP2006005202A (ja) | 2006-01-05 |
JP4528035B2 true JP4528035B2 (ja) | 2010-08-18 |
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JP2004180628A Active JP4528035B2 (ja) | 2004-06-18 | 2004-06-18 | 半導体装置 |
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US (1) | US7301244B2 (ja) |
JP (1) | JP4528035B2 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10337569B4 (de) * | 2003-08-14 | 2008-12-11 | Infineon Technologies Ag | Integrierte Anschlussanordnung und Herstellungsverfahren |
JP2006332533A (ja) * | 2005-05-30 | 2006-12-07 | Fujitsu Ltd | 半導体素子及びその製造方法 |
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JPH1064945A (ja) * | 1996-08-20 | 1998-03-06 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2001015516A (ja) * | 1999-06-30 | 2001-01-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2001298029A (ja) * | 1999-12-16 | 2001-10-26 | Lucent Technol Inc | ストレスを減少してパッドの下に回路を入れることができるようにするためのデュアル食刻ボンドパッド構造およびそれを形成するための方法 |
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