TWI546872B - 電子元件與半導體元件 - Google Patents

電子元件與半導體元件 Download PDF

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Publication number
TWI546872B
TWI546872B TW101123180A TW101123180A TWI546872B TW I546872 B TWI546872 B TW I546872B TW 101123180 A TW101123180 A TW 101123180A TW 101123180 A TW101123180 A TW 101123180A TW I546872 B TWI546872 B TW I546872B
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Taiwan
Prior art keywords
pad
layer
protective layer
passivation layer
bonding
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TW101123180A
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English (en)
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TW201340223A (zh
Inventor
余振華
李明機
李建勳
陳永慶
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台灣積體電路製造股份有限公司
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Publication of TW201340223A publication Critical patent/TW201340223A/zh
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Publication of TWI546872B publication Critical patent/TWI546872B/zh

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Description

電子元件與半導體元件
本發明有關於元件，且特別是有關於電子元件與半導體元件。
在封裝裝置中，積體電路(IC)晶片經常是以導線(例如金導線或是銅導線)電性連接至封裝基板，以進行外部的訊號交換。此種導線一般是利用熱壓合(thermal compression)及/或超音波振動(ultrasonic vibration)的方式接合至形成在積體電路晶片上的接墊。打線接合製程(wire bonding process)係使用熱應力與機械應力。應力係施加在接墊上，並傳遞至接墊下方的膜層以及結構。接墊的結構需能夠承受應力，以確保打線接合的品質。
現今許多製程使用低k值(low-k，低介電常數)以及超低k值介電材料作為金屬間介電(Inter-Metal Dielectric，IMD)層以降低RC延遲(RC delay)以及寄生電容。一般而言，金屬間介電層的設計趨勢為使金屬間介電層的介電常數(k值)越來越小，從低k值降低至超低k值。也就是說，金屬間介電層(金屬線與導孔形成於其中)的機械性質相當易碎。再者，在打線接合的應力作用下，可能會使金屬間介電層剝離(delaminate)。因此，不利於接合製程的良率。
本發明一實施例提供一種電子元件，包括：一基板；一接墊，位於基板上；一保護層，位於接墊上，其中保護 層與接墊的材質不同；一接合球，配置於保護層上；以及一接合線，連接接合球。
本發明另一實施例提供一種半導體元件，包括：一半導體基板；一接墊，包括鋁與銅位於半導體基板上；一第一鈍化層，包括多個部分位於接墊的多個邊緣部分下；一第二鈍化層，包括多個部分位於接墊的邊緣部分上；一保護層，位於接墊上並接觸接墊，其中保護層包括一金層、與一鎳層位於金層上；一接合球，接合至保護層；以及一接合線，連接接合球，其中接合線電性連接至接墊。
本發明又一實施例提供一種半導體元件，包括：一半導體基板；一接墊，包括鋁與銅位於半導體基板上；一第一鈍化層，包括多個部分位於接墊的多個邊緣部分下；一第二鈍化層，包括多個部分位於接墊的邊緣部分上；一保護層，位於接墊上，其中保護層的硬度大於接墊的硬度；一接合球，接合至保護層上；以及一接合線，連接至接合球。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材 料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方便標示。再者，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。
以下將介紹多個實施例之打線接合結構。以下將討論多個實施例之多種變化。在所有的圖式與實施例中，相似的元件符號係用以標記相似的元件。
第1圖繪示本發明多個實施例之一晶片100的剖面圖。晶片100包括基板20以及主動電路22形成於基板20的一頂面上。在一些實施例中，基板20為一半導體基板，其材質包括矽、矽鍺、或其相似物。主動電路22可包括互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor，CMOS)電晶體、電阻、電容、及其相似物。晶片100的圖示區域24可為一輸入/輸出(Input/Output，IO)區。因此，主動電路22可為一輸入/輸出電路。在另外的實施例中，沒有主動電路形成在圖示的區域24中。然而，主動電路仍然可形成在晶片100的其他區域中。
內連線結構30形成在區域24中，且包括一部分位於主動電路22上並對齊主動電路22。內連線結構30包括多條金屬線34與多個導孔36，用以連接主動電路22的不同部分，以及用以將主動電路22連接至主動電路22上方的接墊50。內連線結構30包括多層介電層32，且金屬線34與導孔36係形成於介電層32中。在全文中，在同一水平面上的金屬線34可總稱為一金屬層。在一些實施例中，介 電層32為低k值介電層，其介電常數(k值)約低於3.0，或是約介於2.0與2.8之間。金屬線34與導孔36的材質包括銅或銅合金。在一些實施例中，金屬線34與導孔36具有電性連接的功能，且電流/訊號可流經金屬線34與導孔36。在另外的實施例中，金屬線34與導孔36為閒置的連接結構(dummy connection)，其非用以作為電性連接之用。因此，當晶片100通電時，沒有電流會流過閒置的金屬線34與導孔36。
內連線結構30包括多個頂介電層，金屬墊38、40形成於頂介電層中，且頂介電層的材質包括未摻雜的矽酸玻璃或是低k值介電材料。在一些實施例中，在內連線結構30的兩個頂金屬層(可稱為Mtop層與Mtop-1層)中，形成雙層的實心接墊(double solid pad)44。雙層的實心接墊44包括Mtop接墊40、Mtop-1接墊38、以及多個導孔42連接接墊40、38。Mtop接墊40、Mtop-1接墊38、以及導孔42的材質包括銅、鎢、或其他金屬，且其形成方法包括雙鑲嵌製程(dual damascene process)或是單鑲嵌製程(single damascene process)。或者是，Mtop接墊40以及Mtop-1接墊38的形成方法包括沉積金屬層以及蝕刻前述金屬層。
在一些實施例中，雙層的實心接墊44係實體接觸(physical contact)其上的接墊50。在另外的實施例中，雙層的實心接墊44可經由導孔(未繪示)電性連接至接墊50。在又一實施例中，係以一單一接墊取代雙層的實心接墊44，單一接墊係位於Mtop層中，並可形成於接墊50下。
鈍化層(passivation layer)46、48形成於基板20上並位於內連線結構30上。鈍化層46、48在本技術領域中可分別稱為鈍化-1與鈍化-2，其材質例如包括氧化矽、氮化矽、未摻雜的矽酸玻璃(un-doped silicate glass，USG)、及/或前述材料之多層結構。在一些實施例中，接墊50與一部分的鈍化層46形成在同一平面上。接墊50的邊緣部分可形成在該部分的鈍化層46上或者是對齊該部分的鈍化層46。再者，接墊50可包括一部分位於鈍化層48中、以及一被鈍化層48的開口53暴露出的部分。接墊50的邊緣部分可被部分的鈍化層48所覆蓋。接墊50的材質包括金屬材料，例如鋁、銅、銀、金、鎳、鎢、前述之合金、及/或前述之多層結構。在一些實施例中，接墊50的材質為鋁銅。在一些示範性的實施例中，接墊50中的鋁與銅的體積百分比(volume percentages)分別約為99.5%以及0.5%。在其他示範性的實施例中，接墊50包括鋁、矽、以及銅。在含矽的鋁銅中，鋁、矽、以及銅的體積百分比分別約為97.5%、2%、以及0.5%。接墊50可電性耦接至主動電路22，例如，可經由雙層的實心接墊44或是其他的內連線結構。接墊50的厚度例如約為5000埃至40000埃。
保護層52係形成於接墊50的頂面上。保護層52可為一單層結構、或是一包括多個膜層的複合層結構。在一些實施例中，保護層52包括金層52A與鎳層52B位於金層52A上。金層52A可接觸接墊50。保護層52可為一化鎳浸金(Electroless Nickel Immersion Gold，ENIG)結構，其係藉由浸漬法(immersion)形成。在另外的實施例中， 保護層可包括一化鎳鈀浸金(Electroless Nickel Electroless Palladium Immersion Gold，ENEPIG)結構，其包括一金層位於接墊50上、一鈀層位於金層上、以及一鎳層位於鈀層上。保護層52的形成方法包括電鍍、無電鍍、浸鍍、物理氣相沉積、或前述之組合。保護層52的硬度(hardness)可大於接墊50的硬度。
在晶片100的打線接合製程中，形成一打線以電性連接晶片100至另一封裝元件(未繪示)，例如一封裝基板、一導線架、或其相似物。接合製程係為打線接合至接墊50。各別的打線接合結構包括接合球(bond ball)56(亦即習知的植球，bump stud)以及接合線58，其中接合球56的直徑大於接合線58的直徑。接合球56以及接合線58的材質包括金、銅、鋁、及/或其相似物。接合線58係經由接合球56電性連接至接墊50，以及更電性連接至接墊50下的主動電路22。打線接合可為向前打線接合(forward wire bonding)、反向打線接合(reverse wire bonding)、疊凸塊接合(例如如第4圖所示)、或其相似的接合方式。接合線58的直徑約介於0.5密爾(mil)與2.0密爾之間。
在多個不同的實施例中，保護層52可具有多種形狀(form)。請參照第1圖，保護層52係形成於接墊50的整個頂表面之上，且對齊接墊50的整個頂表面。在另外的實施例中，如第2圖所示，保護層52係形成於鈍化層48的開口53中，且未延伸到鈍化層48之下。在其他多個實施例中，如第3圖所示，保護層52形成於接墊50的整個頂表面之上，且對齊接墊50的整個頂表面，且可更延伸至 接墊50的側壁上。在這些實施例中，保護層52延伸到部分的鈍化層48之下並與該部分的鈍化層48重疊。
在多個實施例中，保護層52的硬度可大於接墊50的硬度，以利於將接合製程所產生的應力分散到較大的晶片面積上。當無保護層時，接墊50會傳遞較大的應力予其下方的結構，例如低k值介電層。因此，藉由使用本實施例，可有效提昇打線接合製程的良率。
在多個實施例中，一電子元件包括一基板、與一接墊位於該基板上。一保護層位於該接墊上。該保護層與該接墊的材質不同。一接合球配置於該保護層上。一接合線連接該接合球。
在其他實施例中，一半導體元件包括一半導體基板、一鋁銅接墊位於該半導體基板上、以及一第一與一第二鈍化層。第一鈍化層包括多個部分位於該鋁銅接墊的多個邊緣部分下。第二鈍化層包括多個部分位於該鋁銅接墊的該些邊緣部分上。一保護層位於該鋁銅接墊上並接觸該鋁銅接墊。該保護層包括一金層、與一鎳層位於該金層上。一接合球接合至該保護層。一接合線連接該接合球，其中該接合線電性連接至該鋁銅接墊。
在又一實施例中，一半導體元件包括一半導體基板、一鋁銅接墊位於該半導體基板上、以及一第一與一第二鈍化層。第一鈍化層包括多個部分位於該鋁銅接墊的多個邊緣部分下。第二鈍化層包括多個部分位於該鋁銅接墊的該些邊緣部分上。一保護層位於該鋁銅接墊上。保護層的硬度大於該鋁銅接墊的硬度。一接合球接合至該保護層上。 一接合線連接至該接合球。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧基板
22‧‧‧主動電路
24‧‧‧區域
30‧‧‧內連線結構
32‧‧‧介電層
34‧‧‧金屬線
36‧‧‧導孔
38‧‧‧金屬墊、Mtop-1接墊
40‧‧‧Mtop接墊、金屬墊
42‧‧‧導孔
44‧‧‧雙層的實心接墊
46、48‧‧‧鈍化層
50‧‧‧接墊
52‧‧‧保護層
52A‧‧‧金層
52B‧‧‧鎳層
53‧‧‧開口
56‧‧‧接合球
58‧‧‧接合線
100‧‧‧晶片
第1圖繪示本發明多個示範性的實施例之一晶片的剖面圖，其中晶片包括一打線接合結構，其包括一接墊與一位於接墊上的保護層。
第2圖至第4圖繪示本發明多個實施例之多個晶片的剖面圖。
20‧‧‧基板
22‧‧‧主動電路
24‧‧‧區域
30‧‧‧內連線結構
32‧‧‧介電層
34‧‧‧金屬線
36‧‧‧導孔
38‧‧‧金屬墊、Mtop-1接墊
40‧‧‧Mtop接墊、金屬墊
42‧‧‧導孔
44‧‧‧雙層的實心接墊
46、48‧‧‧鈍化層
50‧‧‧接墊
52‧‧‧保護層
52A‧‧‧金層
52B‧‧‧鎳層
53‧‧‧開口
56‧‧‧接合球
58‧‧‧接合線
100‧‧‧晶片

Claims (5)

  1. 一種電子元件，包括：一基板；一接墊，位於該基板上；一保護層，位於該接墊上，其中該保護層與該接墊包括不同的材質；一第一鈍化層，包括一位於部分該接墊下的部分；一第二鈍化層，位於該第一鈍化層上，其中該第二鈍化層覆蓋該接墊的邊緣部分，及其中該接墊的邊緣部分完全地延伸覆蓋至與其鄰接之第一鈍化層的上表面，其中該保護層覆蓋該接墊之整體，並延伸至該第二鈍化層的一部分之下，且對齊該第二鈍化層的該部分，該保護層更延伸至該接墊的側壁上；一接合球，配置於該保護層上；以及一接合線，連接該接合球。
  2. 如申請專利範圍第1項所述之電子元件，其中該接墊的材質包括鋁、與銅，且該保護層包括一金層、以及一位於該金層上的鎳層，其中該接合球接觸該鎳層，該金層接觸該接墊。
  3. 一種半導體元件，包括：一半導體基板；一接墊，包括鋁與銅，且位於該半導體基板上；一第一鈍化層，包括多個部分位於該接墊的多個邊緣部分下，其中該接墊的邊緣部分完全地延伸覆蓋至與其鄰接之第一鈍化層的上表面； 一第二鈍化層，包括多個部分位於該接墊的該些邊緣部分上；一保護層，位於該接墊上並接觸該接墊，其中該保護層包括一金層、與一鎳層位於該金層上，該保護層更包括一鈀層位於該金層與該鎳層之間；一接合球，接合至該保護層；以及一接合線，連接該接合球，其中該接合線電性連接至該接墊。
  4. 如申請專利範圍第3項所述之半導體元件，更包括：一雙層的實心接墊，位於該接墊下且對齊該接墊。
  5. 一種半導體元件，包括：一半導體基板；一接墊，包括鋁與銅，且位於該半導體基板上；一第一鈍化層，包括多個部分位於該接墊的多個邊緣部分下，其中該接墊的邊緣部分完全地延伸覆蓋至與其鄰接之第一鈍化層的上表面；一第二鈍化層，包括多個部分位於該接墊的該些邊緣部分上；一保護層，位於該接墊上，其中該保護層的硬度大於該接墊的硬度，其中該保護層覆蓋該接墊之整體，並延伸至該第二鈍化層的一部分之下，且對齊該第二鈍化層的該部分，該保護層更延伸至該接墊的側壁上；一接合球，接合至該保護層上；以及一接合線，連接至該接合球。
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