TWI416693B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI416693B
TWI416693B TW99105432A TW99105432A TWI416693B TW I416693 B TWI416693 B TW I416693B TW 99105432 A TW99105432 A TW 99105432A TW 99105432 A TW99105432 A TW 99105432A TW I416693 B TWI416693 B TW I416693B
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Taiwan
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substrate
conductive
semiconductor device
layer
tsv
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TW99105432A
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TW201034157A (en
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Oscar M K Law
Kuo-Chu Wu
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Taiwan Semiconductor Mfg
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Description

半導體裝置及其製造方法
本發明係有關於一種系統及方法以連接半導體裝置，特別有關於一種系統及方法藉由使用先導孔製程的穿矽導孔(via-first TSV)及後導孔製程的穿矽導孔(via-last TSV)已連接晶片於系統級封裝(System-in-Package，簡稱SiP)構造中。
大體上，穿矽導孔(through-silicon via，簡稱TSV)已用於形成電性連接於系統級封裝(SiP)構造中，以連接多重半導體晶片穿透半導體晶片基板。一種形成所述穿矽導孔(TSV)的方法被稱為先導孔(via-first)製程，在形成半導體晶片的金屬化層之前，先形成穿矽導孔(TSV)穿透該基板，並且該穿矽導孔電性連接至靠近該基板的一金屬化層。然而，為維持一低電阻的路徑至該基板上的主動元件，此一連接事實上卻增加任何饋孔(feedthrough)連接(亦即提供電力至另一晶片)，其必須亦包括該些金屬化層的電阻，藉由這些金屬化層電力必須傳至該晶片的另一面。
為了降低此饋孔(feedthrough)電阻，可使用另一方法被稱為後導孔(via-last)製程。於此方法中，該些金屬化層先形成於該基板之上，然後形成穿矽導孔(TSV)延伸穿透該基板和該些金屬化層。此方法能允許一直線路徑穿透該晶片，從該些金屬化層而並無增加額外的電阻。然而，為降低電阻從晶片的一面至另一面(以及至另一晶粒)，此一穿矽導孔(TSV)亦增加至主動元件位於該晶片上的電阻，由於任一電力訊號必須沿著此後導孔(via-last)製程的TSV傳遞穿越該半導體晶片，並且接著傳遞回來穿越該些金屬化層已抵達該主動元件。
有鑑於此，業界亟需一種系統及方法，能降低饋孔(feedthrough)電阻而不會增加連接至主動元件的連線電阻。
上述所揭露及其他的問題可藉由本發明實施例而獲得解決及避免，並且能達成技術上的優點，本發明實施例提供於系統級封裝中具有穿矽導孔(TSV)的一混成結構。
根據本發明之一實施例，一種半導體裝置包括一基板具有一第一面和對向於第一面的一第二面以及一第一導電區域位於該基板的第一面上。一第一導電孔自該基板的第二面延伸至該第一導電區域，而未延伸穿越該第一導電區域；以及一第二導電孔自該基板的第二面延伸穿越該導電區域。
根據本發明另一實施例，一種半導體裝置包括一第一半導體晶片包括一第一基板以及一第一金屬化區域，該第一基板包括一第一面和一第二面。一第一導電孔自該第一基板的第二面延伸至該第一基板的第一面並且終止於該第一金屬化區域。一第二導電孔延伸穿越該第一半導體晶片。
根據本發明又一實施例，一種半導體裝置的製造方法包括提供一第一基板及形成一第一導電孔穿越該第一基板。一第一導電區域形成於該第一基板之上，以及形成一第二導電孔延伸穿越該第一基板與該第一導電區域。
本發明所述實施例的優點為，其提供一低電阻路徑藉由一先導孔製程的穿矽導孔(via-first TSV)以供相鄰晶片連線，而亦提供一饋孔(feedthrough)通道，藉由一後導孔製程的穿矽導孔(via-last TSV)以供多重晶片之間的連線。藉由提供不同的穿矽導孔(TSV)精確地視實際TSV的使用而定，能降低整體的連線電阻。
為使本發明能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下：
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式，另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
本發明的實施例以特定的內容所揭露，亦即以三維系統級封裝(SiP)構造為例，其具有先導孔製程的穿矽導孔(via-first TSV)及後導孔製程的穿矽導孔(via-last TSV)的混成結構。然而，本發明亦可應用於其他形式的電性連接。
請參閱第1圖，其顯示一基板101具有主動元件102和一層間介電層(interlayer dielectric，簡稱ILD)104。該基板具有一第一面105和對向於第一面105的一第二面107以及一先導孔製程的穿矽導孔(via-first TSV)103形成於其中。該基板可包括矽塊材、摻雜或未摻雜、或一主動層於絕緣層上有矽(Silicon-on-insulator，簡稱SOI)基板。一般而言，一SOI基板包括一半導體材料層，例如矽、鍺、矽鍺、SOI、絕緣層上有矽鍺(SGOI)、或上述材料的組合。可使用的其他基板包括多層基板、漸層基板、或混合位向基板。
於第1圖中所顯示的主動元件102為兩電晶體。然而，本發明所屬技術領域中具有通常知識者應可理解廣泛的各種類型的元件例如電容、電阻、電感、high-k金屬閘極元件、以及其他等同類型的元件，可用以產生所欲的結構上及功能上的設計需求。所述主動元件102可利用適當的方法形成於該基板101的表面上或形成於該基板101中。
該層間介電層104形成於基板101和主動元件102上，藉由化學氣相沉積法、濺鍍法、或其他任何已知及已使用於本技術領域中用以形成ILD 104的方法。典型的層間介電層104具有一平坦化的表面，以及可包括氧化矽，然而亦可選用其他材料，例如high-K或low-k材料。該層間介電層104可選擇地形成以致施予一應變於主動元件102內的基板101，如同本技術領域所周知，此將可增加主動元件102的整體效能。
可形成一先導孔製程的穿矽導孔(via-first TSV)103，藉由先將一適合的光阻(未顯示)進行塗佈並顯影步驟，接著蝕刻該層間介電層104與基板101以形成一開口。於此階段所形成的開口需延伸進入該基板101，至少甚於該主動元件102，並且抵達一深度至少大於最終所欲完成的基板101的厚度。而此深度為依賴該基板101的整體設計而定，因此，此深度可自該基板101的表面深入大約1微米(μm)至大約700微米之間，例如大約50微米。所形成的該開口具有一直徑大約介於1微米至100微米之間，例如大約6微米。
一旦已形成此開口，可將該開口填入一阻障層及一導電材料以形成先導孔製程的穿矽導孔(via-first TSV)103。該阻障層可包括一導電材料，例如氮化鈦，雖然亦可替換使用其他材料，例如氮化鉭、鈦、介電材料、或類似材料。該阻障層可藉由使用一化學氣相沉積法(CVD)形成，例如電漿輔助化學氣相沉積法(PECVD)。然而，亦可選擇使用其他可替代的方法，例如濺鍍法或有機金屬化學氣相沉積法(MOCVD)。該阻障層可形成以順應下方的開口的形狀，該開口用於先導孔製程的穿矽導孔(via-first TSV)103。
該導電材料可包括銅，雖然亦可替代其他適合的材料，例如鋁、合金、摻雜多晶矽、上述材料的組合、或其他類似的材料。形成該該導電材料可藉由先沉積一晶種層，接著電鍍銅於該晶種層上，填入且溢滿該開口，其用於先導孔製程的穿矽導孔(via-first TSV)103。一旦導電材料已填入用於先導孔製程的穿矽導孔(via-first TSV)103的開口中，在用於先導孔製程的穿矽導孔(via-first TSV)103的開口外部多餘的阻障層和多餘的導電層，透過一研磨製程被移除，例如化學機械研磨法(CMP)，雖然亦可使用其他適合的移除製程。
第2圖顯示形成金屬化層201於該層間介電層104、該基板101和先導孔製程的穿矽導孔(via-first TSV)103的剖面示意圖。該些金屬化層201形成於該基板101、主動元件102、層間介電層104、和先導孔製程的穿矽導孔103之上，並且設計以連接各種不同的主動元件102以形成功能性電路。形成該些金屬化層201是以介電材料和導電材料的交錯疊層形式，並且可利用任何適當的製程(例如沉積、鑲嵌、雙鑲嵌等)。於一實施例中，至少有四層金屬化層分別由ILD層104與基板101隔離，然而，金屬化層201確實數目至少部分依據該半導體晶片的整體設計而定。
將接觸墊203形成於該些金屬化層201的最上層中，以提供自電路(包括主動元件102和金屬化層201)至其他裝置(例如其他半導體晶片，如以下第5圖所述)的連接。該些接觸墊203可包括鋁，並且可藉由順應性地沉積一鋁層，以致接觸從該些金屬化層201的低層的一連線。
第3圖顯示根據本發明實施例之形成後導孔製程的穿矽導孔(via-last TSV)的剖面示意圖。該後導孔製程的穿矽導孔(via-last TSV)301可藉由塗佈及顯影一適合的光阻(未繪示)，接著蝕刻該些金屬化層201、該些ILD層104和至少一部分的基板101而形成。該後導孔製程的穿矽導孔(via-last TSV)301的形成步驟，相似於先導孔製程的穿矽導孔(via-first TSV)103的形成步驟，使導孔延伸進入該基板101中至少超過該主動元件102，以至一深度大於所欲的該基板的最終高度。有鑑於此，而此深度為依賴該基板101的整體設計而定，因此，此深度可自該基板101的表面深入大約1微米(μm)至大約700微米之間，例如大約50微米。所形成的該開口具有一直徑大約介於1微米至100微米之間，例如大約6微米。
可選擇地，亦可形成後導孔製程的接觸墊(未繪示)於該後導孔製程的穿矽導孔(via-last TSV)301上，以提供一外部連接至其他裝置。該些後導孔製程的接觸墊可藉由與接觸墊203相類似的形式和相似的材料形成，如以上第2圖中所描述。然而，其他任何適當的材料及方法以可用以替換形成該些後導孔製程的接觸墊。
第4圖係顯示將該基板101薄化以露出該先導孔製程的穿矽導孔(via-first TSV)103和後導孔製程的穿矽導孔(via-last TSV)301，而形成via-first TSV 401和via-last TSV 403。為了薄化該基板101，將該基板101的第二面107的部分移除，以露出位於先導孔製程的穿矽導孔103和後導孔製程的穿矽導孔301內的導電材料。此移除步驟可藉由一研磨製程實施，例如一化學機械研磨(CMP)，雖然，亦可選擇使用其他適合的替代方法，例如蝕刻法。
然而，做為本發明所屬技術領域中具有通常知識者應可瞭解的是，上述形成via-first TSV 401和via-last TSV 403的方法僅僅是用以說明的實施例，並非限定於這些實施例。亦可選擇使用其他適合的替代方法。例如，用於先導孔製程的穿矽導孔(via-first TSV)103和後導孔製程的穿矽導孔(via-last TSV)301可填入介電材料，直至該基板101的第二面107薄化完成後，於此階段可將介電材料移除並且取代以導電材料。此實施例以及其他適合的實施例可替代以用於形成via-first TSV 401和via-last TSV 403。
在移除部分的該基板101的第二面107之後，可實施一清洗蝕刻步驟。此清洗蝕刻步驟意欲清洗並拋光於CMP步驟之後的該基板101。此外，此清洗蝕刻步驟亦可幫助應力釋放，此應力是在CMP製程時研磨基板101生成。此清洗蝕刻步驟可使用HNO3 ，然而亦可選擇使用其他適合的替代蝕刻液。
再者，在清洗步驟以移除任何殘留的研磨殘留物，例如氧化銅之後，可形成一導電層405於該基板101的第二面107上形成一電性連接至該via-first TSV 401和via-last TSV 403。該導電層405可包括鋁，並且可藉由一濺鍍沉積製程形成。然而，亦可替代使用其他材料，例如鎳和銅，以及其他形成方法，例如電鍍法或無電鍍法。所形成的該導電層405的厚度範圍可介於大約1微米(μm)至大約3微米之間，例如大約2微米。
在形成導電層405之後可接續一無電鍍鎳金(Electroless Nickel Gold，簡稱ENIG)製程以形成一無電鍍鎳金層407，從該基板101相對於該導電層405。該ENIG製程提供一均勻的金屬表面，供形成接觸從該基板101至其他裝置(詳細描述於以下第5圖中)。該ENIG製程可包括清潔該導電層405，浸潤該基板101於一鋅酸鹽活化溶液中，無電鍍一鎳層於該導電層405上，無電鍍一金層於該鎳層上。所形成的該ENIG層407的厚度範圍可介於大約2微米至大約4微米之間，例如大約3微米。一旦形成，可將該導電層405和該ENIG層407圖案化，藉由一適當的黃光微影製程，並且移除不想要的材料透過適當的蝕刻步驟如第4圖所示。
應注意的是，上述導電層405和ENIG層407僅僅是一具潛力的製程，可用於薄化的該基板101的第二面107。另擇一地，可將該基板101的第二面107形成一凹入，使得該via-first TSV 401和via-last TSV 403自該基板101的第二面107的表面延伸遠離。另外，可形成一保護層以保護該via-first TSV 401和via-last TSV 403，或者形成重置層或者其他型式的適當的連線，替代地形成於該基板101的第二面107上。
第5圖係顯示本發明之一實施例，藉由使用上述對應第1~4圖的製程所形成的第一晶片501，與一封裝基板503、一第二晶片505和第三晶片507積體化至一SiP構造中。該封裝基板503提供一輸出/輸入(簡稱I/O)、電力及透過接觸凸塊509將該via-first TSV 401和via-last TSV 403連接接地。該封裝基板503可以是印刷電路板(簡稱PCB)、IC封裝、或者其他基板，其可用於封裝具傳輸訊號、電力及將該第一晶片501、第二晶片505和第三晶片507接地。
所述接觸凸塊509可包括一材料，例如錫，或其他適合的材料例如銀、無鉛錫、或銅。於一實施例中，該接觸凸塊509為焊錫凸塊。該接觸凸塊509的形成方式最初是以形成一錫層，透過常用的方法例如蒸鍍法、電鍍法、印刷法、銲錫轉移法、錫球置入法(ball placement)等，直至一厚度大約100微米。一旦一錫層已形成於所述結構上，施以一迴焊步驟以將該材料定型成為所欲的凸塊形狀。
該第二晶片505和第三晶片507以可藉由相似於第一晶片501的方法形成，如上述對應第1~4圖所述。例如，於此實施例中該第二晶片505和第三晶片507皆包括via-first TSV 401、via-last TSV 403和接觸墊203。再者，該via-first TSV 401和via-last TSV 403的確切數目、設置及位置必須至少部分地依據該SiP的整體設計而定，將該via-first TSV 401設置以提供連接至一接觸墊203(如第一圈區域511所圖示)或者一鄰近晶片的via-last TSV 403(如第二圈區域513所圖示)。另外，將該via-last TSV 403設置以提供連接至一接觸墊203(如第三圈區域515所圖示)或者一鄰近晶片的via-last TSV 403(如第四圈區域517所圖示)。
然而，如本發明所屬技術領域中具有通常知識者應可瞭解的是，仍有許多結合可用於連線任意數目適合的晶片，並且上述實施例並非意欲限定本發明。亦可使用任何適當的晶片的結合(具有任意數目的via-first TSV 401和via-last TSV 403提供電力和訊號路徑，此數目亦包括零)，仍不脫離本發明之精神和範圍，以及所有的這些結合完全涵括於本發明的範圍內。此外，可形成或設置重置層(redistribution layer)和插入件(interposer，未繪示)，以確保該第一晶片501、第二晶片505和第三晶片507之間的連接(例如導電層405和ENIG層407)具適當的對準。
藉由使用via-first TSV 401和via-last TSV 403的結合，可兼具有via-first TSV 401和via-last TSV 403的優點，以提供一低電阻路徑供相鄰晶片連接通過一via-first TSV 401，而亦提供一饋孔(feedthrough)通道，藉由一via-last TSV 403以供多重晶片之間的連線。藉由提供不同的穿矽導孔(TSV)精確地視實際TSV的使用而定，能降低整體的連線電阻。
例如，在一系統級封裝(SiP)的第三晶片507內，如第5圖中所示包括via-first TSV 401和via-last TSV 403二者，自該封裝基板503至該些主動元件102之一的連線路徑的電阻，可藉由以下公式1計算得：
連線電阻=R’+(n-1)R”　(式1)
其中：n為晶片的數目；R為各晶片中金屬化層的電阻；R’為各晶片中via-first TSV的電阻；R”為各晶片中via-last TSV的電阻。
易言之，於第三晶片507上的主動元件102之一的電阻路徑為第三晶片507內的via-first TSV 401的電阻及兩個via-last TSV 403的電阻總和，此via-last TSV 403為延伸穿透第一晶片501和第二晶片505。
相較於標準的先前技術，其僅透過via-first TSV 401或via-last TSV 403之一，提供連線至位於第三晶片507上的該些主動元件102之一，上述實施例針對三維系統級封裝(3D SiP)構造提供了更有效地成本解決方案。於僅僅具有via-first TSV 401的案例中，為達到位於第三晶片507上的主動元件102，該電阻路徑可包括該第一晶片501的via-first TSV 401、該第一晶片501的金屬化層201、該第二晶片505的via-first TSV 401、該第二晶片505的金屬化層201、和該第三晶片507的via-first TSV 401的電阻，總結於公式2中：
Via-First TSV電阻=(n+1)R+nR’　(式2)
於僅僅具有via-last TSV 403的案例中，為達到位於第三晶片507上的主動元件102之一，該電阻路徑可包括透過各個第一晶片501的via-last TSV 403的電阻，及該第三晶片507的金屬化層201的電阻總和，總結於公式3中：
Via-Last TSV電阻=R+nR”　(式3)
雖然本發明及其優點已於上述實施例中詳細揭露，應瞭解的是可進行各種變化、取代或替換而不脫離本發明所主張請求保護專利之精神和範圍。例如，各種不同via-first TSV和via-last TSV的結合應可用於將分離的晶片連接在一起。於另一例中，任何數目的方法皆可替換地使用於形成via-first TSV 401和via-last TSV。
本發明雖以各種實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾。本發明之保護範圍當視後附之申請專利範圍所界定者為準。
101．．．基板
102．．．主動元件
103．．．先導孔製程的穿矽導孔(via-first TSV)
104．．．層間介電層
105．．．基板的第一面
107．．．基板的第二面
201．．．金屬化層
203．．．接觸墊
301．．．後導孔製程的穿矽導孔(via-last TSV)
401．．．via-first TSV
403．．．via-last TSV
405．．．導電層
407．．．ENIG層
501．．．第一晶片
503．．．封裝基板
505．．．第二晶片
507．．．第三晶片
509．．．接觸凸塊
511、513、515、517．．．圈出區域
第1圖顯示根據本發明之實施例於形成先導孔製程的穿矽導孔(via-first TSV)的初始步驟的剖面示意圖。
第2圖顯示根據本發明之實施例在形成金屬化層於該層間介電層、該基板和先導孔製程的穿矽導孔(via-first TSV)的剖面示意圖。
第3圖顯示根據本發明之實施例在形成後導孔製程的穿矽導孔(via-last TSV)的剖面示意圖。
第4圖顯示根據本發明之實施例將該基板薄化以露出該先導孔製程的穿矽導孔(via-first TSV)103和後導孔製程的穿矽導孔(via-last TSV)301，而形成via-first TSV 401和via-last TSV 403的剖面示意圖。
第5圖顯示根據本發明之一實施例，藉由使用上述對應第1~4圖的製程所形成的第一晶片501，與一封裝基板503、一第二晶片505和第三晶片507積體化至系統級封裝(SiP)構造的剖面示意圖。
101．．．基板
102．．．主動元件
104．．．層間介電層
201．．．金屬化層
203．．．接觸墊
401．．．via-first TSV
403．．．via-last TSV
405．．．導電層
407．．．ENIG層
501．．．第一晶片
503．．．封裝基板
505．．．第二晶片
507．．．第三晶片
509．．．接觸凸塊
511、513、515、517．．．圈出區域

Claims (20)

  1. 一種半導體裝置，包括：一第一基板；一第一複數介電層；一第一導孔延伸穿越該第一基板及一或多層該第一複數介電層；以及一第二導孔延伸穿越該第一基板及一或多層該第一複數介電層，該第二導孔所穿越該第一複數介電層的層數多於該第一導孔所穿越該第一複數介電層的層數。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第一導孔僅穿越該第一複數介電層的其中一層。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括：一主動元件位於該第一基板上；以及複數個金屬化層設置於該主動元件之上，其中最接近該第一基板的一第一金屬化層電性連接該第一導孔與該主動元件。
  4. 如申請專利範圍第3項所述之半導體裝置，更包括一導電層相對於該主動元件位於該第一基板相對側，該導電層與該第一導孔電性連接。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該第二導孔延伸穿越該第一複數介電層的每一層。
  6. 如申請專利範圍第1項所述之半導體裝置，更包括：一第二基板；一第二複數介電層；一第三導孔延伸穿越該第二基板及一或多層該第二複數介電層；以及一第四導孔延伸穿越該第二基板及一或多層該第二複數介電層，該第四導孔所穿越該第二複數介電層的層數多於該第三導孔所穿越該第二複數介電層的層數，其中該第四導孔電性連接至該第二導孔。
  7. 如申請專利範圍第6項所述之半導體裝置，其中該第三導孔電性連接至該第一導孔，此乃藉由位於該第一複數個介電層中的金屬化層連接。
  8. 一種半導體裝置，包括：一第一半導體晶片包括一第一基板；一第一導電孔延伸穿越該半導體晶片；以及一第二導電孔延伸部分地穿越該第一半導體晶片，該第二導電孔延伸穿越該第一基板。
  9. 如申請專利範圍第8項所述之半導體裝置，更包括複數個介電層位於該第一基板之上，其中該第二導電孔延伸穿越一單一的介電層位在鄰近於該第一基板。
  10. 如申請專利範圍第8項所述之半導體裝置，更包括一主動元件位於該第一基板上，其中該主動元件透過一金屬化層與該第二導電孔電性連接。
  11. 如申請專利範圍第10項所述之半導體裝置，其中該第一導電孔是由介電材料所環繞穿透該半導體晶片。
  12. 如申請專利範圍第8項所述之半導體裝置，更包括：一第二半導體晶片包括一第二基板；一第三導電孔延伸穿越該半導體晶片，其中該第三導電孔電性連接至該第二導電孔；以及一第四導電孔延伸穿越該第二半導體晶片的程度較少於該第四導電孔延伸穿越該第二基板的程度。
  13. 如申請專利範圍第12項所述之半導體裝置，其中該第三導電孔電性連接至該第二導電孔，此乃藉由位於該第一半導體晶片中的該基板上的金屬化層連接。
  14. 一種半導體裝置的製造方法，包括：提供一第一基板；形成一或多層第一介電層於該第一基板之上；形成一第一導電孔延伸穿越該第一基板及該一或多層第一介電層；形成複數層第二介電層於該一或多層第一介電層和該第一基板之上；以及形成一第二導電孔延伸穿越該第一基板、該一或多層第一介電層、及該複數層第二介電層。
  15. 如申請專利範圍第14項所述之半導體裝置的製造方法，更包括：形成一主動元件位於該第一基板上；以及形成一第一金屬化層於該主動元件之上，該第一金屬化層電性連接該第一導電孔與該主動元件。
  16. 如申請專利範圍第15項所述之半導體裝置的製造方法，更包括形成一導電層於該第一基板上，相對於一或多層第一介電層的相對側，該導電層與該第一導電孔電性連接。
  17. 如申請專利範圍第14項所述之半導體裝置的製造方法，更包括形成複數導電互連線於該第一導電孔上，且位於該複數第二介電層上。
  18. 如申請專利範圍第14項所述之半導體裝置的製造方法，其中所述形成該第一導電孔的步驟更包括：形成一開口於該基底的一第一面上；將一導電材料填入該開口中；以及薄化該基板的一第二面，相對於該第一面，以露出該導電材料。
  19. 如申請專利範圍第14項所述之半導體裝置的製造方法，更包括將一第三導電孔連接至該第二導電孔，該第三導電孔延伸穿透一第二基板。
  20. 如申請專利範圍第19項所述之半導體裝置的製造方法，更包括形成金屬化層於該第二基板之上，將該第三導電孔電性連接至位於該第二基板上的一主動元件。
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Families Citing this family (262)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064717B2 (en) * 2008-09-26 2015-06-23 International Business Machines Corporation Lock and key through-via method for wafer level 3D integration and structures produced thereby
US8749027B2 (en) * 2009-01-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Robust TSV structure
US8487444B2 (en) 2009-03-06 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional system-in-package architecture
US8531015B2 (en) * 2009-03-26 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a thin wafer without a carrier
US7964916B2 (en) * 2009-04-14 2011-06-21 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US8669778B1 (en) * 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8367470B2 (en) * 2009-08-07 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in build-up interconnect structure for short signal path between die
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US12027518B1 (en) 2009-10-12 2024-07-02 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US9892972B2 (en) * 2009-10-12 2018-02-13 Monolithic 3D Inc. 3D semiconductor device and structure
US9999129B2 (en) * 2009-11-12 2018-06-12 Intel Corporation Microelectronic device and method of manufacturing same
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8143712B2 (en) * 2010-07-15 2012-03-27 Nanya Technology Corp. Die package structure
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
KR20120012602A (ko) * 2010-08-02 2012-02-10 삼성전자주식회사 반도체 장치, 그 제조 방법 및 반도체 패키지의 제조 방법
KR101190682B1 (ko) 2010-09-30 2012-10-12 에스케이하이닉스 주식회사 3차원 적층 반도체 집적회로
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US12094892B2 (en) 2010-10-13 2024-09-17 Monolithic 3D Inc. 3D micro display device and structure
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US12080743B2 (en) 2010-10-13 2024-09-03 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
KR101690487B1 (ko) * 2010-11-08 2016-12-28 삼성전자주식회사 반도체 장치 및 제조 방법
US12100611B2 (en) 2010-11-18 2024-09-24 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US12033884B2 (en) 2010-11-18 2024-07-09 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US12068187B2 (en) 2010-11-18 2024-08-20 Monolithic 3D Inc. 3D semiconductor device and structure with bonding and DRAM memory cells
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
FR2969592B1 (fr) * 2010-12-23 2013-02-08 Commissariat Energie Atomique Dispositif pour connecter des nano-objets a des systèmes électriques externes, et procédé de fabrication du dispositif
KR101209458B1 (ko) 2010-12-24 2012-12-07 한국과학기술원 반도체 칩, 이의 제조 방법 및 이를 포함하는 반도체 모듈
CN102543729B (zh) 2010-12-31 2014-03-12 中芯国际集成电路制造(上海)有限公司 电容的形成方法及其电容结构
JP5574539B2 (ja) * 2011-02-15 2014-08-20 ルネサスエレクトロニクス株式会社 半導体装置及び電子装置
EP2684213A4 (en) 2011-03-11 2014-11-26 Basf Se METHOD FOR PRODUCING BASIC CONTACT HOLES FOR WAFER
TWI467695B (zh) * 2011-03-24 2015-01-01 Sony Corp 半導體裝置及其製造方法
JP2012221998A (ja) 2011-04-04 2012-11-12 Toshiba Corp 半導体装置ならびにその製造方法
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US8617925B2 (en) * 2011-08-09 2013-12-31 Soitec Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
WO2013057886A1 (ja) * 2011-10-17 2013-04-25 パナソニック株式会社 集積回路、マルチコアプロセッサ装置及び集積回路の製造方法
WO2013062593A1 (en) 2011-10-28 2013-05-02 Intel Corporation 3d interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
CN103890940B (zh) * 2011-10-28 2017-03-01 英特尔公司 包括结合使用双镶嵌型方案制造的微细间距背侧金属再分布线的穿硅过孔的3d互连结构
US9362267B2 (en) * 2012-03-15 2016-06-07 Infineon Technologies Americas Corp. Group III-V and group IV composite switch
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US9443783B2 (en) * 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9190346B2 (en) 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
KR101419601B1 (ko) * 2012-11-20 2014-07-16 앰코 테크놀로지 코리아 주식회사 Emc 웨이퍼 서포트 시스템을 이용한 반도체 디바이스 및 이의 제조방법
US8933564B2 (en) 2012-12-21 2015-01-13 Intel Corporation Landing structure for through-silicon via
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US12051674B2 (en) 2012-12-22 2024-07-30 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
CN103165561B (zh) * 2013-02-28 2015-09-23 江阴长电先进封装有限公司 一种硅基转接板的封装结构
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US12094965B2 (en) 2013-03-11 2024-09-17 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US12100646B2 (en) 2013-03-12 2024-09-24 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
KR102077153B1 (ko) 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
DE112013002916T5 (de) * 2013-06-27 2015-03-05 Intel IP Corporation Hochleitende, hochfrequente Durchkontaktierung für elektronische Anlagen
WO2015042700A1 (en) 2013-09-24 2015-04-02 Motion Engine Inc. Mems components and method of wafer-level manufacturing thereof
JP6339669B2 (ja) 2013-07-08 2018-06-06 モーション・エンジン・インコーポレーテッド Ｍｅｍｓデバイスおよび製造する方法
KR102151177B1 (ko) 2013-07-25 2020-09-02 삼성전자 주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
EP3028007A4 (en) 2013-08-02 2017-07-12 Motion Engine Inc. Mems motion sensor and method of manufacturing
JP2015076502A (ja) 2013-10-09 2015-04-20 ソニー株式会社 半導体装置およびその製造方法、並びに電子機器
KR102094473B1 (ko) 2013-10-15 2020-03-27 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
US9443758B2 (en) * 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
US9543229B2 (en) * 2013-12-27 2017-01-10 International Business Machines Corporation Combination of TSV and back side wiring in 3D integration
JP6590812B2 (ja) 2014-01-09 2019-10-16 モーション・エンジン・インコーポレーテッド 集積ｍｅｍｓシステム
US9252105B2 (en) * 2014-01-15 2016-02-02 Nanya Technology Corporation Chip package
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US12094829B2 (en) 2014-01-28 2024-09-17 Monolithic 3D Inc. 3D semiconductor device and structure
WO2015154173A1 (en) 2014-04-10 2015-10-15 Motion Engine Inc. Mems pressure sensor
US9786633B2 (en) 2014-04-23 2017-10-10 Massachusetts Institute Of Technology Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
WO2015184531A1 (en) 2014-06-02 2015-12-10 Motion Engine Inc. Multi-mass mems motion sensor
US9449914B2 (en) * 2014-07-17 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
WO2016025478A1 (en) 2014-08-11 2016-02-18 Massachusetts Institute Of Technology Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure
KR20170066321A (ko) * 2014-09-26 2017-06-14 인텔 코포레이션 후방측 수동 컴포넌트들을 가지는 집적 회로 다이 및 이와 연관된 방법들
WO2016118209A2 (en) 2014-11-05 2016-07-28 Massachusetts Institute Of Technology Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques
KR102264548B1 (ko) 2014-11-21 2021-06-16 삼성전자주식회사 반도체 패키지 및 그 제조 방법
CA3004760A1 (en) 2014-12-09 2016-06-16 Motion Engine Inc. 3d mems magnetometer and associated methods
US11056463B2 (en) * 2014-12-18 2021-07-06 Sony Corporation Arrangement of penetrating electrode interconnections
CA3220839A1 (en) 2015-01-15 2016-07-21 Motion Engine Inc. 3d mems device with hermetic cavity
US9397073B1 (en) * 2015-03-23 2016-07-19 Globalfoundries Inc. Method of using a back-end-of-line connection structure to distribute current envenly among multiple TSVs in a series for delivery to a top die
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US10068181B1 (en) 2015-04-27 2018-09-04 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafer and methods for making the same
US10134972B2 (en) 2015-07-23 2018-11-20 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
US10658424B2 (en) 2015-07-23 2020-05-19 Massachusetts Institute Of Technology Superconducting integrated circuit
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US12100658B2 (en) 2015-09-21 2024-09-24 Monolithic 3D Inc. Method to produce a 3D multilayer semiconductor device and structure
DE112016004265T5 (de) 2015-09-21 2018-06-07 Monolithic 3D Inc. 3d halbleitervorrichtung und -struktur
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
CN108028241B (zh) * 2015-09-25 2022-11-04 英特尔公司 通过硅来分配功率的两侧上的金属
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US12035531B2 (en) 2015-10-24 2024-07-09 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US12120880B1 (en) 2015-10-24 2024-10-15 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US12016181B2 (en) 2015-10-24 2024-06-18 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US10242968B2 (en) 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
WO2017079417A1 (en) 2015-11-05 2017-05-11 Massachusetts Institute Of Technology Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits
KR102473664B1 (ko) * 2016-01-19 2022-12-02 삼성전자주식회사 Tsv 구조체를 가진 다중 적층 소자
CN107039372B (zh) * 2016-02-04 2019-05-28 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
KR102487532B1 (ko) * 2016-04-28 2023-01-12 에스케이하이닉스 주식회사 반도체 칩 및 이를 이용한 적층 반도체 칩
US10163771B2 (en) * 2016-08-08 2018-12-25 Qualcomm Incorporated Interposer device including at least one transistor and at least one through-substrate via
WO2018056965A1 (en) * 2016-09-21 2018-03-29 Massachusetts Institute Of Technology Multi-layer semiconductor structure and methods for fabricating multi-layer semiconductor structures
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US10586909B2 (en) 2016-10-11 2020-03-10 Massachusetts Institute Of Technology Cryogenic electronic packages and assemblies
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
US11041211B2 (en) 2018-02-22 2021-06-22 Xilinx, Inc. Power distribution for active-on-active die stack with reduced resistance
US10515920B2 (en) * 2018-04-09 2019-12-24 Google Llc High bandwidth memory package for high performance processors
US10692799B2 (en) * 2018-06-01 2020-06-23 Innolux Corporation Semiconductor electronic device
US11543453B2 (en) * 2019-01-25 2023-01-03 Texas Instruments Incorporated In-wafer reliability testing
JP7150632B2 (ja) * 2019-02-13 2022-10-11 キオクシア株式会社 半導体装置の製造方法
US11094683B2 (en) * 2019-03-26 2021-08-17 International Business Machines Corporation Bonded nanofluidic device chip stacks
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
KR102605619B1 (ko) * 2019-07-17 2023-11-23 삼성전자주식회사 기판 관통 비아들을 포함하는 반도체 소자 및 그 제조 방법
KR20220016411A (ko) 2020-07-31 2022-02-09 삼성전자주식회사 반도체 소자
US11749629B2 (en) * 2020-12-10 2023-09-05 Advanced Micro Devices, Inc. High-speed die connections using a conductive insert
US11869874B2 (en) * 2020-12-14 2024-01-09 Advanced Micro Devices, Inc. Stacked die circuit routing system and method
US20220271033A1 (en) * 2021-02-19 2022-08-25 Daniel Chanemougame Inverted top-tier fet for multi-tier gate-on-gate 3-dimension integration (3di)
US20220293750A1 (en) * 2021-03-12 2022-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit including backside conductive vias
KR20220133013A (ko) * 2021-03-24 2022-10-04 삼성전자주식회사 관통 비아 구조물을 갖는 반도체 장치
US11705384B2 (en) * 2021-03-31 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through vias of semiconductor structure and method of forming thereof
KR20220143444A (ko) * 2021-04-16 2022-10-25 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지
US12001772B2 (en) 2021-09-24 2024-06-04 International Business Machines Corporation Ultra-short-height standard cell architecture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109236A1 (en) * 2001-02-09 2002-08-15 Samsung Electronics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
US20070080382A1 (en) * 2005-10-07 2007-04-12 Fujitsu Limited Semiconductor device
TW200901343A (en) * 2007-06-27 2009-01-01 Taiwan Semiconductor Mfg Stacked integrated circuit and semiconductor component

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
JPH05211239A (ja) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> 集積回路相互接続構造とそれを形成する方法
DE4314907C1 (de) 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP2002100727A (ja) * 2000-09-12 2002-04-05 Nokia Mobile Phones Ltd 半導体装置および電子装置
JP3870704B2 (ja) * 2001-03-14 2007-01-24 松下電器産業株式会社 半導体装置
US20020163072A1 (en) * 2001-05-01 2002-11-07 Subhash Gupta Method for bonding wafers to produce stacked integrated circuits
JP4408006B2 (ja) 2001-06-28 2010-02-03 富士通マイクロエレクトロニクス株式会社 半導体装置およびその製造方法
JP2003023067A (ja) 2001-07-09 2003-01-24 Tokyo Electron Ltd ビアメタル層の形成方法およびビアメタル層形成基板
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
EP1472730A4 (en) 2002-01-16 2010-04-14 Mann Alfred E Found Scient Res HOUSING FOR ELECTRONIC CIRCUITS WITH REDUCED SIZE
CN1227729C (zh) * 2002-02-05 2005-11-16 台湾积体电路制造股份有限公司 集成电路芯片的制造方法
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6800930B2 (en) 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4467318B2 (ja) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP2007250561A (ja) 2004-04-12 2007-09-27 Japan Science & Technology Agency 半導体素子および半導体システム
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
JP4869664B2 (ja) * 2005-08-26 2012-02-08 本田技研工業株式会社 半導体装置の製造方法
TWI285419B (en) * 2005-10-26 2007-08-11 Ind Tech Res Inst Wafer-to-wafer stacking with supporting pedestals
US7663232B2 (en) * 2006-03-07 2010-02-16 Micron Technology, Inc. Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
CN100517623C (zh) * 2006-12-05 2009-07-22 中芯国际集成电路制造(上海)有限公司 晶片压焊键合方法及其结构
US7893529B2 (en) * 2009-01-12 2011-02-22 International Business Machines Corporation Thermoelectric 3D cooling
US8487444B2 (en) 2009-03-06 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional system-in-package architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109236A1 (en) * 2001-02-09 2002-08-15 Samsung Electronics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
US20070080382A1 (en) * 2005-10-07 2007-04-12 Fujitsu Limited Semiconductor device
TW200901343A (en) * 2007-06-27 2009-01-01 Taiwan Semiconductor Mfg Stacked integrated circuit and semiconductor component

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