TWI413224B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI413224B
TWI413224B TW99110693A TW99110693A TWI413224B TW I413224 B TWI413224 B TW I413224B TW 99110693 A TW99110693 A TW 99110693A TW 99110693 A TW99110693 A TW 99110693A TW I413224 B TWI413224 B TW I413224B
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Taiwan
Prior art keywords
substrate
power
tsv
semiconductor device
ground
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TW99110693A
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English (en)
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TW201037806A (en
Inventor
Kuo H Wu
Oscar M K Law
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Taiwan Semiconductor Mfg
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Publication of TW201037806A publication Critical patent/TW201037806A/zh
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Publication of TWI413224B publication Critical patent/TWI413224B/zh

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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Description

半導體裝置及其製造方法
本發明係有關於一種系統及方法以連接半導體裝置，特別有關於一種系統及方法以提供連線至半導體晶片的背面。
接觸墊(contact pads)大體上是用於半導體裝置，以提供訊號、電源和接地連接至外部的裝置。在這些半導體裝置中，接觸墊通常是連接到位於主動元件上方的金屬化層。此金屬化層將所述訊號、電源和接地連接延伸路徑至所欲的位置，並且與各種主動元件相互連接，以形成功能性電路。
然而，因為增加接觸墊的數量所造成的延伸路徑擁擠的緣故，使得這些接觸墊典型地沿著裝置的週邊區域約束在一起，此作用限制了整個元件尺寸的任何縮減。更有甚者，隨著半導體裝置發展成更強效且更複雜，因而在該些金屬化層內部的延伸路徑的內連線亦已變得更複雜。此結果導致金屬化層的數量增加，並且因額外金屬化層所需高電阻導電孔而導致電阻及功率消耗的增加。此複雜性亦已導致兩最上層的金屬化層典型地幾乎完全被用於延伸路徑至電源和接地，此稱做金屬化層的電源網(power mesh of metallization layers)。
藉由要求將訊號、電源、和接地連線全部製作成穿透位於該金屬化層上方的接觸墊，可使得所述訊號、電源、和接地連線所需要的複雜度和延伸路徑的距離增加，導致較大的電阻、較大的功率耗損、較多的金屬化層數量、以及整體較大的製造成本。就其本身而論，業界所亟需的是一種降低穿透該金屬化層的訊號、電源、和接地連線的複雜度的方法。
藉由本發明實施例所提供的穿透基板的穿矽導孔(TSV)，可使得上述所揭露及其他的問題大致上獲得解決和避免，並且大致上能達成技術上的優點。
根據本發明之一實施例，一種半導體裝置包括：一基板，具有一第一面和對向該第一面的一第二面，該基板於該第二面上具有一週邊區域和該週邊區域所環繞的一內部區域；複數個主動元件，位於該基板的該第一面上；一第一組導電孔，延伸穿透該基板，一或多個該第一組導電孔位於該週邊區域中；以及一第二組導電孔，延伸穿透該基板，一或多個該第一組導電孔位於該內部區域中。
根據本發明另一實施例，一種半導體裝置包括：一第一基板，具有一第一面和一第二面；多個主動元件和一金屬化區域，位於該第一基板的該第一面上；以及一電源矩陣，位於該第一基板的該第二面上。
根據本發明又一實施例，一種半導體裝置的製造方法包括；提供一基板，具有一第一面和一第二面，該基板於該第二面上具有一週邊區域和該週邊區域所環繞的一內部區域。形成一第一組導電孔於該週邊區域中，延伸穿透該基板。形成第二組導電孔於該內部區域中，延伸穿透該基板。
本發明所述實施例的優點包括，可降低金屬化層的數量，由此導致較小的整體裝置面積。再者，隨著訊號和電源連線可從該裝置的週邊區域重線佈置於基板的內部中，可使得所述整體尺寸的限制降低。。
為使本發明能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下：
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式，另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
本發明的實施例以特定的內容所揭露，亦即在一晶片系統(system-on-a-chip)的配置中，一半導體晶片具有I/O連線延伸路徑至該半導體晶片的背面。然而，本發明亦可使用其他形式的穿透半導體晶片的連線。
請參閱第1圖，其顯示一基板101具有主動元件102和一層間介電層(interlayer dielectric，簡稱ILD)106。該基板具有一第一面105和對向於該第一面105的第二面107。此外，訊號導孔103和電源/接地(power/ground，簡稱P/G)導孔104形成於基板101和ILD 106內部。該基板101可包括矽塊材、摻雜或未摻雜、或一主動層位於絕緣層上有矽(silicon-on-insulator，簡稱SOI)基板。一般而言，一SOI基板包括一半導體材料層，例如矽、鍺、矽鍺、SOI、絕緣層上有矽鍺(SGOI)、或上述材料的組合。可使用的其他基板包括多層基板、漸層基板、或混合位向基板。
於第1圖中所顯示的主動元件102為五個電晶體。然而，本發明所屬技術領域中具有通常知識者應可理解廣泛的各種類型的元件例如電容、電阻、high-k金屬閘極元件、電感、以及其他等同類型的元件，可用以產生所欲的結構上及功能上的設計需求。另外，該些主動元件102可積體化以形成各種電路，例如訊號驅動器、訊號接收器、靜電放電結構、或其他等同類型的元件，該些主動元件102可利用適當的方法形成於該基板101的表面上或形成於該基板101中。
所述ILD 106是藉由化學氣相沉積法、濺鍍法、或其他任何已知及已使用於本技術領域中用以形成ILD 106的方法以形成於基板101和主動元件102上，典型的層間介電層106具有一平坦化的表面，並且可包括氧化矽，然而亦可選用其他材料，例如high-k材料。該層間介電層106可選擇地形成以致施予一應變於主動元件102內的基板101，如同本技術領域所周知，此將可增加主動元件102的整體效能。
所述訊號導孔103和電源/接地(P/G)導孔104的形成方式可藉由先將一適合的光阻(未顯示)塗佈並顯影，並接著蝕刻該層間介電層106與基板101以形成多個開口。於此階段的該些開口需要延伸進入該基板101，至少超過該些主動元件102，並且抵達一深度至少大於最終所欲完成的基板101的厚度。由於此深度為依賴該基板101的整體設計而決定，因此，此深度可自該基板101的表面深入大約1微米(μm)至大約700微米之間，例如大約50微米。所形成的該些開口具有一直徑大約介於1微米至100微米之間，例如大約6微米。
一旦已形成該些開口，可將該些開口填入一阻障層(未繪示)及一導電材料以形成該訊號導孔103和電源/接地(P/G)導孔104。該阻障層可包括一導電材料，例如氮化鈦，雖然亦可替換使用其他材料，例如氮化鉭、鈦、介電材料、或類似材料。該阻障層可藉由使用一化學氣相沉積法(CVD)形成，例如電漿輔助化學氣相沉積法(PECVD)。然而，亦可選擇使用其他可替代的方法，例如濺鍍法或有機金屬化學氣相沉積法(MOCVD)。該阻障層可形成以順應下方用於訊號導孔103和電源/接地(P/G)導孔104的開口的形狀。
該導電材料可包括銅，雖然亦可替代其他適合的材料，例如鋁、合金、摻雜多晶矽、上述材料的組合、或其他類似的材料。形成該導電材料可藉由先沉積一晶種層，接著形成電鍍銅於該晶種層上，填入且溢滿該些用於訊號導孔103和電源/接地(P/G)導孔104的開口。一旦導電材料已填入該些用於訊號導孔103和電源/接地(P/G)導孔104的開口中，可透過一研磨製程，例如化學機械研磨法(CMP)，雖然亦可使用其他適合的移除製程，將位於該些開口外部多餘的阻障層和多餘的導電層移除。
第2圖顯示形成多金屬化層201和一保護層203於該層間介電層106、該基板101和該訊號導孔103和電源/接地(P/G)導孔104上實施例的剖面示意圖。於此實施例中，該些金屬化層201包括內連線和連接線，以將訊號延伸路徑於該基板101的第一面105上方的各主動元件102之間。然而，於此實施例中，所述輸入、輸出、電源、和接地皆延伸路徑至訊號導孔103和電源/接地(P/G)導孔104，於下文中將對照第3圖詳細描述形成穿矽導孔(TSV)，並且不需要使用I/O接觸墊與位於該基板101的第一面105上方的相關線路。就其本身而論，由於可獲得空間以用於該些主動元件102之間的訊號路徑，因此可使用較少的金屬化層(例如六層或更少的金屬化層)。
該些金屬化層201形成於該基板101、主動元件102、層間介電層106、和該訊號導孔103和電源/接地(P/G)導孔104之上，並且設計以連接各種不同的主動元件102以形成功能性電路。該些金屬化層201的形成是以介電材料和導電材料的交錯疊層形式，並且可利用任何適當的製程(例如沉積、鑲嵌、雙鑲嵌等)。於一實施例中，至少有四層金屬化層分別由ILD層106與基板101隔離，然而，金屬化層201精確數目至少部分依據該半導體晶片的整體設計而定。
於此實施例中，該保護層203可形成成為一完整而連續的層，以包覆該些金屬化層201避免外界接觸。再者，由於該些I/O接觸是藉由訊號導孔103和電源/接地(P/G)導孔104而延伸路徑穿透基板101，該保護層203上並無可以允許製做電性接觸至該些金屬化層201的開口。該保護層203可由一或多種介電材料形成，例如氧化矽、氮化矽、低介電常數材料例如碳摻雜氧化物、極低介電常數材料例如多孔性碳摻雜二氧化矽、上述材料的組合、或同類型性質的材料。該保護層203可透過以下製程形成，例如化學氣相沉積法(CVD)，雖然亦可使用其他適合的移除製程。
第3圖顯示根據本發明實施例之為了露出訊號導孔103和電源/接地(P/G)導孔104而薄化該基板101以形成訊號穿矽導孔(signal TSVs)301和電源/接地穿矽導孔(P/G TSVs)303的剖面示意圖。為了薄化該基板101，將部分的該基板101的第二面107移除以露出位於訊號導孔103和電源/接地(P/G)導孔104內部的導電材料(請參閱第2圖)。該移除步驟可藉由一研磨製程實施，例如化學機械研磨法(CMP)，然而亦可使用其他適合製程，例如蝕刻製程。
然而，本發明所屬技術領域中具有通常知識者應可理解上述揭露形成訊號TSV 301和電源/接地TSV 303的方法，僅僅為用於輔助說明的一實施例，且並非意圖使本發明僅限定於這些實施例中。再者，亦可選擇改用其他適合的方法。例如，可將用於訊號TSV 301和電源/接地TSV 303的開口填入介電材料，直至該基板101的第二面107薄化完成後，於此階段可將介電材料移除並且取代以導電材料。這些實施例以及其他適合的實施例可替代以用於形成訊號TSV 301和電源/接地TSV 303。
在移除部分的該基板101的第二面107之後，可接著實施一清洗蝕刻步驟。此清洗蝕刻步驟意欲清洗並拋光在進行CMP步驟之後的該基板101。此外，此清洗蝕刻步驟亦可幫助應力釋放，此應力是在CMP製程時研磨基板101生成。此清洗蝕刻步驟可使用HNO3 ，然而亦可選擇使用其他適合的替代蝕刻液。
第4圖係顯示於該基板101的第二面107上形成多個重新分佈線(redistribution lines) 401以電性連接至訊號TSV 301和電源/接地TSV 303的剖面示意圖。該些重新分佈線401是從所對應的穿矽導孔(TSV)，這些TSV電性連接至訊號TSV 301和電源/接地TSV 303，而延伸至如下文中所描述的凸塊底層金屬(Under-Bump Metallization，簡稱UBM) 403。
該些重新分佈線401可利用在積體電路中形成連接線的任何適當方法形成。該些重新分佈線401包括至少一由金屬構成的導電層，例如鋁、銅、鎢、鈦、及上述金屬的任意組合。該些重新分佈線401的形成方式可藉由將金屬鍍於一晶種層上，接著蝕刻不想要的部分，留下該些重新分佈線401。於一實施例中，該些重新分佈線401約為2微米(μm)至30微米之間，例如大約5微米。然而，亦可替換地使用其他材料和製程，例如公知的鑲嵌製程(damascene process)以形成該些重新分佈線401。
應瞭解的是，該些重新分佈線401可為單一的導電材料層，或者可替換成多層的導電材料，依所欲的性質而定。例如，如上述所形成的重新分佈線401可鍍上另一導電材料例如金或鉻，以提供與後續形成的連接構件良好的黏結性。此鍍層步驟可藉由例如是CVD的製程步驟完成。
為了要提供與外部連接件405良好的界面性質，所述凸塊底層金屬(UBM) 403可形成於鄰接該些重新分佈線401的部分。此外，在第4圖中為求清楚表示，因而所顯示的UBM 403是位於該些重新分佈線401從訊號TSV 301和電源/接地TSV 303對應的相對面上。應瞭解的是，該些UBM 403的確切位置至少部分是由整體的設計而決定，然而仍應維持透過該些重新分佈線401電性連接至訊號TSV 301和電源/接地TSV 303。
該些UBM 403可由至少三層導電材料所構成，例如一層鉻、一層鉻-銅合金、以及一層銅，並且在銅層的頂部上方可選擇性的形成一層金。然而，應瞭解的是，上述材料和層仍有更適當的配置方式，例如以鈦/鈦鎢/銅的配置方式或者以銅/鎳/金的配置方式會更適合於形成該些UBM 403。任何可用於該些UBM 403的適合材料和結構層皆完全包含於本申請案的精神和範圍內。
該些UBM 403的形成方式可藉由將各材料層順應性地形成於該些重新分佈線401上。各材料層可藉由CVD製程完成，例如PECVD，雖然亦可替換地使用其他製程，例如濺鍍或蒸鍍，依所欲沉積的材料而決定。於該些UBM 403中的各材料層可具有一厚度範圍約介於10微米至100微米之間，例如大約45微米。一旦已形成所欲的材料層，接著將部分的材料層以適當的微影光罩和蝕刻法移除，以去除不想要的材料並留下圖案化的UBM 403。
所述外部連接件405可包括多個接觸凸塊，由例如是錫的材料構成，或者由其他適合的材料，例如矽、無鉛錫或銅構成。於一實施例中，該些外部連接件405為錫焊料凸塊。該些外部連接件405可一開始先形成厚度約為100微米的一錫層，透過一般所使用的方法，例如蒸鍍、電鍍、印刷、焊料轉印、植球等。一旦一錫層已形成於上述的結構體上，可實施一迴焊步驟，以將材料定型成為所欲的凸塊形狀。
藉由使用訊號TSV 301和電源/接地TSV 303以將電路直接地連接至該基板101的第二面107上，因而將一縮短的低電阻路徑形成，以供外部I/O介面。就其本身而論，可消除典型的高電阻堆疊式導電孔與長金屬路線。此長金屬路線一般與位於該基板101的第一面105上的訊號301和電源路線相關。上述消除高電阻堆疊式導電孔與長金屬路線得以降低金屬化層的數目。此外，因為在此實施例中並沒有需要穿透該保護層203的連線，因此可使用較窄的金屬線於該頂部金屬層，而非使用相對厚的金屬線，其一般僅使用於較上層的該些金屬化層203。上述使用較窄的金屬線能允許更進一步的改善繞線度(routability)。
第5A圖顯示根據本發明之一實施例的具潛力的I/O佈局架構。如第4圖中所示，該些金屬化層201為藉由訊號TSV 301和電源/接地TSV 303直接地連接至位於該基板101的第二面107上的該些重新分佈線401，由此可允許將訊號TSV 301和電源/接地TSV 303設置於該基板101的第二面107上的位置，仍能維持一縮短的連線路徑。例如，如同明確地顯示於第5A圖中，該訊號TSV 301和電源/接地TSV 303可不僅設置於沿著該基板101第二面107的週邊區域的多條線，並且該些線可作為延伸作用，將該基板101劃分成一第一區塊501和第二區塊503，或者進一步將該第二區塊劃分成一第三區塊505和第四區塊507，或上述之任意組合。
第5B圖顯示根據本發明另一實施例的另一具潛力的I/O佈局架構。於此I/O佈局架構中，將該訊號TSV 301和電源/接地TSV 303形成分屬兩個分開的群組：一週邊群組和一內部群組。於該週邊群組中，該訊號TSV 301和電源/接地TSV 303是沿著該基板101的外部邊緣排列。由該訊號TSV 301和電源/接地TSV 303的週邊群組所環繞的該訊號TSV 301和電源/接地TSV 303的內部群組可排列成一或多條分開且離散的線。這些分開且離散的線可形成平行於該基板的任意一邊，並且多條線可形成彼此間相互垂直。
然而，應瞭解的是，於上述第5A和5B圖所顯示的佈局架構實施例僅僅為兩個用於說明的實施例，並非欲以任何形式限定本發明。基於包含了該些重新分佈線401，可實現含有該訊號TSV 301和電源/接地TSV 303的任一具潛力的佈局，而仍然能維持與該些外部連接件405的連接。全部的這些具潛力的佈局架構皆應視為包含於本發明的保護範圍之內。
因為上述包含了該訊號TSV 301、電源/接地TSV 303、和該些重新分佈線401實施例可增加電源與訊號的選擇性，所以在主動元件102上方的金屬層化層的數量得以降低，導致整體裝置變得更小且更便宜。此外，因為該些外部連接件405可設置成任意的型式，因此上述在晶片上的線路重新分佈通常可實現而無負面效果，導致進一步降低晶片尺寸。
第6A-6B圖分別顯示根據本發明另一實施例的具有電源矩陣600的基板101的第二面107的放大剖面圖和平面圖。為了要直接穿過該基板101直接供應電力給該些主動裝置102，該電源矩陣600是形成於該基板101的第二面107上，且與多重電源/接地TSV 303連接。就其本身而論，由於該電源矩陣600是沿著該基板101的第二面107形成，因此可將一或多個訊號接觸墊613形成於該些金屬化層201的頂層，以穿透該保護層203連接至外部元件。於此樣態中，該電源/接地連線和訊號連線可彼此相互分離，因而該電源/接地連線藉由電源/接地TSV 303延伸路徑穿透該基板101，並且該訊號連線延伸路徑穿透該些金屬化層201和保護層203。
於此實施例中，該些電源/接地TSV 303、該些重新分佈線401、以及該些外部連接件405可分別再次分為電源TSV 601和接地TSV 603、電源重新分佈線605和接地重新分佈線607、電源外部連接件609和接地外部連接件611。於此實施例中，該些電源TSV 601和接地TSV 603排列成一包含行與列的陣列型式，各個行與列具有一交錯序列的電源TSV 601和接地TSV 603。另外，該些電源重新分佈線605和接地重新分佈線607位於一直線上並以交錯的型式排列，使得一電源重新分佈線605並非位於另一電源重新分佈線605的下一順位，而是位於一或多個接地重新分佈線607的下一順位。於此樣態中，一電源重新分佈線605可將各個列上的電源TSV 601連接在一起，而一接地重新分佈線607可將各個列上的接地TSV 603連接在一起。
於此實施例中，多個電源外部連接件609沿著各電源重新分佈線605形成，且各個電源外部連接件609位於一電源TSV 601的上方。在沿著各個電源重新分佈線605上，各個由一電源外部連接件609所覆蓋的電源TSV 601僅相鄰一個其他電源外部連接件609，其亦被另一個電源外部連接件609所覆蓋。就其本身而論，各個電源重新分佈線605具有兩個由被電源外部連接件609所覆蓋的電源TSV 601，並接著一個未被電源外部連接件609所覆蓋的電源TSV 601的重複模式。
相似地，各個接地外部連接件611位於一接地TSV 603的上方。在沿著各個接地重新分佈線607上，各個由一接地外部連接件611所覆蓋的接地TSV 603僅相鄰一個其他接地外部連接件611，其亦被另一個接地外部連接件611所覆蓋。就其本身而論，各個接地重新分佈線607具有兩個由被接地外部連接件611所覆蓋的接地TSV 603，並接著一個未被接地外部連接件611所覆蓋的接地TSV 603的重複模式。
然而，應瞭解的是，於上述參照第6圖所述的陣列佈局僅僅做為一佈局架構的說明的實施例，此佈局架構可用於供應電力和接地連線至該些主動元件102。任何適當的電源TSV 601和接地TSV 603、電源重新分佈線605和接地重新分佈線607、及電源外部連接件609和接地外部連接件611的佈局皆可替換地用於供應電力至該半導體晶片。任一及全部的佈局皆應視為包含於本發明的保護範圍之內。
所述位於該基板101第二面107上的電源矩陣600可10倍小於傳統具有相同電阻的電源網(power mesh)。就其本身而論，此電源矩陣600可取代傳統的電源網，該電源網出現於傳統半導體晶片的最上層金屬化層中，進而允許移除統的電源網及降低所需金屬化層的數量。再者，由於並無中間的電源延伸路徑，外部連接件405(例如電源墊)的整體數量可顯著地降低，允許訊號延伸路徑出現在原先被電源延伸路徑佔據的區域，並且進一步降低位於該基板101第一面105上所需金屬化層的數量。該些電源/接地TSV 303可另做為去耦合電容(decoupling capacitor)，可最小化源自電源供應器的雜訊。上述所有的電源/接地TSV 303可用於降低晶片在面積和金屬化層上的整體尺寸，因而允許在每個晶圓上形成更多的晶片數目，降低成本，且增加良率，然同時降低電源和接地接腳的數目，從一般的1000個至大約300個。
第6C圖顯示本發明另一實施例的電源矩陣600，其由一或多列的電源外部連接件609、接地外部連接件611和訊號外部連接件615所環繞，而非僅沿著該基板101的第二面107連接。基於該電源外部連接件609和接地外部連接件611分別地電性連接至電源TSV 601和接地TSV 603，該訊號外部連接件615連接至訊號TSV 301以將訊號從該基板101的第二面107延伸路徑至該些主動元件102。然而，於此實施例中，由於在週邊區域具有混合的電源外部連接件609、接地外部連接件611和訊號外部連接件615，因此並沒有接地外部連接件611位於電源矩陣600中。
第6D圖顯示本發明再一實施例，相似於上述參照第6C圖的實施例說明內容，此實施例亦將訊號TSV 301納入電源矩陣600中。於此實施例中，該電源矩陣600位於該基板101第二面107的中央、非週邊區域，並且由一或多列的電源TSV 601、接地TSV 603和訊號外TSV 605與其對應的電源外部連接件609、接地外部連接件611和訊號外部連接件615的組合所環繞。然而，於此實施例中，一或多個電源TSV 301位於該電源矩陣600的自身中，由此可擴展選擇訊號延伸路徑至該些主動元件102。訊號可藉由訊號重新分佈線617延伸路徑至上述一或多個電源TSV 301。
第7圖顯示本發明之一實施例，將上述第5A-5B圖的佈局架構的使用方式與上述第6A-6D圖的電源矩陣整合納入系統級封裝(system in package)架構中，而非晶片系統(system on chip)架構中。於此實施例中，上述所揭露的結構與佈局可整合於多重半導體晶片中，例如第一半導體晶片701、第二半導體晶片703、和第三半導體晶片705於一系統級封裝(system in package)配置中。所述第一半導體晶片701、第二半導體晶片703、和第三半導體晶片705可接著接合至一封裝基板709(例如一印刷電路板)，並且上述半導體晶片彼此間相互結合使得一半導體晶片的TSV(例如第二半導體晶片703的訊號TSV 301)與訊號接觸墊603電性連接，或者與一相鄰的半導體晶片(例如第一半導體晶片701)的後導孔製程的穿矽導孔(via-last TSV) 707電性連接。
該後導孔製程的TSV 707可藉由與第1-3圖中所描述的訊號TSV 301和電源/接地TSV 303相類似的工序形成。然而，該後導孔製程的TSV 707的移除和填入步驟是在形成保護層203的步驟之後完成，而非藉由先導孔製程(via-first process)例如是先前所揭露的訊號TSV 301和電源/接地TSV 303。因此，當完成後導孔製程的TSV 707，TSV 707會延伸穿透其本身所存在的半導體晶片(例如第一半導體晶片701)。因此，由上述揭露的實施例可形成先導孔製程TSV(例如訊號TSV 301和電源/接地TSV 303)和後導孔製程TSV(例如後導孔製程的TSV 707)的組合。此外，該訊號TSV 301和電源/接地TSV 303是用來將電源和訊號延伸路徑至位於晶片內的該些主動區域102，且該訊號TSV 301和電源/接地TSV 303是形成於晶片上，另一方面，後導孔製程的TSV 707是用來將電源和訊號延伸路徑穿透該後導孔製程的TSV 707所位在該晶片，再延伸至另一晶片(例如該第二半導體晶片703)。
藉由將訊號TSV 301、電源/接地TSV 303、和後導孔製程的TSV 707相結合，可形成從該第一半導體晶片701的基板101的第二面107至該第二半導體晶片703的基板101的第二面107的多條連接線。例如，位於該第一半導體晶片701的基板第二面107上的電源矩陣600可供應電源至該第一半導體晶片701的主動區域，然而亦可使用後導孔製程的TSV 707以供應電源至位於該第二半導體晶片703的基板101第二面107上的另一電源矩陣600。
再者，應瞭解的是，以上所描述透過後導孔製程的TSV 707所連接的電源矩陣600僅僅為本發明的實施範例之一。任何對應於第5D-6D圖所描述的佈局和架構的適當結合皆可用於形成多重的連線，以供應訊號、電源和接地連線至該第一半導體晶片701、第二半導體晶片703、和第三半導體晶片705。所有的潛在的結合皆應視為包含於本發明的保護範圍之內。
本發明雖以各種實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾。本發明之保護範圍當視後附之申請專利範圍所界定者為準。
101．．．基板
102．．．主動元件
103．．．訊號導孔
104．．．電源/接地(P/G)導孔
105．．．基板的第一面
106．．．層間介電層(ILD)
107．．．基板的第二面
201．．．金屬化層
203．．．保護層
301．．．訊號穿矽導孔
303．．．電源/接地穿矽導孔
401．．．重新分佈線
403．．．凸塊底層金屬(UBM)
405．．．外部連接件
501．．．第一區塊
503．．．第二區塊
505．．．第三區塊
507．．．第四區塊
600．．．電源矩陣
601．．．電源TSV
603．．．接地TSV
605．．．電源重新分佈線
607．．．接地重新分佈線
609．．．電源外部連接件
611．．．接地外部連接件
613．．．訊號接觸墊
615．．．訊號外部連接件
617．．．訊號重新分佈線
701．．．第一半導體晶片
703．．．第二半導體晶片
703．．．第三半導體晶片
707．．．後導孔製程的穿矽導孔
709．．．封裝基板
第1圖顯示根據本發明之實施例的基板具有主動元件和一層間介電層(interlayer dielectric，簡稱ILD)的剖面示意圖。
第2圖顯示形成多金屬化層和一保護層於該層間介電層、該基板和該訊號導孔和電源/接地(P/G)導孔上的實施例的剖面示意圖。
第3圖顯示根據本發明實施例之為了露出訊號導孔和電源/接地(P/G)導孔而薄化該基板以形成訊號穿矽導孔(signal TSVs)和電源/接地穿矽導孔(P/G TSVs)的剖面示意圖。
第4圖係顯示於基板的第二面上形成多個重新分佈線以電性連接至訊號TSV和電源/接地TSV的剖面示意圖。
第5A和5B圖顯示根據本發明之實施例的具潛力的I/O佈局架構。
第6A-6B圖分別顯示根據本發明另一實施例的基板的第二面具有電源矩陣的放大剖面圖和平面圖。
第6C圖顯示本發明另一實施例的電源矩陣，其由一或多列的電源外部連接件、接地外部連接件和訊號外部連接件所環繞，而非僅沿著基板的第二面連接。
第6D圖顯示本發明再一實施例，相似於上述第6C圖的實施例說明內容，此實施例亦將訊號TSV納入電源矩陣中。
第7圖顯示本發明之一實施例，將第5A-5B圖的佈局架構的使用方式與第6A-6D圖的電源矩陣整合納入系統級封裝(system in package)架構中的剖面示意圖。
101．．．基板
102．．．主動元件
103．．．訊號導孔
104．．．電源/接地(P/G)導孔
105．．．基板的第一面
106．．．層間介電層(ILD)
107．．．基板的第二面
201．．．金屬化層
203．．．保護層
301．．．訊號穿矽導孔
303．．．電源/接地穿矽導孔
401．．．重新分佈線
403．．．凸塊底層金屬(UBM)
405．．．外部連接件

Claims (13)

  1. 一種半導體裝置，包括：一基板，具有一第一面和對向該第一面的一第二面，該基板於該第二面上具有一週邊區域和該週邊區域所環繞的一內部區域；複數個主動元件，位於該基板的該第一面上；一第一組導電孔，延伸穿透該基板，一或多個該第一組導電孔位於該週邊區域中；以及一第二組導電孔，延伸穿透該基板，一或多個該第二組導電孔位於該內部區域中。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該第二組導電孔位於一條線上將該基板的該第二面分隔成一第一區塊和一第二區塊。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括多條重新分佈線，設置於該基板的該第二面上，該些重新分佈線電性連接至該第二組導電孔。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括：多個金屬化層，位於該基板的該第一面之上；以及一連續的保護層，位於該些金屬化層之上。
  5. 如申請專利範圍第1項所述之半導體裝置，其中該第二組導電孔排列成至少一第一直線和一第二直線，其中該第一直線平行於該基板的該第一面，以及該第二直線垂直於第一直線且該第二直線與該第一直線分開。
  6. 一種半導體裝置，包括： 一第一基板，具有一第一面和一第二面；多個主動元件和一金屬化區域，位於該第一基板的該第一面上；以及一電源矩陣，位於該第一基板的該第二面上。
  7. 如申請專利範圍第6項所述之半導體裝置，更包括多個導電孔，延伸穿透該第一基板，並使該些主動元件和該金屬化區域電性連接至該電源矩陣。
  8. 如申請專利範圍第6項所述之半導體裝置，其中該電源矩陣更包括：一重新分佈層，電性連接至該些導電孔；以及多個外部連接，電性連接至該重新分佈層。
  9. 如申請專利範圍第8項所述之半導體裝置，其中該重新分佈層包括多條電源重新分佈線和接地重新分佈線，排列成交錯的列。
  10. 如申請專利範圍第8項所述之半導體裝置，其中各個外部連接是位於一導電孔的上方，該導電孔相鄰於不多於一個其他導電孔，其位於另一外部連接的下方。
  11. 一種半導體裝置的製造方法，包括：提供一基板，具有一第一面和一第二面；形成多個主動元件和一金屬化區域於該基板的該第一面之上；以及形成一電源矩陣於該第一基板的該第二面之上。
  12. 如申請專利範圍第11項所述之半導體裝置的製造方法，更包括形成多個導電孔使得該電源矩陣電性連接至該些主動元件和該金屬化區域，該些導電孔延伸穿透該基板。
  13. 如申請專利範圍第12項所述之半導體裝置的製造方法，更包括：形成一重新分佈層，使其與該些導電孔電性接觸；以及形成多個外部連接，使其與該重新分佈層電性接觸。
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US8552563B2 (en) 2013-10-08
US20140264941A1 (en) 2014-09-18
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