TW200820412A - Semiconductor chip, semiconductor chip stack and stacking mathod thereof - Google Patents

Semiconductor chip, semiconductor chip stack and stacking mathod thereof Download PDF

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Publication number
TW200820412A
TW200820412A TW096136656A TW96136656A TW200820412A TW 200820412 A TW200820412 A TW 200820412A TW 096136656 A TW096136656 A TW 096136656A TW 96136656 A TW96136656 A TW 96136656A TW 200820412 A TW200820412 A TW 200820412A
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TW
Taiwan
Prior art keywords
wafer
semiconductor wafer
solder
semiconductor
metal
Prior art date
Application number
TW096136656A
Other languages
Chinese (zh)
Inventor
Juergen Simon
Laurence Edward Singleton
Original Assignee
Qimonda Ag
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Filing date
Publication date
Application filed by Qimonda Ag filed Critical Qimonda Ag
Publication of TW200820412A publication Critical patent/TW200820412A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The chip has contact pads with through-contacts arranged in an area in the form of vias, and metal plugs freely lying on a front side (18) and provided with a solder material (8). The material is applied on the front side in the form of solder balls on the plugs and intermediate spaces between the balls are filled with a concrete joint sealing compound on a semiconductor wafer (1). The compound has adhesive characteristics, and a rear side (12) is provided with a passivation layer that freely leaves one of the metal plugs. An independent claim is also included for a method for stack mounting of semiconductor chips.

Description

200820412 九、發明說明： 導體m形成半導體堆疊的半導體晶片，此種半 塾二電=作=該作用正面具有包括接觸襯 获乂及具有没置在接觸襯墊之區域的敷 的 全脉n 之作用正面及背面上有設置露空 孟屬心，啊金屬栓含有-種焊料。 晶片堆属卜且包括一種半導體晶片堆疊，該半導體 且^有個弟一半導體晶片及一個堆疊在第一半導 體曰曰片之上的第—半導體晶片，且堆疊方式為第二半導體 之背面係位於第-半導體晶片之作用正面的上方，其中， j這^個^導體晶片中都有設置金屬化敷鑛通孔，同時第 -半導體晶片之侧正面上的敷鍍通孔與第二半導體晶片 之背面上的敷鍍通孔藉由焊料構成的中間連接單元形:導 電連接。 此外，本發明還包括一種將半導體晶片堆疊在一起的 方法，根據這種方法，一個具有包括接觸襯墊在内之電路 元件的晶圓的作用正面在接觸襯墊之區域設有凹槽，且凹 槽之深度大於晶圓被磨薄之後的高度。為了製作敷鍍通 孔，所以用金屬填料將這些凹槽填滿，而且該金屬填料含 有焊料，因此彼此堆疊在一起的半導體晶片可以藉由敷鍍 通孔及焊料彼此形成導電連接。 為了進一步縮小電子產品(尤其是可攜式電子產品)的 體積，以及提高電子產品的功能，一種屬於已知技術的作 法是將晶片堆疊在一起。晶片的堆疊有多種不同的連接技 5 200820412 術可供選擇。其中一種已知的連接技術是以敷鑛通孔穿過 晶片的矽材料部分，也就是說一直到達晶片的平坦延伸部 分，這種技術就是所謂的TSV技術(TSV : Through Silicon Via)。由於一種生產效率很高的方法需要將許多製程步驟整 合在晶圓上完成，因此與另外一種亦屬於已知技術之多晶 片組合線連接技術相比，這種TSV技術的製程不但比較費 事’成本也比較高。 美國專利US 2005/0277293揭示一種成本較低的敷鍍 通孔方法。這種方法是先在接觸襯墊區設置垂直於晶片之 平坦延伸部分的盲孔式凹槽。接著在晶片的整個表面(也就 是晶圓的整個表面，因為此時晶片仍位於晶圓上)上設置一 個基本金屬化層，也就是所謂的種子層(SeedeeLayer)。這樣 整個晶圓表面就都具有導電性。接著在該基本金屬化層形 成個掩核，且该掩核在將會有金屬化層生長的位置設有 掩模開口。在接通電壓後，可以在一個電解過程中使金屬 沉積到掩模開口中。在盲孔區也設有這種掩模開口，因此 盲孔也會被金屬填滿。在將掩模去除後，接著將半導體晶 片的背面磨平，也就是將與晶圓具有晶片結構化的那一個 面背對的面磨平，以降低半導體晶片的厚度。 由於盲孔的深度大於晶圓被磨薄後的晶圓厚度，因此 盲孔會在晶圓背面露出開口，使位於盲孔内的金屬化部分 露出。此時這些盲孔就可以作為敷鍍通孔使用。為了將彼 此疊在一起之晶片的敷鍍通孔連接在一起，因此敷鍍通孔 在晶圓背面上有設置焊料。該焊料是以電鍍方式沉積出來 6 200820412 的來’其中在晶圓正面(也就是晶片結構化所在的那一個晶 圓面)上的基本金屬化制樣是作為所有敷鍍通孔之電鐘沉 積的電觸點魏之用。晶„面上的销是作為電鑛沉積 的掩模。待電鍍沉焊概，可簡基本金屬化層結構 化0 雖然製作敷鍍通孔健-倾模步驟，因此能夠將製 各的複雜性控録相當小的程度内，但缺點是必須在力學 穩定性並不足夠的被磨薄的晶圓上進行焊料沉積。 土美國專利US 6 905 945揭示一種在晶圓上加上一層非 流動未充滿材料(no_fl〇w-underfilknaterial)以提高晶圓之力 學穩定性的方法。但是這種方法僅_於—般的倒裝法應 用，對TSV方法並不適用。 本發明的目的是在保持敷鍍通孔之結構化的前提下， 僅以一個掩模避免在被磨薄的晶圓上電鍍沉積出焊料。 採用本文開頭提及的半導體晶片即可達到上述目的， 這種半導體晶片的特徵是作用正社的焊料是以焊料球的 型式被設置在金屬栓上，同時在晶圓上的焊料球之間的空 隙被一種灌注料填滿。 i 這種作法的優點是可以將晶圓背面之加工及在作用正 面上設置焊接球的工作分開進行。因此沉積焊料及熔化成 焊料球的過程可以在未被磨薄的晶圓上進行。將焊料球之 間的空隙以灌注料填滿有助於提高晶圓在磨薄過程及加工 被磨薄之晶圓時的力學穩定性。 根據本發明的一種有利的實施方式，灌注料具有黏著 7 200820412 性。因此灌注料不僅能夠提高被磨薄的晶圓或被磨薄的半 導體晶片的穩定性，㈣在將被分觸的半導晶片堆疊在 一起時，可以在半導體晶片對形成機械連接。 根據本發明的另外一種有利的實施方式，半導體晶片 的背面具有一個使金屬栓露空的鈍化層。如果沒有這個鈍 化層，則在將半導體晶片堆疊在一起時，半導體晶片的背 面a絡工。在半導體晶片的背面上的金屬栓也是露空的， 以便與半導體晶片的焊料形細點接通。不過這樣在焊接 過程中焊料可能會與背面神層形成連接，所以會產生焊 料的重金屬離子滲入矽層的問題，因此鈍化層的一個作用 是可以防止這種情況的發生。 一種可行的方式是以一種非流動未充滿材料構成鈍化 層。在製造半導體晶片的過程中，可以用一種屬於已知技 術的壓模法將這種材料製作成鈍化層。 也可以用聚合物製作鈍化層。 根據本發明的另外一種有利的實施方式，鈍化層具有 黏著14因此不論半導體晶片的襯底是何種性質，例如該 襯底可以是一個基體或是一個在其作用正上有一層灌注料 的半導體晶片，半導體晶片的背面都可以黏著在襯底上， 因而形成機械固定。 本發明還包括本文開頭提及的一種半導體晶片層堆， 其特徵為第-半導體晶片及第二半導體晶片之間的空隙被 一種以壓模法注入的非流動未充滿材料填滿。 將中間空隙填滿的工作對於所使用的技術及材料都有 8 200820412 很南的要求。因此通常是使用一種流動性良好的未充滿材 料。要填滿的空隙間距愈小，未充滿材料的流動性就必須 愈好，因此需定期調整所使用的填充材料，以使其保持足 夠的流動性。所以填充料需要的流動性愈好，填充料的成 本就愈高。利用非流動未充滿材料將中間空隙填滿可以避 免需事後娜巾間雜填滿的鋪。此猶流動未充滿材 料是一種不是利用流動性流入或滲入空隙的填充料，而是 利用種成型方法(例如壓模法或印製法)被填入空隙的填 充料。因此在作業時是先將填充料塗覆在半導體晶片的作 用正面上，然後再將半導體晶片堆疊在一起。 本發明的一種有利的實施方式是直接以非流動未充滿 ^料將第-半導體晶韻正面及第二半導體晶片的背面黏 著在起這樣做的好處是非流動未充滿材料不僅能夠將 中間空隙完全填滿，而且可以在兩個半導體晶片之間形成 穩固的連接。這種實施方式在作#時是先將賴動未充滿 材料塗覆在轉體^上，然後再將轉體晶牌疊在一 ，。至在轉接方式在堆疊在—起的半導體⑼之間形成 焊接連接時會活化非_未充滿材料_紐，因而產生 黏著效果。 根據本發明的另外一種有利的實施方式，在第二半導 體晶片的背面及作為填充料的非流絲充滿材料之間有設 置一個由聚合物構成的分隔層。這個分隔的作暇防止焊 料與其所在之半導體晶片断質背面接觸，賭止重金屬 離子滲入矽材料中。 9 200820412 一個聚合物 也可以在第一半導體晶片的背面上設置 層。200820412 IX. Description of the invention: The conductor m forms a semiconductor wafer of a semiconductor stack, and the positive side has a full pulse n including a contact lining and a region not disposed in the contact pad. The front and back sides are provided with a hollowed-out heart, and the metal plug contains a kind of solder. The wafer stack includes a semiconductor wafer stack having a semiconductor wafer and a first semiconductor wafer stacked on the first semiconductor wafer, and the stacking is performed on the back side of the second semiconductor The upper surface of the first semiconductor wafer is disposed on the front surface of the semiconductor wafer, wherein the metallized through-holes are disposed in the conductor wafer, and the through-via on the front side of the first semiconductor wafer and the second semiconductor wafer The plated through hole on the back side is formed by an intermediate connecting unit formed of solder: an electrically conductive connection. Furthermore, the present invention also includes a method of stacking semiconductor wafers together, according to which a wafer having a circuit component including a contact pad is provided with a recess in a region of the contact pad, and The depth of the groove is greater than the height after the wafer is thinned. In order to form the plated through holes, the grooves are filled with a metal filler, and the metal filler contains solder, so that the semiconductor wafers stacked on each other can be electrically connected to each other by the through holes and the solder. In order to further reduce the size of electronic products (especially portable electronic products) and to enhance the functions of electronic products, it is a known technique to stack wafers together. There are many different connection technologies for stacking wafers. One of the known joining techniques is that the through-holes pass through the portion of the tantalum material of the wafer, that is, all the way to the flat extension of the wafer. This technique is known as TSV (Through Silicon Via). Since a highly productive method requires a number of process steps to be integrated on the wafer, this TSV process is not only more complicated than another multi-chip combination wire connection technology that is also known in the art. The cost is also relatively high. U.S. Patent No. 2005/0277293 discloses a lower cost method of plating vias. This method involves first providing a blind via recess in the contact pad region that is perpendicular to the flat extension of the wafer. A basic metallization layer, also known as a seed layer, is then placed over the entire surface of the wafer (i.e., the entire surface of the wafer because the wafer is still on the wafer). This makes the entire wafer surface conductive. A mask is then formed in the base metallization layer and the mask is provided with a mask opening at a location where the metallization layer will be grown. After the voltage is turned on, metal can be deposited into the mask opening during an electrolysis process. This mask opening is also provided in the blind hole area, so that the blind hole is also filled with metal. After the mask is removed, the back side of the semiconductor wafer is then flattened, i.e., the surface opposite the wafer having the wafer structure is flattened to reduce the thickness of the semiconductor wafer. Since the depth of the blind via is greater than the thickness of the wafer after the wafer is thinned, the blind via exposes the opening on the back side of the wafer, exposing the metallized portion in the blind via. These blind holes can then be used as plated through holes. In order to connect the plated vias of the wafers stacked one upon another, the vias are provided with solder on the back side of the wafer. The solder is deposited by electroplating 6 200820412's basic metallization on the front side of the wafer (that is, the wafer surface on which the wafer is structured) is the electric clock deposition for all coated vias. The electrical contacts are used by Wei. The pin on the surface of the crystal is used as a mask for the deposition of electric ore. To be electroplated and deposited, the basic metallization layer can be structured. 0 Although the through-hole drilling-dipping mode is performed, the complexity can be made. The control is relatively small, but the disadvantage is that solder deposition must be performed on a thinned wafer where mechanical stability is not sufficient. U.S. Patent No. 6,905,945 discloses the application of a non-flowing layer on a wafer. A method of filling the material (no_fl〇w-underfilknaterial) to improve the mechanical stability of the wafer. However, this method is only applicable to the flip-chip method and is not applicable to the TSV method. The object of the present invention is to maintain the application. Under the premise of structuring plated through holes, only one mask is used to avoid electroplating and depositing solder on the thinned wafer. The above object can be achieved by using the semiconductor wafer mentioned at the beginning, which is characterized by The solder of the role of Zhengshe is placed on the metal plug in the form of a solder ball, while the gap between the solder balls on the wafer is filled with a potting material. i The advantage of this method is that the back side of the wafer can be The work of setting the solder balls on the front side of the action is performed separately. Therefore, the process of depositing solder and melting into solder balls can be performed on the unpolished wafer. Filling the gap between the solder balls with the potting material helps In order to improve the mechanical stability of the wafer during the thinning process and the processing of the thinned wafer. According to an advantageous embodiment of the invention, the filling material has the adhesion 7 200820412. Therefore, the filling material can not only improve the thinned The stability of the wafer or the thinned semiconductor wafer, (iv) the mechanical connection can be formed in the semiconductor wafer pair when the contacted semiconductor wafers are stacked together. According to another advantageous embodiment of the invention, the semiconductor wafer The back side has a passivation layer that exposes the metal plug. Without this passivation layer, the backside of the semiconductor wafer is lapped when the semiconductor wafers are stacked together. The metal plug on the back side of the semiconductor wafer is also exposed. In order to connect with the solder-shaped fine spots of the semiconductor wafer, but the solder may form a connection with the back god layer during the soldering process. Therefore, there is a problem that the heavy metal ions of the solder penetrate into the ruthenium layer, and therefore one function of the passivation layer is to prevent this from happening. One possible way is to form a passivation layer with a non-flowing underfill material. In the process, the material may be formed into a passivation layer by a compression molding method known in the art. It is also possible to form a passivation layer from a polymer. According to a further advantageous embodiment of the invention, the passivation layer has an adhesion 14 so that What kind of property is the substrate of the semiconductor wafer, for example, the substrate can be a substrate or a semiconductor wafer having a layer of potting material applied thereto, and the back surface of the semiconductor wafer can be adhered to the substrate to form a mechanical fixing. The present invention also includes a semiconductor wafer layer stack as mentioned at the outset, characterized in that the gap between the first semiconductor wafer and the second semiconductor wafer is filled by a non-flowing underfill material which is injection molded. The work of filling the intermediate gap has a very high requirement for the technology and materials used. Therefore, it is usually the case that an unfilled material with good fluidity is used. The smaller the gap spacing to fill, the better the fluidity of the unfilled material, so the filler material used should be adjusted periodically to maintain adequate fluidity. Therefore, the better the fluidity required for the filler, the higher the cost of the filler. Filling the intermediate space with a non-flowing, unfilled material avoids the need for a shop that fills up after the towel. The still flowing material is a filler which is not flow-in or infiltrated into the void, but is filled with a void by a seed molding method such as compression molding or printing. Therefore, in the operation, the filler is first coated on the front surface of the semiconductor wafer, and then the semiconductor wafers are stacked together. An advantageous embodiment of the present invention is to directly adhere the front side of the first semiconductor crystal and the back side of the second semiconductor wafer with a non-flowing underfill material. The advantage of doing so is that the non-flowing underfill material can not only completely fill the intermediate space. Full, and a robust connection between the two semiconductor wafers. In this embodiment, when the # is made, the unfilled material is first applied to the rotating body, and then the rotating crystal plates are stacked. When the soldering connection is formed between the stacked semiconductors (9) in the switching mode, the non-underfill material_news is activated, thereby producing an adhesive effect. According to a further advantageous embodiment of the invention, a spacer layer of polymer is provided between the back side of the second semiconductor wafer and the non-filament filled material as a filler. This separation prevents the solder from coming into contact with the broken back side of the semiconductor wafer on which it is placed, jeopardizing the infiltration of heavy metal ions into the germanium material. 9 200820412 A polymer may also be provided with a layer on the back side of the first semiconductor wafer.

根據本發明提出之堆疊方法，焊料是在晶職磨薄之 前在作用正面被塗覆到金屬填料上，接著再將晶圓之與作 用正面相制立的背面賴，錢金屬频從背面露空及 形成敷鍍通孔，其中，露空的金屬填料形成金屬检。婉由 上述步驟可贼焊航積及烊接球成·難在未被薄的 晶圓上進行。因此本伽的方料但可以簡化製程，而且 可以降低晶圓破裂的風險。 本發明之方法的-種實施方式是以金屬填料將凹槽殖 滿^吏得在的整個_正面上沉積出—個金屬化層，、 接者在金屬化層上置-個在被金屬填料填滿之凹槽上方 具有掩酬Π的級抗錄模，接著在掩細口内^ 金屬化層上接通-個賴以紐方式沉焊料 位於被焊料覆蓋㈣面狀外的光致抗 厚 2掉’然後再將谭料_料球，也心= 2致餘掩模被去除後不應被糊之金屬填料的位 S由於這種金屬_抵抗姻技術只需使用一個光致 掩拉’因此可以収鮮的方式完成結構化過程。 種可订賴化方式是，在以金屬將凹槽填滿後，姐 料輸送過程在晶圓的侧正面上將金屬化的焊才; 二凹槽⑽金屬频上’然後再將焊觀化成 據這種變化方式，烊料也可以作為金屬抗鱗模、， 、在烊料輸送過程結束後(也就是在以印製法將焊料輪送到 200820412 =屬栓之域)’作為在將焊料熔化之前或之後去除填滿敷 ，又通孔所巾之金屬層㈣掩模。這麵化方式*需要另外 用-個光致_掩模進行遮蔽作業。 /根據本發明之料的—種實施对，在將焊料溶化之 後及將晶圓磨薄之前以灌注料將晶圓上之焊料球之間的空 隙填滿。除了灌注料是在是在將半導體晶牌疊在一起後 才破注入填滿堆疊在一起之半導體晶片之間的空隙外，灌 =料的注人亦有助於提高晶_力學穩定性，因此可以提 高晶圓在成型時或成型期間對機械變化的抵抗力。 、-種制有獅方式是以流動未充滿材料將空 隙填滿。雜錢動未充滿材·製造成本較低，而且可 以用-般已知的方法被填人雜。因此使用非流動未充滿 材料可以達到降低成本的效果。 也可以利用一種屬於已知技術的壓模法將焊料球之間 的空隙填滿。這種方法是將一個壓模置於晶圓上，也就是 置於焊料球上，然後以一種灌注料將空隙填滿。 也可以利用非流動未充滿材料將半導體晶片黏著在一 起，同時以一起二階段可熱硬化材料(B階段材料)將空隙填 滿。在將半導體晶片堆疊在一起後(不論是仍在未切割的晶 圓上或是已經切割成單一的半導體晶片），接著將B為段材 料加熱到一定的温度，並在這個溫度下黏著在半導體晶片 上然後硬化。可以利用焊接金屬栓時的加熱溫度來進行同 時這個步驟。不過原則一也可以將”硬化”及”焊接，，的步驟分 開進行。 11 200820412 —根據本發明之綠的—觀化方式，晶圓的背面被磨 溥到使金屬栓突出於磨薄的背面的程度。這樣做的好處是 在將半導體晶；j堆疊在—起時，焊料會比較容易與金屬检 形成觸點接通。這種變化方式對於接下來的製作鈍化層的 步驟也是很有利的。接著可以舰化層設置在半導體晶片 ，正们肖面上。接著可以進行鈍化層的表面處理(例如磨 平）。由於金屬栓突出於背面，因此經過表面處理後，金屬 栓會再度露空，並作為與挪轉體晶Μ之背面焊接之用。 “根據本發明之方法的—種實施方式，在將晶圓的背面 磨薄並露出金屬栓後，接著在晶圓的背面上設置-個純化 層。這個鈍化層-方面可以防止焊料與背面上的稽料接 觸’以免$金屬離子渗人⑧材料内。另—方面這個純化層 也可以作為一個焊接停止掩模，以有效防止焊料在焊接過 程中從側面流it}。此外，這佩化層亦有助於提高被磨薄 的半導體晶片的力學穩定性。 根據本發明之方法的一種變化方式，可以將鈍化層設 置在金屬栓之間的空隙，以使金屬栓露出。 可以利用壓模法在晶圓的背面設置鈍化層，這種方法 屬於半導體組裝的一種已知技術。這種方法是將一個壓模 置於晶圓的背面上，然後以一種灌注料將空隙填滿。 一種可行的變化方式是以VPES印製法(VPES:真空印 製封裝系統)製作純化層。 如剷面所述，也可以事後再使金屬栓露出，也就是先 以鈍化層將半導體晶片包括金屬栓在内的整個背面覆蓋 12 200820412 住’然後再將整個背面㈣並使金屬栓露出。此外，也可 以藉由壓模將純化層切下，織再將背面磨薄。 即使所選擇岐具有突出於背面的金屬栓的變化方 式’同時献層的沉積基本上餅生在金屬栓之間的空 隙，將整個背面磨光仍然是有利的，因為這樣可以把金屬 栓弄乾淨。例如金屬栓的表面可能會因為壓模時的放油而 受到污染，因而導致焊接特性變差。 士根據本發明之方法的另外一種實施方式，在磨薄步驟 結束後，對背面進行—鋪晶断料之侵錄大於對金屬 栓之侵錄的·_步驟。這種實施方式也可以達到使 金屬栓突出於背面的目的。這種實施方式對於沒有純化層 及有鈍化層的背面上均適用。 曰此外’種有利的方式是以銅製作敷錢通孔，其方式 疋在將月面磨;|後在背面上進行—非電解的鎳沉積。錄沉 積在金屬栓上並使金屬栓鈍化可以聽形成會對焊接過程 造成妨礙的氧化銅。 本毛明之方去的一種實施方式是從組件堆疊片中切割 出處於堆魏態的組件。這種實施方式的實際作法是將半 :體晶片堆疊在堆疊在一起的晶圓上，而且堆疊方式是以 將一個半導體晶片的作用正面與另外一個半導體晶 =月面黏著在一起’然後再從堆疊在一起的晶圓切割出 堆豐在一起的半導體晶片。 另外種可行的變化方式是將已切割開的半導體 個個堆璺在-起。這種實施方式是先將半導體晶片切 13 200820412 割出來，鎌再堆疊在-起，而且堆疊方式是以灌注料將 一個半導體⑼的作肛面與科—個半導體晶片的背面 黏著在一起。 以下配合圖式及實施例對本發明的内容做進_步的說 明。 。According to the stacking method proposed by the present invention, the solder is applied to the metal filler on the front side before the crystal grain is thinned, and then the back surface of the wafer is formed on the front surface of the wafer. And forming a plated through hole, wherein the exposed metal filler forms a metal test.婉 From the above steps, it is possible to weld the marine product and the ball to the ball. It is difficult to perform on a thin wafer. Therefore, this gamma material can simplify the process and reduce the risk of wafer breakage. An embodiment of the method of the present invention deposits a metallization layer on the entire front surface of the recessed material by a metal filler, and the carrier is placed on the metallization layer. Filling the top of the groove with a level of anti-recording mode, and then turning on the metallization layer in the masking port - the solder is placed on the surface of the solder (4) outside the surface of the photoresist 2 Drop 'and then the tan material _ ball, also heart = 2 after the mask is removed, should not be bitten by the metal filler bit S due to this metal _ resistance technology only need to use a photomasking' The structuring process can be completed in a fresh manner. The customizable method is that after filling the groove with metal, the metal material is welded on the side of the wafer on the side of the wafer; the second groove (10) is metal-on- According to this change, the dip can also be used as a metal anti-scaling mold, after the end of the dip conveying process (that is, in the printing method to send the solder wheel to 200820412 = the domain of the plug) Before or after the removal of the filled layer, the metal layer (4) mask of the through hole is removed. This method of facening requires an additional masking operation using a photo-mask. / According to the implementation of the material of the present invention, the gap between the solder balls on the wafer is filled with the potting material after the solder is melted and the wafer is thinned. In addition to the filling material, after the semiconductor crystal plates are stacked together, the injection between the stacked semiconductor wafers is broken, and the injection of the material also contributes to the improvement of the crystal mechanical stability. It can increase the resistance of the wafer to mechanical changes during molding or during molding. - The lion-like method is to fill the gap with flowing unfilled material. Miscellaneous money is not filled with material. The manufacturing cost is low, and it can be filled in with a commonly known method. Therefore, the use of non-flowing underfill materials can achieve cost reduction. It is also possible to fill the gap between the solder balls by a compression molding method known in the art. This method involves placing a stamper on the wafer, that is, placing it on a solder ball, and then filling the gap with a potting material. It is also possible to bond the semiconductor wafers together with a non-flowing underfill material while filling the voids together with a two-stage heat hardenable material (B-stage material). After stacking the semiconductor wafers together (whether still on an uncleaved wafer or having been diced into a single semiconductor wafer), B is then heated to a certain temperature and adhered to the semiconductor at this temperature. The wafer is then hardened. This step can be carried out simultaneously by using the heating temperature at the time of welding the metal plug. However, the principle of "hardening" and "welding" can be carried out separately. 11 200820412 - According to the green-viewing method of the present invention, the back side of the wafer is ground to cause the metal plug to protrude from the thin back surface. The advantage of this is that when the semiconductor crystals are stacked, the solder will be more easily contacted with the metal. This change is also beneficial for the subsequent steps of making the passivation layer. Then the lining layer can be placed on the semiconductor wafer, and then the surface of the passivation layer can be surface treated (for example, smoothed). Since the metal plug protrudes from the back surface, the metal plug will be exposed again after surface treatment. And as a backside soldering with the spinner. "In accordance with an embodiment of the method of the present invention, after the back side of the wafer is thinned and the metal plug is exposed, then on the back side of the wafer - Purified layers. This passivation layer-side prevents solder from contacting the material on the back side to prevent metal ions from penetrating into the material. On the other hand, this purification layer can also be used as a solder stop mask to effectively prevent solder from flowing from the side during soldering. In addition, this layer of adhesion also helps to improve the mechanical stability of the thinned semiconductor wafer. According to a variant of the method of the invention, a passivation layer can be placed in the gap between the metal plugs to expose the metal plug. A passivation layer can be provided on the back side of the wafer by a stamper method, which is a known technique for semiconductor assembly. This method involves placing a stamp on the back side of the wafer and filling the gap with a potting compound. One possible variation is to make a purification layer by VPES printing (VPES: Vacuum Printing Packaging System). As described in the scooping surface, the metal plug can also be exposed afterwards, that is, the entire back surface of the semiconductor wafer including the metal plug is first covered with a passivation layer, and then the entire back surface (4) is exposed and exposed. Alternatively, the purified layer may be cut by compression molding, and the back surface may be thinned. Even if the selected crucible has a variation of the metal plug protruding from the back side, while the deposition of the layer is substantially the gap between the metal plugs, it is still advantageous to polish the entire back surface, because the metal plug can be cleaned. . For example, the surface of the metal plug may be contaminated by oil discharge during compression molding, resulting in poor welding characteristics. According to a further embodiment of the method according to the invention, after the end of the thinning step, the intrusion of the backside-plating material is greater than the step of invading the metal plug. This embodiment also achieves the purpose of projecting the metal plug from the back. This embodiment is suitable for use on the back side without a purification layer and with a passivation layer. In addition, it is advantageous to make a perforated hole in copper in such a way that it is rubbed on the lunar surface; and then on the back side - electroless nickel deposition. Recording is deposited on the metal plug and the metal plug is passivated to form a copper oxide that would interfere with the soldering process. One embodiment of the present invention is to cut the components in the stack from the stack of components. The practical way of this embodiment is to stack the semi-body wafers on the stacked wafers by stacking the active front side of one semiconductor wafer with another semiconductor crystal = lunar surface. The stacked wafers cut out the stacked semiconductor wafers. Another possible way to change is to stack the semiconductors that have been cut. In this embodiment, the semiconductor wafer is first cut and then stacked, and stacked in such a manner that the anal surface of one semiconductor (9) is adhered to the back side of the semiconductor wafer. The contents of the present invention will be described in the following with reference to the drawings and the embodiments. .

第1圖通過準備以Tsv技術進行連接作業之晶 的一鋪面的斷面圖。如第1圖所示，在晶圓⑴的作用正 面(18)上有設置帶有圓形開口⑶的接觸襯墊⑺。如第2圖 所示’接著可以已知的方法在開口⑶區域形成Θ (4)。這些盲孔(4)帶有—個未姻式中詳細繪出的鈍化層。 接著在晶圓(1)的表面上設置一個種子層⑶。種子層⑺是一 整片很薄的金屬層，而且其覆蓋範圍包括盲孔(4)〔經: 子層(5)可以將電解電壓施加於晶圓⑴的整個表面上。如第 3圖所示’這樣就可以經由電鍍沉積使金屬填料將盲孔⑷ 填滿。 如第4圖所示，接著將一個光致抗鱗模⑺設置在晶 圓⑴的表面上，並選擇性的在掩模開口内沉積出焊料⑻。 如第5圖所示，接著將光致抗鱗模⑺及種子層(5)去 除掉，其中，焊料⑻是作為_掩模 ⑻遮蔽的區域躲，但是在麵焊料⑻遮蔽 的區域，則會將光致抗韻掩模⑺及種子層_刻掉。由於 被作為侧賊之焊料⑻魏⑽金屬填料⑹不會受到餘 刻，因此金屬填料⑹會保持其原先在種子層(5)内^产， 也就是說金屬填料⑹會突出於晶圓⑴的頂面，因而^頂 200820412 ⑻熔化成將頂 面金屬栓⑼。接著經由一姆化步驟將焊料 面金屬栓⑼環繞住的焊料球(10)。 種非流動未充滿材料(11)將烊料球⑽之間的Figure 1 is a cross-sectional view of a tile prepared by a crystal that is connected by Tsv technology. As shown in Fig. 1, a contact pad (7) having a circular opening (3) is provided on the active front surface (18) of the wafer (1). As shown in Fig. 2, then Θ (4) is formed in the region of the opening (3) by a known method. These blind holes (4) carry a passivation layer detailed in the unmarried form. A seed layer (3) is then placed on the surface of the wafer (1). The seed layer (7) is a thin, thin metal layer, and its coverage includes blind holes (4). The sub-layer (5) can apply an electrolysis voltage to the entire surface of the wafer (1). As shown in Fig. 3, the metal filler can be filled with the blind holes (4) by electroplating. As shown in Fig. 4, a photo-resistant scale mold (7) is then placed on the surface of the wafer (1), and solder (8) is selectively deposited in the mask opening. As shown in Fig. 5, the photo-anti-scaling mold (7) and the seed layer (5) are removed, wherein the solder (8) is hidden as a region masked by the mask (8), but in the region where the surface solder (8) is shielded, The photo-resistance mask (7) and the seed layer _ are etched away. Since the solder (8) Wei (10) metal filler (6) is not left as a thief, the metal filler (6) will remain in the seed layer (5), that is, the metal filler (6) will protrude from the wafer (1). The top surface, thus ^ top 200820412 (8) is melted into a top metal plug (9). The solder balls (10) around the solder face metal plugs (9) are then passed through a soldering step. Non-flowing unfilled material (11) will be between the ball (10)

充騎财⑽地妓，該非流動未 =材料⑼是—種在不具有流紐的材料。例如可以用通 二疋作為+導體組件之包封層的材料作為麵動未充滿材 二，也可以用所謂的Β階段黏著劑作為非流動未充滿材 料。這些材_沒錢祕m阿崎由麵法被注 入焊料球⑽之f摘雜。馳触是以—定物方式在益 掩模的情況下賴模以在此處無需細_的 球⑽之上，然後注入非流動未充滿材 、 接著將第7目之晶圓(1)的背面(12)磨薄到至少使金屬 填料⑹露出的程度。這樣就會形成如帛8圖的敷鑛通孔 (13)，接著再經由一個爛步驟選擇性的將晶圓⑴的背面 (12)侧到敷鍍通孔⑽，因而使敷鍍通孔⑽突出於晶圓⑴ 的背面(I2)並形成背面金屬栓。在如第8圖的狀態下就可以 將半導體晶>1堆疊在晶®⑴上，或是如第1G圖所示作為單 一半導體晶片堆疊在一起。例如根據第8圖的配置方式， 一個第一半導體晶片(15)係堆疊在一個第二半導體晶片（16) 之上。 接著對以此種方式堆疊在一起的第一半導體晶片（15) 及苐一半導體晶片（16)進行一個加熱步驟，以便使第一半導 體晶片（15)的焊接球(1〇)與第二半導體晶片（16)的背面金屬 栓(14)連接在一起。 15 200820412 從第ίο圖可以看出，第一半導體晶片（15)的焊接球(1〇) 可能會緊靠在第二半導體晶片（16)的背面(12)上。因此嬋接 球(10)釋出的重金屬離子可能會滲入第二半導體晶片（16)的 石夕材料内。為了避免此一現象之發生，應進行如第9圖所 不的步驟。第9圖所示的步驟是在晶圓的背面(12)上設置 一個鈍化層(17)，但是這個鈍化層(17)並未將背面金屬栓(14) 覆蓋住。設置鈍化層(17)的步驟仍然可以用壓模法來進行。 在晶圓⑴的背面(12)沉積出鈍化層(π)後，可以將背面(12) 再磨光一次，以便將金屬栓(14)的表面弄乾淨，以方便接下 來的焊接作業。 200820412 【圖式簡單說明】 第1圖：通過準備以TSV技術進行連接作業之晶圓的 一個截面的斷面圖。 第2圖：如第1圖之帶有盲孔的晶圓截面的斷面圖。 第3圖：該晶圓截面被種子層覆蓋住且盲孔被填滿的 斷面圖。 、第4圖··該晶圓截面之帶有選擇性在光致抗姓掩模内 沉積出之焊料的斷面圖。 第5圖：該晶圓截面在光致抗姓掩模及種子層被去除 後的斷面圖。 第6圖·該晶圓截面在帶有將熔化成焊料球之焊料時 的斷面圖。 第7圖：該晶圓截面在焊料球之間的空隙被填滿時的 所面圖。 第8圖·該晶圓截面在晶圓被磨薄時的斷面圖。 弟9圖·該晶圓截面在具有一個沉積於背面上之鈍化 層時的斷面圖。 最第10圖：在第8圖之製造步驟結束後的半導體晶片堆 弟11圖·在弟9圖之製造步驟結束後的半導體晶片堆。 17 200820412Filling the money (10) mantle, the non-flowing material = material (9) is a kind of material that does not have a flow. For example, it is possible to use the material of the encapsulating layer of the +conductor component as the surface-unfilled material. It is also possible to use a so-called niobium-stage adhesive as the non-flowing unfilled material. These materials are not included in the solder ball (10). The touch is in the form of a blanket in the case of a benefit mask, on which the ball (10) is not required, and then the non-flowing unfilled material is injected, and then the wafer of the seventh mesh (1) is The back side (12) is thinned to the extent that at least the metal filler (6) is exposed. This will form a perforation via (13) as shown in Fig. 8, and then selectively pass the back side (12) of the wafer (1) to the via (10) via a rotting step, thereby allowing the via (10) Highlights the back side of the wafer (1) (I2) and forms a back metal plug. The semiconductor crystals > 1 may be stacked on the crystals (1) in the state as shown in Fig. 8, or may be stacked as a single semiconductor wafer as shown in Fig. 1G. For example, according to the configuration of Fig. 8, a first semiconductor wafer (15) is stacked on top of a second semiconductor wafer (16). Next, a heating step is performed on the first semiconductor wafer (15) and the first semiconductor wafer (16) stacked in this manner to bond the solder balls (1) of the first semiconductor wafer (15) with the second semiconductor. The back metal plugs (14) of the wafer (16) are connected together. 15 200820412 As can be seen from the figure, the solder balls (1〇) of the first semiconductor wafer (15) may abut against the back side (12) of the second semiconductor wafer (16). Therefore, heavy metal ions released from the ball (10) may penetrate into the stone material of the second semiconductor wafer (16). In order to avoid this phenomenon, the steps as shown in Figure 9 should be performed. The step shown in Figure 9 is to provide a passivation layer (17) on the back side (12) of the wafer, but this passivation layer (17) does not cover the back metal plug (14). The step of providing the passivation layer (17) can still be carried out by compression molding. After the passivation layer (π) is deposited on the back side (12) of the wafer (1), the back surface (12) can be polished again to clean the surface of the metal plug (14) to facilitate the subsequent soldering operation. 200820412 [Simplified description of the drawings] Fig. 1: A cross-sectional view of a cross section of a wafer to be connected by TSV technology. Figure 2: A cross-sectional view of a cross section of a wafer with a blind via as in Figure 1. Figure 3: Sectional view of the wafer cross section covered by the seed layer and the blind holes filled. Figure 4 is a cross-sectional view of the wafer cross-section with solder selectively deposited in the photo-resistance mask. Figure 5: Sectional view of the wafer cross section after the photoreactive mask and seed layer have been removed. Fig. 6 is a cross-sectional view of the wafer cross section with solder to be melted into a solder ball. Fig. 7 is a plan view showing the cross section of the wafer when the gap between the solder balls is filled. Fig. 8 is a cross-sectional view of the wafer cross section when the wafer is thinned. Figure 9 is a cross-sectional view of the wafer cross section with a passivation layer deposited on the back side. Fig. 10 is a view showing the semiconductor wafer stack after the end of the manufacturing step of Fig. 8 and the semiconductor wafer stack after the manufacturing step of Fig. 9 is completed. 17 200820412

_ 【主要元件符號說明】 1 晶圓 2 接觸襯墊 3 襯墊上的開口 4 盲孔 5 種子層/基本金屬化層 6 金屬填料/金屬化層 7 光致抗餘掩模 8 焊料 9 頂面金屬栓 10 焊料球 11 非流動未充滿材料 12 背面 13 敷鍍通孔 14 背面金屬栓 15 第一半導體晶片 16 第二半導體晶片 17 鈍化層 18 作用正面 18_ [Main component symbol description] 1 Wafer 2 Contact pad 3 Opening on pad 4 Blind hole 5 Seed layer / Basic metallization layer 6 Metal filler / metallization layer 7 Photoresistance mask 8 Solder 9 Top surface Metal plug 10 solder ball 11 non-flowing unfilled material 12 back 13 plated through hole 14 back metal plug 15 first semiconductor wafer 16 second semiconductor wafer 17 passivation layer 18 function front surface 18

Claims (1)

200820412 十、申請專利範園： 一御辭導體堆疊的轉體晶片（15; 16)，具有-個 作用正面(18)，該作用正面(18)具有包括接觸襯墊⑺在内 的電路元件，以及具有設置在接觸襯墊⑵之區域的敷鍍 通孔(13) ’在半導體晶片之作用正面⑽及背面(12)上有 設置露空的金屬栓(9 ; ♦同時金屬栓⑼含有-種焊料 (18) ’廷種半導體晶片的特徵為··作用正面⑽上的谭料 ⑻是以騎球⑽_式被設置在金屬栓⑼上同時在 晶圓⑴上的焊料球⑽之間的空隙被一種灌注料⑼填200820412 X. Patent application garden: A rotating wafer (15; 16) with a conductor stack, having an active front surface (18) having a circuit component including a contact pad (7). And a plated through hole (13) having a region disposed in the contact pad (2). A metal plug (9; ♦ at the same time the metal plug (9) is included on the front surface (10) and the back surface (12) of the semiconductor wafer. Solder (18) 'The type of semiconductor wafer is characterized by the fact that the tan (8) on the front side (10) is a gap between the solder balls (10) on the metal plug (9) while being placed on the metal plug (10). Filled with a filling material (9) • y月專利範圍第1項之半導體晶片，其特徵為 料(11)具有黏著性。3. ΓϋΓ範圍第1項或第2項之半導_，其特徵 體晶卿16)的背面⑽具有一個使金屬栓 路空的鈍化層（17)。 4. =請3專利範圍第2項之半導體晶片，其特徵為：鈍化 4 ( 7)是由一種非流動未充滿材料所構成。 如申請專利範圍第2項至第4項中任一項之半導體 片’其特徵為：純化層(17)是由一種聚合物所構成。 如申請專利範圍第2項至第5項中任—項之半導體 片，其特徵為：鈍化層(17)具有黏著性。=導體晶片堆疊，具有—個第—半導體晶片及一個 =弟，半導體晶片之上的第二半導體晶片且堆疊 式為弟二半導體⑽之背面(12)係位於第—半導體晶 灌注 5· 6· 曰曰 曰曰 19 200820412 b 8. 9· 10· 片（15)之作用正面(18)的上方，其中，在這兩個半導體晶 片（15; 16)中都有設置金屬化敷鍍通孔(13)，同時第一半 導體晶片（15)之作用正面(18)上的敷鍍通孔(13)與第二半 導體晶片（16)之背面(12)上的敷鍍通孔(13)藉由焊料(10) 構成的中間連接單元形成導電連接，這種半導體晶片堆 疊的特徵為：第一半導體晶片（15)及第二半導體晶片（16) 之間的空隙被一種以壓模法注入的非流動未充滿材料 (11)填滿。 如申請專利範圍第7項之半導體晶片堆疊，其特徵為： 直接以非流動未充滿材料(11)將第一半導體晶片（15)之 作用正面(18)及第二半導體晶片（16)之背面(12)黏著在一 起。 如申請專利範圍第7項之半導體晶片堆疊，其特徵為： 在第二半導體晶片（16)的背面(12)及作為填充料的非流 動未充滿材料(Π)之間有設置一個由聚合物構成的分隔 層(17)〇 如申請專利範圍第9項之半導體晶片堆疊，其特徵為： 在弟一半導體晶片（15)的背面(12)上有設置一個聚合物 層。 一種將半導體晶片（15 ; 16)堆疊在一起的方法，這種方 法是將一個具有包括接觸襯墊(2)在内之電路元件的晶 圓⑴的作用正面（18)在接觸襯墊(2)之區域設有凹槽 (4)，且凹槽(4)之深度大於晶圓⑴被磨薄之後的高度，為 了製作敷鍍通孔(13)，所以用金屬填料⑹將凹槽⑷填 20 11. 200820412 滿，而且金屬填料⑹含有焊料⑻，因此彼此堆疊在一起 的半導體晶片（I5 ; I6)可以藉由敷鍍通孔㈣及焊料⑻ 彼此形成導1：連接，這種方法的特徵為：焊料⑻是在晶 圓⑴被磨薄之前在作用正面(18)被塗覆到金屬填料⑹ 上，接著再將晶圓⑴之與作用正面(18)相對而立的背面 (12) 磨薄’並使金屬填料⑹從背面露空及形成敷鑛通孔 (13) ，其中，露空的金屬填料(6)形成金屬检(14)。 12. 如申請專利範圍第n項之方法，其特徵為：以金屬填料 將凹槽⑷填滿使得在晶圓⑴的整個作用正面⑽上沉積 出-個金屬化層⑹，接著在金屬化層⑹上設置一個在被 金屬填料填滿之凹槽⑷上方具有掩模開口的光致抗餘 掩模⑺，接著在掩模開口内藉由在金屬化層(5)上接通一 個，壓以電鍍方式沉積出焊料⑻，接著將位於被焊料⑻ 覆蓋住的面積之外的光致抗蝕掩模(7)及金屬化層(句去 除掉，然後再將焊料(8)溶化成焊料球(1〇)。 13. 如申請專利範圍第n項之方法，其特徵為：在以金屬將 凹槽(4)填滿後’經由一個焊料輸送過程在晶圓⑴的作用 正面（18)上將焊料(8)設置在凹槽(4)内的金屬填料(6) 上’然後再將焊料⑻熔化成焊料球(10)。 14. 如申請專利範圍第n項至第13項中任一項之方法其 特徵為：在將焊料溶化之後及將晶圓⑴磨薄之前以灌注 料(11)將晶圓⑴上之焊料球⑽之間的空隙填滿。 15. 如申請專利範圍第14項之方法，其特徵為：以一種非流 動未充滿材料(11)將空隙填滿。 21 2〇〇82〇412 •如申凊專利範圍第15項之方法，其特徵為··將一個壓模 置於晶圓⑴上，然後以一種灌注料將空隙填滿。 Π·如申請專利範圍第14項至第16項中任一項之方法，其 特徵為：以一起二階段可熱硬化材料(Β階段材料)將空 隙填滿。 ， 18.如申請專利範圍第11項至第17項中任一項之方法，其 k 特徵為：將晶圓(1)的背面(12)磨薄到使金屬栓(14)突出於 磨薄的背面(12)的程度。 •如申睛專利範圍第11項至第18項中任一項之方法，其 特徵為·在將晶圓(1)的背面(12)磨薄並露出金屬栓(14) 後，接著在晶圓(1)的背面(12)上設置一個鈍化層(17)。 2〇.如申請專利範圍第18項及第19項之方法其特徵為： 在金屬栓(H)之間的空隙有設置一個由聚合物構成的鈍 化層(17)。 ^ 如申明專利範圍第20項之方法，其特徵為：將一個壓模 置於晶圓(1)的背面(12)上，然後以一種灌注料將空隙填 滿。 22. 如申請專利範圍第20項之方法，其特徵為：以VpES 印製法(VPES :真空印製封裝系統)製作鈍化層(17)。 23. 如申請專利範圍第19項至第22項中任一項之方法，其 特徵為：先以純化層(17)將半導體晶片包括金屬栓(14) 在内的整個背面(I2)覆蓋住，然後再將整個背面(12)磨薄 並使金屬栓(14)露出。 4.如申明專利範圍第23項之方法，其特徵為··在磨薄步驟 22 200820412 '、、。東後對g面(12)進行一種對晶圓(i)材料之侵钱性大 於對金屬栓(14)之侵蝕性的電漿蝕刻步驟。 5·如申明專利氣圍第23項或第％項之方法，其特徵為： 敷锻通孔(13)疋由銅製成，並在磨薄步驟結束後 ’在背 面(12)進行一非電解的鎳沉積。 26·如申請專利範圍第14項至第22項中任一項之方法，其 =徵為：將半導體晶片（15; 16)堆疊在堆疊在一起的晶 二(1)上，而j_堆疊方式是以灌注料將—個半導體晶片⑽ =用正面⑽與另外—個半導體晶片⑽的背面⑽黏 考一起，然後再從堆疊在一起的晶圓⑴切割出堆疊在 一起的半導體晶片（15 ;16、〇• The semiconductor wafer of item 1 of the y patent of the y-month is characterized in that the material (11) is adhesive. 3. The semi-conductor of the first or second item of the range ,, characterized by the back surface (10) of the body crystal 16) has a passivation layer (17) that allows the metal to be bolted. 4. = 3 The semiconductor wafer of item 2 of the patent scope is characterized in that passivation 4 (7) is composed of a non-flowing underfill material. The semiconductor wafer according to any one of claims 2 to 4 is characterized in that the purification layer (17) is composed of a polymer. A semiconductor wafer according to any one of claims 2 to 5, characterized in that the passivation layer (17) has adhesiveness. = a conductor wafer stack having a first semiconductor wafer and a second semiconductor wafer, and a stacked semiconductor wafer (10) on the back side (12) of the second semiconductor (10) is located in the first semiconductor crystal perfusion 5·6·曰曰曰曰19 200820412 b 8. 9· 10· The role of the sheet (15) is above the front side (18), in which the metallized plated through holes are provided in the two semiconductor wafers (15; 16) 13) at the same time, the first semiconductor wafer (15) acts on the plated through hole (13) on the front side (18) and the plated through hole (13) on the back side (12) of the second semiconductor wafer (16) The intermediate connection unit formed by the solder (10) forms an electrically conductive connection, and the semiconductor wafer stack is characterized in that the gap between the first semiconductor wafer (15) and the second semiconductor wafer (16) is injected by a compression molding method. The flow of unfilled material (11) is filled. The semiconductor wafer stack of claim 7 is characterized in that: the first semiconductor wafer (15) is directly applied to the front side (18) and the back side of the second semiconductor wafer (16) by a non-flowing underfill material (11). (12) Adhered together. The semiconductor wafer stack of claim 7 is characterized in that: a polymer is disposed between the back surface (12) of the second semiconductor wafer (16) and the non-flowing underfill material (Π) as a filler. A separator layer (17) is constructed, for example, in the semiconductor wafer stack of claim 9 characterized in that: a polymer layer is provided on the back surface (12) of the semiconductor wafer (15). A method of stacking semiconductor wafers (15; 16) together by applying a wafer (1) having a circuit component including a contact pad (2) to the front side (18) of the contact pad (2) The area is provided with a groove (4), and the depth of the groove (4) is greater than the height after the wafer (1) is thinned. To make the plated through hole (13), the groove (4) is filled with the metal filler (6). 20 11. 200820412 is full, and the metal filler (6) contains solder (8), so the semiconductor wafers (I5; I6) stacked on each other can be connected to each other by the plated through holes (4) and the solder (8). The solder (8) is applied to the metal filler (6) on the active front side (18) before the wafer (1) is thinned, and then the back side (12) of the wafer (1) opposite the active front side (18) is thinned. 'The metal filler (6) is exposed from the back side and forms a through hole (13), wherein the exposed metal filler (6) forms a metal test (14). 12. The method of claim n, characterized in that the recess (4) is filled with a metal filler such that a metallization layer (6) is deposited on the entire active front surface (10) of the wafer (1), followed by a metallization layer. (6) providing a photo-resistance mask (7) having a mask opening above the recess (4) filled with the metal filler, and then pressing one on the metallization layer (5) in the mask opening, pressing The solder (8) is deposited by electroplating, and then the photoresist mask (7) and the metallization layer outside the area covered by the solder (8) are removed (the sentence is removed, and then the solder (8) is melted into a solder ball ( 1〇). 13. The method of claim n, characterized in that after filling the groove (4) with metal, 'on the active front side (18) of the wafer (1) via a solder transfer process Solder (8) is placed on the metal filler (6) in the recess (4) and then the solder (8) is melted into a solder ball (10). 14. As in any of items n to 13 of the patent application scope The method is characterized in that the wafer (1) is soldered with a potting material (11) after the solder is melted and before the wafer (1) is thinned. The gap between the balls (10) is filled. 15. The method of claim 14, characterized in that the void is filled with a non-flowing underfill material (11). 21 2〇〇82〇412 • The method of claim 15 is characterized in that: a stamper is placed on the wafer (1), and then the void is filled with a potting material. Π·If the patent scope is in items 14 to 16, A method according to any one of the preceding claims, characterized in that the voids are filled with a two-stage heat-hardenable material (the Β-stage material), and the method of any one of claims 11 to 17, k is characterized by: thinning the back side (12) of the wafer (1) to the extent that the metal plug (14) protrudes from the thin back surface (12). • In the 11th to 18th items of the patent scope A method according to any one of the preceding claims, characterized in that after the back surface (12) of the wafer (1) is thinned and the metal plug (14) is exposed, a passivation layer is then provided on the back surface (12) of the wafer (1). (17). The method of claim 18 and 19 is characterized in that: the space between the metal plugs (H) is provided by a polymer structure A passivation layer (17). ^ The method of claim 20, characterized in that a stamper is placed on the back side (12) of the wafer (1), and then the void is filled with a potting material. 22. The method of claim 20, characterized in that the passivation layer (17) is produced by VpES printing (VPES: Vacuum Printing and Packaging System). 23. If the patent scope is 19 to 22 A method according to any one of the preceding claims, characterized in that the entire surface (I2) of the semiconductor wafer including the metal plug (14) is covered with a purification layer (17), and then the entire back surface (12) is thinned and The metal plug (14) is exposed. 4. The method of claim 23, characterized in that it is in the step of thinning 22 200820412 ', . The east side of the g-plane (12) is subjected to a plasma etching step that is more aggressive to the wafer (i) material than to the metal plug (14). 5. The method of claim 23, or the method of claim 2, wherein the forging hole (13) is made of copper and is subjected to a non-electrolysis on the back side (12) after the thinning step is completed. Nickel deposition. The method of any one of claims 14 to 22, wherein the semiconductor wafer (15; 16) is stacked on the stacked crystals (1), and the j_stack The method is to sandwich a semiconductor wafer (10) = with the front side (10) and the back side (10) of another semiconductor wafer (10), and then cut the stacked semiconductor wafers from the stacked wafers (1) (15; 16, 〇 而且堆疊方式是以灌注料將一個半導體晶 22項中任一項之方法，其 F體晶片（15 ; 16)，然後再 片（15)的作用正面(18)與另外一個半導體 (12)黏著在一起。 23Moreover, the stacking method is a method in which one of the semiconductor crystals 22 is filled by a potting material, and the F-body wafer (15; 16), and then the sheet (15) acts on the front side (18) and adheres to another semiconductor (12). Together. twenty three
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